CN102035555B - Analog digital converter, conversion method and digital power supply controller adopting analog digital converter - Google Patents
Analog digital converter, conversion method and digital power supply controller adopting analog digital converter Download PDFInfo
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- CN102035555B CN102035555B CN 201010612571 CN201010612571A CN102035555B CN 102035555 B CN102035555 B CN 102035555B CN 201010612571 CN201010612571 CN 201010612571 CN 201010612571 A CN201010612571 A CN 201010612571A CN 102035555 B CN102035555 B CN 102035555B
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Abstract
The invention provides an analog digital converter, a conversion method and a digital power supply controller adopting the analog digital converter. Under the control of a first clock signal, a trigger samples analog voltage within the previous clock cycle T and samples reference voltage within the next clock cycle T, wherein the sampling time of the trigger is controlled by a clock signal which is generated by a primary delay locked loop. Thus, analog-digital conversion can be completed within two clock cycles T; and the sampling frequency of the analog digital converter is two times the internal clock frequency due to reciprocal relation between the clock cycle and the internal clock frequency. Therefore, compared with that of the conventional analog digital converter, the internal clock frequency of the analog digital converter is greatly reduced under the same sampling frequency, so that the power consumption can be reduced, and the analog digital converter is easy to implement on a circuit.
Description
Technical field
The present invention relates to the modulus conversion technique field, particularly a kind of analog to digital converter, conversion method and use its digital power controller.
Background technology
It is digital signal that analog to digital converter (ADC, Analog Digital Converter) is used for analog signal conversion, supplies digital circuit to handle, and therefore is widely used in the various electronic circuits.
ADC can be divided into slope type, successive approximation, parallel relatively type etc. according to its work characteristics.Wherein slope type ADC comprises single-slope type and dual slope type (biproduct somatotype).Dual slope type ADC since structural characteristics eliminated because the non-linear error of bringing of slope circuit, therefore than single-slope type ADC use more extensive.
Introduce the operation principle of the two slope ADC in traditional N position below in conjunction with Fig. 1, referring to Fig. 1, this figure is the sketch map of traditional two slope ADC.
This ADC comprises positive integrator 101, comparator 102, digital control logic circuit 103 and N digit counter 104.Wherein, N has represented the conversion accuracy of ADC, and N is big more, and the conversion accuracy of ADC is high more.
This ADC has the two-way input signal, is respectively v
In *(V
REF).Positive integrator 101 is selected the two-way input signal is carried out integration respectively through switch 1 and switch 2.Integral result v
IntWith sampled voltage lower limit V
ThRespectively as two input signals of comparator 102.Comparator 102 is v relatively
IntAnd V
ThThe output comparative result is given digital control logic circuit 103, and digital control logic circuit 103 is counted according to the comparative result control counter, thus the result of output ADC; The result of ADC is a binary data, thereby the analog signal conversion of accomplishing input is a digital signal.
Fig. 2 is the working waveform figure of the ADC of Fig. 1.Wherein, ordinate is the integral result v of positive integrator
Int, abscissa is time t.V
ThBe the lower limit that adopts voltage, V
Th+ V
REFIt is the upper limit of sampled voltage.
This N position course of work of ADC in a sampling period is following:
1,0-t
0Stage: ADC is by zero clearing, v
Int=0.Begin reseting stage then, positive integrator 101 is started working v
IntBeginning increases, until v
Int=V
Th
2, t
1Stage: t
0Constantly, switch 1 closure, v
In *At N
REFIndividual clock cycle integrates is equivalent to the electric capacity charging, and comparator 102 is output as height.At t1 moment v
IntFor:
v
int(t
1)＝K·N
REFT·v
in *+v
th (1)
Wherein, K is an integral coefficient, and T is the clock cycle, N
REFBe clock cycle number, wherein N
REF=2
N
3, in t2 stage: the t1 moment, switch 1 is opened, switch 2 closures, (V
REF) the beginning integration, be equivalent to capacitor discharge.Because |-V
REF|＞| v
In *|, so v
IntAll the time can be discharged to V
Th, used clock cycle number is N
Out, this moment, comparator was put low.At t2 constantly, v
Int(t
2)=V
Th, at t1 moment v
IntFor:
v
int(t
2)＝v
int(t
1)-K·N
outT·V
REF＝V
th (2)
With promptly getting in formula (2) the substitution formula (1):
N
out＝(N
REF×v
in *)/V
REF＝(2
N×v
in *)/V
REF (3)
N
OutBe analog signal v
In *Convert the pairing binary number of digital signal into.
Can find out to traditional N position dual slope type ADC job analysis that in conjunction with Fig. 2 the charging interval is N in the one-period
REFT, be N discharge time
REFT, therefore, the internal clocking frequency f of ADC
ClkWith sample frequency f
SampleRelation be: f
Clk=f
Sample* 2N * 2.
Suppose f
SampleBe 1MHz, the conversion accuracy N of ADC is 10, then uses traditional N position dual slope type ADC, its f
ClkUp to 1GHz, high f like this
ClkRealize all difficult the realization in power consumption and circuit.Therefore the range of application of traditional dual slope type ADC based on counter is very limited, and it goes for the lower occasion of frequency, and the upper frequency occasion is difficult to be realized.
Summary of the invention
The technical problem that the present invention will solve provides a kind of analog to digital converter, conversion method and uses its digital power controller, can dwindle the multiple between sample frequency and the internal clocking frequency.
The present invention provides a kind of analog to digital converter, comprising: voltage time change-over circuit, the first trigger group, change-over circuit, clock generating circuit and first delay phase-locked loop;
Clock generating circuit is used to receive the external clock input signal, produces first clock signal, second clock signal and the 3rd clock signal; Said second clock signal is as the input clock of first delay phase-locked loop, and said the 3rd clock signal is as the reference clock of first delay phase-locked loop, and the difference of said input clock and reference clock is clock cycle T;
The voltage time change-over circuit; Be used to receive aanalogvoltage and reference voltage; Under the control of first clock signal; Convert said aanalogvoltage into square-wave signal in the previous clock cycle T, convert said reference voltage into square-wave signal in the back clock cycle T, said square-wave signal and said aanalogvoltage are linear;
Said first delay phase-locked loop is used for the difference of said input clock and reference clock is divided into M delay time lag, M clock signal of corresponding generation; M >=2;
The said first trigger group; Comprise M trigger; A said M clock signal connects the input end of clock of M trigger respectively, and the input of each trigger connects said square-wave signal, and each trigger is at the said square-wave signal of control down-sampling of separately clock signal; The output of each trigger connects the different inputs of said change-over circuit respectively;
Said change-over circuit, the output conversion of signals that is used for said trigger is the corresponding digital signal of said aanalogvoltage.
Preferably, said first delay phase-locked loop comprises phase discriminator, a charge pump and M delay cell;
The first input end of said phase discriminator connects said reference clock;
The output of said phase discriminator connects the input of said charge pump, and said electric charge delivery side of pump connects the first input end of each delay cell;
The output of previous delay cell connects second input of a back delay cell; Second input of first delay cell connects said input clock, and the output of last delay cell connects second input of said phase discriminator;
Said phase discriminator is used for the output signal and the reference clock of last delay cell of comparison, and comparative result is exported to said charge pump;
Said charge pump is used for regulating output voltage according to said comparative result, to regulate each delay cell, the output signal of last delay cell and reference clock is realized synchronously.
Preferably, a said M trigger is d type flip flop;
The input end of clock of each d type flip flop connects the output of corresponding delay cell;
Each d type flip flop said square-wave voltage that is used to sample;
The output of each d type flip flop connects the different inputs of said change-over circuit respectively.
Preferably, said M is 2
NWherein N is the conversion accuracy of analog to digital converter ADC.
Preferably, a said M delay time lag is identical.
Preferably, said M delay time lag is different.
Preferably, also comprise n the delay phase-locked loop identical, be respectively second level delay phase-locked loop, third level delay phase-locked loop, up to (n+1) level delay phase-locked loop with said first order delay phase-locked loop structure; Also comprising n delay phase-locked loop corresponding n the trigger group identical with the said first trigger group structure, is respectively the second trigger group, and the 3rd trigger group is up to (n+1) trigger group; N >=1;
The output of any two delay cells of said first order delay phase-locked loop connects the reference clock and the input clock of second level delay phase-locked loop respectively; The output of any two delay cells of second level delay phase-locked loop connects the reference clock and the input clock of third level delay phase-locked loop respectively; The reference clock and the input clock that connect (n+1) level delay phase-locked loop up to the output of any two delay cells of n level delay phase-locked loop respectively;
The output of each delay cell of every grade of delay phase-locked loop connects the input end of clock of the trigger in the corresponding trigger group; The input of each trigger in every group of trigger all connects said square-wave signal, and the output of each trigger in every group of trigger connects the different inputs of said change-over circuit respectively.
Preferably, said voltage time change-over circuit comprises: selector switch, integrator and comparator;
The input of said selector switch connects aanalogvoltage, reference voltage and voltage source, is used under the control of said first clock signal, selects the voltage of input to export at output;
The input of said integrator connects the output of said selector switch, is used for the first input end that signal with input carries out exporting to behind the integration comparator;
Said comparator is used for the output signal of integrator and the lower limit of sampled voltage are compared, and the output comparative result is given said each trigger.
The present invention also provides a kind of D conversion method, may further comprise the steps:
Receive the external clock input signal, produce first clock signal, second clock signal and the 3rd clock signal; The difference of said second clock signal and the 3rd clock signal is clock cycle T;
Receive aanalogvoltage and reference voltage, under the control of first clock signal, convert the aanalogvoltage in the said reference voltage range into square-wave signal, said square-wave signal and said aanalogvoltage are linear;
The difference T of second clock signal and the 3rd clock signal is divided into M delay time lag, corresponding M the clock signal of the first order that produce; M >=2;
Under the control of a said first order M clock signal, said square-wave signal is sampled;
With the conversion of signals after the sampling is the corresponding digital signal of said aanalogvoltage.
Preferably, comprise that also the difference with any two clock signals of a first order M clock signal is divided into n
1Individual delay time lag, the corresponding second level n that produces
1Individual clock signal is at said second level n
1Under the control of individual clock signal said square-wave signal is sampled; N wherein
1>=2;
With second level n
1The difference of any two clock signals of individual clock signal is divided into n
2Individual delay time lag, the corresponding third level n that produces
2Individual clock signal is at said third level n
2Under the control of individual clock signal said square-wave signal is sampled; Wherein, n
2>=2;
Up to n level n
(n-1)The difference of any two clock signals of individual clock signal is divided into n
nIndividual delay time lag, corresponding (n+1) level n that produces
nIndividual clock signal is at said (n+1) level n
nUnder the control of individual clock signal said square-wave signal is sampled; Wherein, n
n>=2;
With the conversion of signals after all samplings is the corresponding digital signal of said aanalogvoltage.
Preferably, said M is 2
NWherein N is the conversion accuracy of analog to digital converter ADC.
Preferably, a said first order M delay time lag is identical.
Preferably, said first order M delay time lag is different.
The present invention also provides a kind of digital power controller, comprises described analog to digital converter, also comprises: power stage circuit, feedback circuit, error amplifier, digital pulse width adjuster and drive circuit;
Said feedback circuit is used to gather the output signal of said power stage circuit, and the analog signal of gathering is fed back to said analog to digital converter;
Said analog to digital converter, being used for said analog signal conversion is digital signal, is sent to an input of said error amplifier;
Said error amplifier is used for said digital signal and numerical reference signal are compared, and comparative result is sent to said digital pulse width adjuster;
Said digital pulse width adjuster is used for sending a control signal to said drive circuit according to said comparative result;
Said drive circuit is used for driving according to said control signal the switch motion of the switching device of said power stage circuit, to regulate the output signal of said power stage circuit.
Compared with prior art, the present invention has the following advantages:
ADC provided by the invention is under the control of first clock signal; In previous clock cycle T, aanalogvoltage is sampled; In next clock cycle T, reference voltage is sampled; Concrete sampling is accomplished by trigger, and the sampling time of trigger is to be controlled by the clock signal that first order delay phase-locked loop produces.In two clock cycle T, just can accomplish analog-to-digital conversion like this, because clock cycle and internal clocking frequency are reciprocal relations, therefore, the relation of the sample frequency of this ADC and internal clocking frequency is two times a relation.Under identical sample frequency, ADC of the present invention reduces with respect to the internal clocking frequency of traditional ADC greatly, can reduce power consumption so like this, and also realizes easily on the circuit.
Description of drawings
Fig. 1 is the sketch map of traditional two slope ADC;
Fig. 2 is the working waveform figure of the ADC of Fig. 1;
Fig. 3 is embodiment one structure chart of ADC provided by the invention;
Fig. 4 is the sketch map of another embodiment of ADC provided by the invention;
Fig. 5 is the oscillogram of the output signal of integrator provided by the invention;
Fig. 6 is that each main signal of the present invention is at (t
1-t
2) interior oscillogram of time period;
Fig. 7 is the sample waveform figure of each delay cell in the present invention's first order delay phase-locked loop shown in Figure 4;
Fig. 8 is the sequential comparison diagram of ADC provided by the invention and traditional ADC;
Fig. 9 is the another example structure figure of ADC provided by the invention;
Figure 10 is the oscillogram of the output signal of the corresponding delay cell of Fig. 9 of the present invention;
Figure 11 is the not corresponding simultaneously oscillogram of delay time lag between the delay cell of the present invention;
Figure 12 is D conversion method embodiment one flow chart provided by the invention;
Figure 13 is the structure chart of digital power controller embodiment provided by the invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
The ADC that the embodiment of the invention provides utilizes delay phase-locked loop to replace the counter among traditional ADC, thereby makes the internal clocking frequency of ADC and the relation that sample frequency only is two times, can reduce ADC internal clocking frequency like this, thereby expands the application scenario of ADC.
Referring to Fig. 3, this figure is embodiment one structure chart of ADC provided by the invention.
The ADC that present embodiment provides comprises: voltage time change-over circuit 100, the first trigger group 200, change-over circuit 300, clock generating circuit 400 and first delay phase-locked loop 500.
Voltage time change-over circuit 100 is used to receive aanalogvoltage and reference voltage, under the control of first clock signal, converts the aanalogvoltage in the said reference voltage range into square-wave signal, and said square-wave signal and said aanalogvoltage are linear;
Said first delay phase-locked loop 500 is used for said T is divided into M delay time lag, M clock signal of corresponding generation; M >=2;
The said first trigger group 200; Comprise M trigger; A said M clock signal connects the input end of clock of M trigger respectively, and the input of each trigger connects said square-wave signal, and each trigger is at the said square-wave signal of control down-sampling of separately clock signal; The output of each trigger connects the different inputs of said change-over circuit respectively;
Said change-over circuit 300, the output conversion of signals that is used for said trigger is the corresponding digital signal of said aanalogvoltage.
ADC provided by the invention is under the control of first clock signal; In previous clock cycle T, aanalogvoltage is sampled; In next clock cycle T, reference voltage is sampled; Concrete sampling is accomplished by trigger, and the sampling time of trigger is to be controlled by the clock signal that first order delay phase-locked loop produces.In two clock cycle T, just can accomplish analog-to-digital conversion like this, because clock cycle and internal clocking frequency are reciprocal relations, therefore, the relation of the sample frequency of this ADC and internal clocking frequency is two times a relation.Under identical sample frequency, ADC of the present invention reduces with respect to the internal clocking frequency of traditional ADC greatly, can reduce power consumption so like this, and also realizes easily on the circuit.
Need to prove that said M is as long as be the integer more than or equal to 2, but for ease, M can be taken as 2
NWherein N is the conversion accuracy of analog to digital converter ADC.
Need to prove that a said M delay time lag can be identical, also can be different.
Be 2 all in following examples with M
NFor example is introduced.
Introduce the inside physical circuit of ADC provided by the invention below, referring to Fig. 4, this figure is the sketch map of another embodiment of ADC provided by the invention.
First delay phase-locked loop 500 that present embodiment provides comprises phase discriminator 502, charge pump 503 and 2
N Individual delay cell 501;
The first input end of said phase discriminator 502 connects said reference clock clk
Ref
The output of said phase discriminator 502 connects the input of said charge pump 503, and the output of said charge pump 503 connects the first input end of each delay cell 501;
The output of previous delay cell connects second input of a back delay cell; Second input of first delay cell connects said input clock clk
Delay, the output of last delay cell connects second input of said phase discriminator 502;
Said phase discriminator 502 is used for the output signal and the reference clock clk of last delay cell of comparison
Ref, comparative result is exported to said charge pump 503;
Said charge pump 503 is used for regulating output voltage according to said comparative result, to regulate each delay cell 501, makes the output signal and the reference clock clk of last delay cell
RefRealize synchronously.
Present embodiment provide 2
NIndividual trigger is d type flip flop 201;
The input end of clock of each d type flip flop 201 connects the output of corresponding delay cell 501;
Each d type flip flop 201 said square-wave voltage that is used to sample; That is, each d type flip flop 201 input connects the output of voltage time change-over circuit;
The output of each d type flip flop 201 connects the different inputs of said change-over circuit 300 respectively.
Said voltage time change-over circuit 100 comprises: selector switch 101, integrator 102 and comparator 103;
The input of said selector switch 101 connects aanalogvoltage, reference voltage and voltage source, is used at the said first clock signal clk
SwitchControl under, select the voltage of input to export at output;
The input of said integrator 102 connects the output of said selector switch 101, is used for the first input end that signal with input carries out exporting to behind the integration comparator 103;
Introduce the operation principle of voltage time change-over circuit below in conjunction with the oscillogram of the output signal of integrator.
Referring to Fig. 5, this figure is the oscillogram of the output signal of integrator provided by the invention.
The work of integrator 102 be divided into reset, input voltage v
InCharging and reference voltage-V
REFThe discharge three phases, integrator 102 work wave v
IntAs shown in Figure 5, V
ThBe the lower limit of analog to digital converter sampled voltage scope, V
REF+ V
ThBe the upper limit of analog to digital converter sampled voltage scope, T is an input clock cycle.
1,0-t
0Stage: circuit is initially by zero clearing, v
Int=0.Begin reseting stage then, switch 0 closure, integrator 102 is started working, and integration is to v
Int=V
Th, switch 0 breaks off.
2, t
0-t
1Stage: t
0Constantly, switch 1 closure, v
InAn input clock cycle T integrates, be equivalent to the electric capacity charging, comparator 103 is output as height.At t
1Shi Keyou:
v
int(t
1)＝K·T·v
in+V
th (4)
Wherein K is an integral coefficient.
3, t
1-t
2Stage: t
1Constantly, switch 1 is opened, switch 2 closures ,-V
REFIn an input clock cycle T, begin integration, be equivalent to capacitor discharge.Because |-V
REF|＞| v
In|, so v
IntAll the time can be discharged to V
Th, comparator 103 is output as low.At t
2Constantly, v
Int(t
2)=V
ThSo, have:
v
int(t
2)＝v
int(t
1)-K·(t
2-t
1)·V
REF＝V
th (5)
With formula (5) substitution formula (4), promptly get:
(t
2-t
1)/T＝v
in/V
REF (6)
Can obtain input voltage v according to formula (6)
InWith (t discharge time
2-t
1) between relation, can be time quantum with voltage transitions through this mode.
With reference to figure 6, this figure is that each main signal is at (t
1-t
2) interior oscillogram of time period.
Clk
RefStipulated the terminal point of time of delay, clk
DelayAnd clk
RefBetween time phase difference be T, show that promptly the whole piece delay line is T in condition following time of delay of locking.V
CompFor the output of comparator in the analog to digital converter 103, from t
1Constantly begin the output signal V of comparator 103
CompThe time interval of high level be (t
2-t
1), and with input voltage v
InCorresponding relation in the formula (6) is arranged.
Referring to Fig. 7, this figure is the sample waveform figure of each delay cell in the first order delay phase-locked loop shown in Figure 4.
Present embodiment is 3 with N, then 2
NBe 8, corresponding 8 delay cells 501 and 8 d type flip flops 201.
v
C1-v
C8The output waveform of 8 delay cells 501 of expression.
V wherein
C8The output waveform of representing last delay cell 501, its output is through phase discriminator 502 and reference clock clk
RefCompare, comparative result is used to regulate the output voltage of charge pump 503, and then the delay of control lag unit, reaches the effect of lock phase through such negative feedback operation.
When first order delay phase-locked loop 500 reaches phase locked state, v
C8Rising edge constantly and reference clock clk
RefRising edge constantly identical, i.e. v
C8With clk
RefKeep synchronously.
v
C1-v
C7As each d type flip flop 201 that clock signal connects in the correspondence with it shown in rising edge time trigger Fig. 4, the output signal V of each trigger 201 these comparator 103 constantly of sampling
CompThe output Q1-Q8 of trigger 201 forms 8 digit numeric codes.The number of " 1 " has just been represented time (t in 8 digit numeric codes
2-t
1), according to the record of formula (6), by (t
2-t
1) can obtain aanalogvoltage v
InNumerical value, its precision is 3.Convert digital code into binary code through change-over circuit 300 at last, with the corresponding binary digital signal of output aanalogvoltage.
Referring to Fig. 8, this figure is the sequential comparison diagram of ADC provided by the invention and traditional ADC.
As can be seen from Figure 8, ignore T resetting time
Reset, the sampling period of integrator is 2T, and the sampling period of traditional ADC is 2N
REFT is because N
REF=2
NT, therefore, traditional ADC sampling time is (2
N* 2) T.
For reaching identical sample conversion speed and conversion accuracy, be 1MS/s with sample conversion speed, conversion accuracy is 8 and is example, because sampling period and sample frequency are relations reciprocal, therefore:
Adopt the relation of traditional ADC internal clocking frequency and sample frequency to be:
f
clk＝f
sample×2
N×2＝1M×2
8×2＝512MHz
Adopt the relation of ADC internal clocking frequency of the present invention and sample frequency to be:
f
clk＝f
sample×2＝1M×2＝2MHz
This shows, same sample frequency (1M), the internal clocking frequency that needs for traditional ADC is 512M, and only needs 2M for ADC provided by the invention.To reduce the power consumption of adc circuit like this, and realize easily also on the hardware circuit that therefore, the application scenario of ADC provided by the invention is compared than the application scenario of traditional ADC and is expanded.
Referring to Fig. 9, this figure is the another example structure figure of ADC provided by the invention.
Only comprise first order delay phase-locked loop among the ADC shown in Figure 4; It is understandable that; Can also comprise n the delay phase-locked loop identical, be respectively second level delay phase-locked loop, third level delay phase-locked loop, up to (n+1) level delay phase-locked loop with said first order delay phase-locked loop structure; Also comprising n delay phase-locked loop corresponding n the trigger group identical with the said first trigger group structure, is respectively the second trigger group, and the 3rd trigger group is up to (n+1) trigger group; N >=1;
The output of any two delay cells of said first order delay phase-locked loop connects the reference clock and the input clock of second level delay phase-locked loop respectively; The output of any two delay cells of second level delay phase-locked loop connects the reference clock and the input clock of third level delay phase-locked loop respectively; The reference clock and the input clock that connect (n+1) level delay phase-locked loop up to the output of any two delay cells of n level delay phase-locked loop respectively;
The output of each delay cell of every grade of delay phase-locked loop connects the input end of clock of the trigger in the corresponding trigger group; The input of each trigger in every group of trigger all connects said square-wave signal, and the output of each trigger in every group of trigger connects the different inputs of said change-over circuit respectively.
Fig. 9 is to comprise that the two-stage delay phase-locked loop is that example describes.
Among Fig. 9 with the output of two adjacent in the first order delay phase-locked loop 500 delay cells as second level delay phase-locked loop 500 " input clock clk '
DelayWith reference clock clk '
Ref, it is understandable that the output that also can use non-conterminous two delay cells is as delay phase-locked loop 500 " input clock clk '
DelayWith reference clock clk '
Ref
The input of first delay cell in the second level delay phase-locked loop 500 ", wherein, the output of first delay cell in the first order delay phase-locked loop 500 connects second level delay phase-locked loop 500 ";
The output of second delay cell in the first order delay phase-locked loop 500 connects second level delay phase-locked loop 500 " in the first input end of phase discriminator 902;
The output of phase discriminator 902 connects the input of charge pump 903, and the output of charge pump 903 connects second level delay phase-locked loop 500 " in the first input end of each delay cell.
It is understandable that second level delay phase-locked loop 500 " in the output of each delay cell connect the input end of clock of the trigger in the second corresponding trigger group respectively.
" and the operation principle of the second corresponding trigger group is identical with the operation principle of the first order delay phase-locked loop 500 and the first trigger group, repeats no more at this to need to prove second level delay phase-locked loop 500.
For some sample circuit application scenario, only need it in some less voltage ranges, to reach higher sample conversion precision, in whole input range, do not need all to have identical high precision.DC-to-dc (DC-DC) switching controller in the digital power controller for example; Output voltage through dividing potential drop then sample conversion be digital signal; Digital signal compares with a digital reference quantity, controls the duty ratio of switch element in DC-to-dc (DC-DC) transducer after the error signal that obtains is calculated through digital compensation.When this DC-to-dc (DC-DC) when transducer is in stable state, the digital signal that sampling obtains is very approaching with the digital reference amount, and the sample conversion precision is high more, means that the difference of error signal is more little, and the direct current output accuracy is also just high more.And with the bigger voltage range of the voltage difference of digital reference amount representative in, reaching same high precision does not obviously have very big meaning, lower sampling precision also allows.The ADC that therefore, just can be used for this structure shown in Figure 9 for this occasion.
Referring to Figure 10, this figure is the oscillogram of the output signal of the corresponding delay cell of Fig. 9.
v
C1, v
C2, v
C3The output signal of representing first delay cell in the first order delay phase-locked loop 500, second delay cell and the 3rd delay cell respectively.
v
C1 '-v
C8 'Represent second level delay phase-locked loop 500 respectively " in the output signal of 8 delay cells.
As can be seen from Figure 10, second level delay phase-locked loop 500 " in the rising edge of output signal of 8 delay cells with v
C1, v
C2Time interval of rising edge divided 8 parts equally.
Need to prove that each delay time lag among Figure 10 is identical.Certainly, also can be different.
Referring to Figure 11, this figure is the not corresponding simultaneously oscillogram of delay time lag.
For the application scenario of some sample circuit, such as the DC-to-dc switching controller in the digital power controller, its sample circuit only need be at some voltage V
xAs reaching higher sample conversion precision in the reference data voltage environs, in whole input range, do not need all have identical high precision, even do not need them that identical step-length is arranged.
Therefore can save delay unit amount like this through constituting the time-delay sampling heterogeneous shown in Figure 11 the time of delay between each delay cell in the adjustment delay phase-locked loop.Such sample mode can be applied in the digital power controller, cooperates rational digital processing, can improve system response time.
In Figure 11, at V
xNear sampling 16 times, v
C1-v
C16, be the output signal of 16 delay cells, by finding out among the figure, time interval of rising edge of these 16 output signals is inhomogeneous, from V
xNearer local time is less at interval, from V
xLocal time far away is bigger at interval.
Based on the above-mentioned a kind of analog to digital converter that provides, the present invention also provides a kind of D conversion method, specifies its workflow below in conjunction with specific embodiment.
Referring to Figure 12, this figure is D conversion method embodiment one flow chart provided by the invention.
S1201: receive the external clock input signal, produce first clock signal, second clock signal and the 3rd clock signal; The difference of said second clock signal and the 3rd clock signal is clock cycle T;
S1202: receive aanalogvoltage and reference voltage; Under the control of first clock signal; Convert said aanalogvoltage into square-wave signal in the previous clock cycle T; Convert said reference voltage into square-wave signal in the clock cycle T in back, said square-wave signal and said aanalogvoltage are linear;
S1203: said clock cycle T is divided into M delay time lag, corresponding M the clock signal of the first order that produce; M >=2;
S1204 samples to said square-wave signal under the control of a said first order M clock signal;
S1205: the conversion of signals after will sampling is the corresponding digital signal of said aanalogvoltage.
D conversion method provided by the invention is under the control of first clock signal; In previous clock cycle T, aanalogvoltage is sampled; In next clock cycle T, reference voltage is sampled; Concrete sampling is accomplished by trigger, and the sampling time of trigger is to be controlled by the clock signal that first order delay phase-locked loop produces.In two clock cycle T, just can accomplish analog-to-digital conversion like this, because clock cycle and internal clocking frequency are reciprocal relations, therefore, the relation of the sample frequency of this method and internal clocking frequency is two times a relation.Under identical sample frequency, this method reduces with respect to the internal clocking frequency of traditional ADC greatly, can reduce power consumption so like this, and also realizes easily on the circuit.
Need to prove that said M is as long as be the integer more than or equal to 2, but for ease, M can preferably be taken as 2
NWherein N is the conversion accuracy of analog to digital converter ADC.Following examples are 2 with M
NFor example is introduced.Need to prove that a said first order M delay time lag can be identical, also can be different.
The embodiment that Figure 12 is corresponding comprises the one-level delay time lag, it is understandable that, also comprises the first order 2
NThe difference of any two clock signals of individual clock signal is divided into n
1Individual delay time lag, the corresponding second level n that produces
1Individual clock signal is at said second level n
1Under the control of individual clock signal said square-wave signal is sampled; N wherein
1>=2;
With second level n
1The difference of any two clock signals of individual clock signal is divided into n
2Individual delay time lag, the corresponding third level n that produces
2Individual clock signal is at said third level n
2Under the control of individual clock signal said square-wave signal is sampled; Wherein, n
2>=2;
Up to n level n
(n-1)The difference of any two clock signals of individual clock signal is divided into n
nIndividual delay time lag, corresponding (n+1) level n that produces
nIndividual clock signal is at said (n+1) level n
nUnder the control of individual clock signal said square-wave signal is sampled; Wherein, n
n>=2;
With the conversion of signals after all samplings is the corresponding digital signal of said aanalogvoltage.
With the conversion of signals after all samplings is the corresponding digital signal of said aanalogvoltage.
During the time interval,, the signal after all samplings is all carried out analog-to-digital conversion as multilevel delay at the corresponding clock signal down-sampling of all delay time lags.
Based on the above-mentioned a kind of analog to digital converter that provides, the present invention also provides a kind of digital power controller of using said analog to digital converter, specifies its part below in conjunction with specific embodiment.
Referring to Figure 13, this figure is the structure chart of digital power controller provided by the invention.
The digital power controller that the embodiment of the invention provides; Comprise the described analog to digital converter 1405 of above embodiment, also comprise: power stage circuit 1401, feedback circuit 1404, error amplifier 1406, digital pulse width adjuster 1403 and drive circuit 1402;
Said feedback circuit 1404 is used to gather the output signal of said power stage circuit 1401, and with the analog signal V that gathers
SampleFeed back to said analog to digital converter 1405;
Said analog to digital converter 1405 is used for said analog signal V
SampleConvert digital signal D into
Sample, be sent to an input of said error amplifier 1406;
Said error amplifier 1406 is used for said digital signal D
SampleWith numerical reference signal D
RefCompare, comparative result is sent to said digital pulse width adjuster 1403;
Said digital pulse width adjuster 1403 is used for sending a control signal to said drive circuit 1402 according to said comparative result;
Said drive circuit 1402 is used for driving according to said control signal the switch motion of the switching device of said power stage circuit 1401, to regulate the output signal of said power stage circuit 1401.
Need to prove that the internal structure of the analog to digital converter 1405 in the present embodiment can be used realizing among the above embodiment, repeats no more at this.
Said feedback circuit 1404 can be realized by resistor voltage divider network.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention, or are revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (14)
1. an analog to digital converter is characterized in that, comprising: voltage time change-over circuit, the first trigger group, change-over circuit, clock generating circuit and first order delay phase-locked loop;
Clock generating circuit is used to receive the external clock input signal, produces first clock signal, second clock signal and the 3rd clock signal; Said second clock signal is as the input clock of first order delay phase-locked loop, and said the 3rd clock signal is as the reference clock of first order delay phase-locked loop, and the difference of said input clock and reference clock is clock cycle T;
The voltage time change-over circuit; Be used to receive aanalogvoltage and reference voltage; Under the control of first clock signal; Convert said aanalogvoltage into square-wave signal in the previous clock cycle T, convert said reference voltage into square-wave signal in the back clock cycle T, said square-wave signal and said aanalogvoltage are linear;
Said first order delay phase-locked loop is used for the difference of said input clock and reference clock is divided into M delay time lag, M clock signal of corresponding generation; M >=2;
The said first trigger group; Comprise M trigger; A said M clock signal connects the input end of clock of M trigger respectively, and the input of each trigger connects said square-wave signal, and each trigger is at the said square-wave signal of control down-sampling of separately clock signal; The output of each trigger connects the different inputs of said change-over circuit respectively;
Said change-over circuit, the output conversion of signals that is used for said trigger is the corresponding digital signal of said aanalogvoltage.
2. analog to digital converter according to claim 1 is characterized in that, said first order delay phase-locked loop comprises phase discriminator, a charge pump and M delay cell;
The first input end of said phase discriminator connects said reference clock;
The output of said phase discriminator connects the input of said charge pump, and said electric charge delivery side of pump connects the first input end of each delay cell;
The output of previous delay cell connects second input of a back delay cell; Second input of first delay cell connects said input clock, and the output of last delay cell connects second input of said phase discriminator;
Said phase discriminator is used for the output signal and the reference clock of last delay cell of comparison, and comparative result is exported to said charge pump;
Said charge pump is used for regulating output voltage according to said comparative result, to regulate each delay cell, the output signal of last delay cell and reference clock is realized synchronously.
3. analog to digital converter according to claim 2 is characterized in that, a said M trigger is d type flip flop;
The input end of clock of each d type flip flop connects the output of corresponding delay cell;
Each d type flip flop said square-wave signal that is used to sample;
The output of each d type flip flop connects the different inputs of said change-over circuit respectively.
4. according to each described analog to digital converter of claim 1-3, it is characterized in that said M is 2
NWherein N is the conversion accuracy of analog to digital converter ADC.
5. analog to digital converter according to claim 1 is characterized in that a said M delay time lag is identical.
6. analog to digital converter according to claim 1 is characterized in that, said M delay time lag is different.
7. analog to digital converter according to claim 3; It is characterized in that; Also comprise n the delay phase-locked loop identical, be respectively second level delay phase-locked loop, third level delay phase-locked loop, up to (n+1) level delay phase-locked loop with said first order delay phase-locked loop structure; Also comprising n delay phase-locked loop corresponding n the trigger group identical with the said first trigger group structure, is respectively the second trigger group, and the 3rd trigger group is up to (n+1) trigger group; N >=1;
The output of any two delay cells of said first order delay phase-locked loop connects the reference clock and the input clock of second level delay phase-locked loop respectively; The output of any two delay cells of second level delay phase-locked loop connects the reference clock and the input clock of third level delay phase-locked loop respectively; The reference clock and the input clock that connect (n+1) level delay phase-locked loop up to the output of any two delay cells of n level delay phase-locked loop respectively;
The output of each delay cell of every grade of delay phase-locked loop connects the input end of clock of the trigger in the corresponding trigger group; The input of each trigger in every group of trigger all connects said square-wave signal, and the output of each trigger in every group of trigger connects the different inputs of said change-over circuit respectively.
8. analog to digital converter according to claim 1 is characterized in that, said voltage time change-over circuit comprises: selector switch, integrator and comparator;
The input of said selector switch connects aanalogvoltage, reference voltage and voltage source, is used under the control of said first clock signal, selects the voltage of input to export at output;
The input of said integrator connects the output of said selector switch, is used for the first input end that signal with input carries out exporting to behind the integration comparator;
Said comparator is used for the output signal of integrator and the lower limit of sampled voltage are compared, and the output comparative result is given said each trigger.
9. a D conversion method is characterized in that, may further comprise the steps:
Receive the external clock input signal, produce first clock signal, second clock signal and the 3rd clock signal; The difference of said second clock signal and the 3rd clock signal is clock cycle T;
Receive aanalogvoltage and reference voltage; Under the control of first clock signal, convert said aanalogvoltage into square-wave signal in the previous clock cycle T; Convert said reference voltage into square-wave signal in the clock cycle T in back, said square-wave signal and said aanalogvoltage are linear;
The difference T of second clock signal and the 3rd clock signal is divided into M delay time lag, corresponding M the clock signal of the first order that produce; M >=2;
Under the control of a said first order M clock signal, said square-wave signal is sampled;
With the conversion of signals after the sampling is the corresponding digital signal of said aanalogvoltage.
10. D conversion method according to claim 9 is characterized in that, comprises that also the difference with any two clock signals of a first order M clock signal is divided into n
1Individual delay time lag, the corresponding second level n that produces
1Individual clock signal is at said second level n
1Under the control of individual clock signal said square-wave signal is sampled; N wherein
1>=2;
With second level n
1The difference of any two clock signals of individual clock signal is divided into n
2Individual delay time lag, the corresponding third level n that produces
2Individual clock signal is at said third level n
2Under the control of individual clock signal said square-wave signal is sampled; Wherein, n
2>=2;
Up to n level n
(n-1)The difference of any two clock signals of individual clock signal is divided into n
nIndividual delay time lag, corresponding (n+1) level n that produces
nIndividual clock signal is at said (n+1) level n
nUnder the control of individual clock signal said square-wave signal is sampled; Wherein, n
n>=2;
With the conversion of signals after all samplings is the corresponding digital signal of said aanalogvoltage.
11., it is characterized in that said M is 2 according to claim 9 or 10 D conversion methods
NWherein N is the conversion accuracy of analog to digital converter ADC.
12., it is characterized in that a said first order M delay time lag is identical according to claim 9 or 10 described D conversion methods.
13., it is characterized in that said first order M delay time lag is different according to claim 9 or 10 described D conversion methods.
14. a digital power controller is characterized in that, comprises each described analog to digital converter of claim 1-8, also comprises: power stage circuit, feedback circuit, error amplifier, digital pulse width adjuster and drive circuit;
Said feedback circuit is used to gather the output signal of said power stage circuit, and the analog signal of gathering is fed back to said analog to digital converter;
Said analog to digital converter, being used for said analog signal conversion is digital signal, is sent to an input of said error amplifier;
Said error amplifier is used for said digital signal and numerical reference signal are compared, and comparative result is sent to said digital pulse width adjuster;
Said digital pulse width adjuster is used for sending a control signal to said drive circuit according to said comparative result;
Said drive circuit is used for driving according to said control signal the switch motion of the switching device of said power stage circuit, to regulate the output signal of said power stage circuit.
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