CN103166644A - A low-power successive approximation analog-to-digital converter and its conversion method - Google Patents

Abstract

The invention discloses a low power consumption successive approximation type analog-digital converter and a converting method of the low power consumption successive approximation type analog-digital converter. A switched capacitor network comprises a capacitor pair which is one less in number when compared with output binary coding, timing sequence of switches is arranged anew, common mode electrical level Vcm is introduced during the comparison process, compensation capacitor in traditional successive approximation type analog-digital converter switched capacitor networks, and the effect of achieving N bit resolution ratio of N-1 capacitor is achieved. Compared with traditional successive approximation type analog-digital converters, two capacitor pairs of a highest order and a second highest order are cut down, and accordingly the whole total capacitance is reduced by 75%. Along with reduction of capacitance, charging and discharging target is correspondingly reduced, accordingly overall power consumption is lowered, chip area is reduced, and economic benefit is improved. During conversion process, compared with traditional structures, common mode voltage change quantity of an input end of a comparator is little in common mode shaking only.

Description

A kind of low-power consumption gradual approaching A/D converter and conversion method thereof

Technical field

The invention belongs to technical field of integrated circuits, particularly a kind of gradual approaching A/D converter and conversion method thereof.

Background technology

Gradual approaching A/D converter is the analog-digital converter structure of a kind of middle high accuracy, moderate rate, super low-power consumption.Use for wireless sense network, portable set etc., analog to digital converter is required and can be operated under low supply voltage.Yet along with the reduction of supply voltage, the gain of circuit is restricted, and the structure of gradual approaching A/D converter includes only comparator, digital to analog converter and successive approximation register, does not need to provide the circuit of gain.The power consumption of digital circuit can constantly reduce along with the process reduction ratio, and the power consumption of analog circuit is difficult to synchronously reduce along with the progress of technique.The capacitor type gradual approaching A/D converter needs to use large electric capacity under high definition case, not only discharges and recharges power consumption large, and makes large electric capacity waste chip area, and economic benefit is not high.

Summary of the invention

Goal of the invention: propose a kind of low-power consumption gradual approaching A/D converter and conversion method thereof, in the situation that equal accuracy, capacitance reduces 75% than traditional scheme, reduces power consumption.

Technical scheme: a kind of low-power consumption gradual approaching A/D converter comprises comparator and switched capacitor network; Described switched capacitor network comprises the positive capacitance network that connects described comparator normal phase input end and the inverted capacitance network that is connected described comparator inverting input; Described positive capacitance network and inverted capacitance network comprise that respectively the binary coding figure place N than analog to digital converter output lacks N-1 the electric capacity of one.

Wherein, the electric capacity top crown of described positive capacitance network selects to connect positive input voltage vin, common mode electrical level Vcm, low level VL, high level VH by switch respectively; The be coupled normal phase input end that is connected to described comparator and connect common mode electrical level Vcm by the positive switch of the electric capacity bottom crown of described positive capacitance network; The electric capacity top crown of described inverted capacitance network selects to connect reverse inter-input-ing voltage Vip, common mode electrical level Vcm, low level VL, high level VH by switch respectively; The be coupled inverting input that is connected to described comparator and connect common mode electrical level Vcm by anti-phase opening of the electric capacity bottom crown of described inverted capacitance network.

Wherein, the first capacitor C of described positive capacitance network ₁Capacitance is C, and the second capacitance to N-1 electric capacity is C _i=2 ^i-2C, wherein, i is the natural number of 2≤i≤N-1; The first capacitor C of described inverted capacitance network ₁Capacitance is C, and the second capacitance to N-1 electric capacity is C _i=2 ^i-2C, wherein, i is the natural number of 2≤i≤N-1.

A kind of D conversion method based on above-mentioned low-power consumption gradual approaching A/D converter is characterized in that: its transfer process comprises the steps:

Sample phase:

In switched capacitor network, the bottom crown of all electric capacity connects common mode electrical level Vcm, and the top crown of all electric capacity of positive capacitance network that are connected with the comparator normal phase input end connects the positive input voltage vin; The top crown of all electric capacity of inverted capacitance network that are connected with the comparator inverting input connects reverse inter-input-ing voltage Vip;

The AD change-over period:

At first, the bottom crown of all electric capacity of switched capacitor network disconnects and being connected of common mode electrical level Vcm; The top crown of all electric capacity of positive capacitance network that are connected with the comparator normal phase input end connects common mode electrical level Vcm; The top crown of all electric capacity of inverted capacitance network that are connected with the comparator inverting input connects common mode electrical level Vcm; Switched capacitor network carries out after electric charge heavily distributes; Comparator comparison normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn size also output results to control circuit; If Vxp＞Vxn, i.e. V _ip-V _in＞0, control circuit is binary coding extreme higher position 1, if Vxp less than Vxn, i.e. V _ip-V _in＜0, control circuit is with binary coding extreme higher position 0;

According to the signal value of comparator output, the highest order capacitance switch of controlling respectively positive capacitance network and inverted capacitance network by control circuit meets low level VL or high level VH or maintained switch and is failure to actuate, and switched capacitor network begins electric charge and heavily distributes;

When the switched capacitor network electric charge heavily distribute complete after, output signal to control circuit after comparator comparison normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn size, control circuit is with binary coding time high position 1 or set to 0;

Successively relatively go down successively, until binary code extreme lower position 1 or set to 0 after, in this binary code write control circuit register, complete analog-to-digital conversion.

Beneficial effect: the switched capacitor network in the present invention comprises the electric capacity pair of few one of specific output binary coding quantity, by arranging and introducing common mode electrical level Vcm in comparison procedure the sequential of switch is brand-new, saved the building-out capacitor in conventional successive approach type analog to digital converter switched capacitor network, reached N-1 electric capacity to realizing that resolution is the effect of N position, by lacked highest order and time high-order two electric capacity pair than conventional successive approach type analog to digital converter, whole total capacitance also reduces by 75%.Along with reducing of electric capacity, charging and discharging currents is corresponding reducing also, thereby reduced overall power, and also reduced chip area, improved economic benefit.In transfer process, the common-mode voltage variation amount of comparator input terminal is compared with traditional structure, is only

Wherein N is analog-digital bit, V _ref=VH-VL, the common mode shake is very little.

Description of drawings

Fig. 1 is the circuit structure diagram of low-power consumption gradual approaching A/D converter of the present invention;

Fig. 2 is first three time of low-power consumption gradual approaching A/D converter of the present invention switch transition fundamental diagram;

Fig. 3 is that low-power consumption gradual approaching A/D converter of the present invention is at input reference signal [V _ref, V _ref/ 2] the 4th switch transition fundamental diagram;

Fig. 4 is that low-power consumption gradual approaching A/D converter of the present invention is at input reference signal [V _ref/ 2,0] the 4th switch transition fundamental diagram;

Fig. 5 be low-power consumption gradual approaching A/D converter of the present invention input reference signal [0 ,-V _ref/ 2] the 4th switch transition fundamental diagram;

Fig. 6 is that low-power consumption gradual approaching A/D converter of the present invention is at input reference signal [V _ref/ 2 ,-V _ref] the 4th switch transition fundamental diagram;

Fig. 7 is the working timing figure of low-power consumption gradual approaching A/D converter of the present invention.

Embodiment

Below in conjunction with accompanying drawing, the present invention is done further and explain.

As shown in Figure 1, the present embodiment is that the low-power consumption gradual approaching A/D converter of 4 outputs comprises control circuit, comparator and switched capacitor network.Wherein switched capacitor network comprises the positive capacitance network that is connected to the comparator normal phase input end, and the inverted capacitance network that is connected to the comparator inverting input.In the positive capacitance network, the electric capacity of the few number of specific output binary coding figure place is arranged, this example is 4 output B4B3B2B1, and 3 electric capacity are namely arranged, and is followed successively by the first capacitor C 1 to the 3rd capacitor C 3 from lowest order to highest order.The common port of the first capacitor C 1 to the 3rd capacitor C 3 is connected to the normal phase input end of comparator jointly, and can be connected to common mode electrical level Vcm by K switch p, the other end is respectively by the first K switch 1 to the 3rd selectable connection input signal of K switch 3 Vin, low level VL, high level VH or common mode electrical level Vcm.The first capacitor C 1 capacitance is C, and the capacitance of other electric capacity is C _i=2 ^i-2C, (i=2,3).All switches are controlled by the pulse signal of control circuit output.In the inverted capacitance network, the electric capacity with positive network similar number is arranged, be followed successively by the 4th capacitor C 12, the 5th capacitor C 22, the 6th capacitor C 32 from lowest order to highest order.The common port of the 4th capacitor C 12, the 5th capacitor C 22, the 6th capacitor C 32 is connected to the inverting input of comparator jointly, and can be connected to common mode electrical level Vcm by K switch n, the other end is respectively by the 4th K switch 12, the 5th K switch 22, the 6th K switch 32, selectable connection input signal Vip, low level VL, high level VH or common mode electrical level Vcm.The 4th capacitor C 12 capacitances are C, and the capacitance of other electric capacity is C _i2=2 ^i-2C, (i=2,3).Anti-phase network configuration is identical with the positive network configuration.

As shown in Fig. 2 (A), sample phase, K switch p is closed under the driving of control circuit in the positive network, the public termination common mode electrical level Vcm of the first capacitor C 1 to the 3rd capacitor C 3, the first K switch 1 to the 3rd K switch 3 is closed under control circuit drives simultaneously, meet input signal Vin, give the capacitor charging of positive network; K switch n is closed under the driving of control circuit in anti-phase network, the public termination common mode electrical level Vcm of the 4th capacitor C 12, the 5th capacitor C 22, the 6th capacitor C 32, while the 4th K switch 12, the 5th K switch 22, the 6th K switch 32 closure under control circuit drives, meet input signal Vip, give the capacitor charging of anti-phase network.In at this moment stored quantity of electric charge positive network be: Q _p=(V _cm-V _in) * 4C; In anti-phase network be: Q _n=(V _cm-V _ip) * 4C.

As shown in Fig. 2 (B), in comparison phase, positive K switch p and phase-veversal switch Kn all disconnect, simultaneously in the positive network in the first K switch 1 to the 3rd K switch 3 and anti-phase network the 4th K switch 12, the 5th K switch 22, the 6th K switch 32 meet common mode electrical level Vcm under control circuit drives, in positive network and anti-phase network, the quantity of electric charge remains unchanged, electric charge heavily distributes, i.e. Q _xp=Q _p, Q _xn=Q _n, have:

Q _xp＝(V _xp-V _cm)×4C＝Q _p

Q _xn＝(V _xn-V _cm)×4C＝Q _n

Note $V_{\mathrm{ref}}=V_H-V_L,V_{\mathrm{cm}}=\frac{1}{2}(V_H+V_L),$ V _xp=2V _cm-V _in, V _xn=2V _cm-V _ip

This moment, comparator compared normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn, and result is outputed to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, i.e. V _ip-V _in＞0, binary coding highest order B4 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, i.e. V _ip-V _in＜0, binary coding highest order B4 is set to 0.

(1) for B4 be 1 situation:

When highest order B4 is set to 1, control circuit produces corresponding control signal according to the Output rusults of comparator, make an end of the 3rd capacitor C 3 in the positive network be connected to low level VL by the 3rd K switch 3, one end of the 6th capacitor C 32 in anti-phase network is connected to high level VH by the 6th K switch 32, as shown in Fig. 2 (C1).This moment, the electric charge in positive network and anti-phase network on electric capacity can occur heavily to distribute, thereby causes comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change due to the variation of voltage.According to principle of charge conservation, the stored quantity of electric charge of sample phase should remain unchanged, thereby obtains following equation:

Q _xp＝(V _xp-V _L)×2C+(V _xp-V _cm)×2C＝Q _p

Q _xn＝(V _xn-V _H)×2C+(V _xn-V _cm)×2C＝Q _n

Above-mentioned two formulas of abbreviation can get: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}-\frac{1}{4}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}-\frac{1}{4}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

This moment, comparator compared normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn, and result is outputed to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely

Binary coding time high-order B3 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely Binary coding time high-order B3 is set to 0.

Be 11 situation for B4B3:

When inferior high-order B3 is set to 1, control circuit produces corresponding control signal according to the Output rusults of comparator, make an end of the second capacitor C 2 in the positive network be connected to low level VL by second switch K2, one end of the 5th capacitor C 22 in anti-phase network is connected to high level VH by the 5th K switch 22, as shown in Fig. 2 (D1).This moment, the electric charge in positive network and anti-phase network on electric capacity can occur heavily to distribute, thereby causes comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change due to the variation of voltage.According to principle of charge conservation, the stored quantity of electric charge of sample phase should remain unchanged, thereby obtains following equation:

Q _xp＝(V _xp-V _L)×3C+(V _xp-V _cm)×C＝Q _p

Q _xn＝(V _xn-V _H)×3C+(V _xn-V _cm)×C＝Q _n

Above-mentioned two formulas of abbreviation can get: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}-\frac{3}{8}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}+\frac{3}{8}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

This moment, comparator compared normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn, and result is outputed to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely With binary coding again high-order B2 be set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely

With binary coding again high-order B2 be set to 0.

When B2 was set to 1, control circuit produced corresponding control signal according to the Output rusults of comparator, makes an end of the first capacitor C 1 in the positive network be connected to low level VL by the first K switch 1, and anti-phase network is constant, as shown in Fig. 3 (E1).This moment, the electric charge in positive network and anti-phase network on electric capacity can occur heavily to distribute, thereby causes comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change due to the variation of voltage.According to principle of charge conservation, the stored quantity of electric charge of sample phase should remain unchanged, thereby obtains following equation:

Q _xp＝(V _xp-V _L)×4C＝Q _p

Q _xn＝(V _xn-V _H)×3C+(V _xn-V _cm)×C＝Q _n

Above-mentioned two formulas of abbreviation can get: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}-\frac{1}{2}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}+\frac{3}{8}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

This moment, comparator compared normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn, and result is outputed to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely

Binary coding lowest order B1 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely

Binary coding lowest order B1 is set to 0.

When B2 was set to 0, control circuit produced corresponding control signal according to the Output rusults of comparator, makes an end of the 4th capacitor C 12 in anti-phase network be connected to low level VL by the 4th K switch 12, and the positive network is constant, as shown in Fig. 3 (E2).This moment, the electric charge in positive network and anti-phase network on electric capacity can occur heavily to distribute, thereby causes comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change due to the variation of voltage.According to principle of charge conservation, the stored quantity of electric charge of sample phase should remain unchanged, thereby obtains following equation:

Q _xp＝(V _xp-V _L)×3C+(V _xp-V _cm)×C＝Q _p

Q _xn＝(V _xn-V _H)×3C+(V _xn-V _L)×C＝Q _n

Above-mentioned two formulas of abbreviation can get: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}-\frac{3}{8}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}+\frac{1}{4}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

This moment, comparator compared normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn, and result is outputed to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely

Binary coding lowest order B1 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely

Binary coding lowest order B1 is set to 0.

Be 10 situation for B4B3:

When inferior high-order B3 is set to 0, control circuit produces corresponding control signal according to the Output rusults of comparator, make an end of the second capacitor C 2 in the positive network be connected to high level VH by second switch K2, one end of the 5th capacitor C 22 in anti-phase network is connected to low level VL by the 5th K switch 22, as shown in Fig. 2 (D2).This moment, the electric charge in positive network and anti-phase network on electric capacity can occur heavily to distribute, thereby causes comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change due to the variation of voltage.According to principle of charge conservation, the stored quantity of electric charge of sample phase should remain unchanged, thereby obtains following equation:

Q _xp＝(V _xp-V _L)×2C+(V _xp-V _H)×C+(V _xp-V _cm)×C＝Q _p

Q _xn＝(V _xn-V _H)×2C+(V _xn-V _L)×C+(V _xn-V _cm)×C＝Q _n

Above-mentioned two formulas of abbreviation can get: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}-\frac{1}{8}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}+\frac{1}{8}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

This moment, comparator compared normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn, and result is outputed to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely

With binary coding again high-order B2 be set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely

With binary coding again high-order B2 be set to 0.

When B2 was set to 1, control circuit produced corresponding control signal according to the Output rusults of comparator, makes an end of the first capacitor C 1 in the positive network be connected to low level VL by the first K switch 1, and anti-phase network is constant, as shown in Fig. 4 (E3).This moment, the electric charge in positive network and anti-phase network on electric capacity can occur heavily to distribute, thereby causes comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change due to the variation of voltage.According to principle of charge conservation, the stored quantity of electric charge of sample phase should remain unchanged, thereby obtains following equation:

Q _xp＝(V _xp-V _L)×3C+(V _xp-V _H)×C＝Q _p

Q _xn＝(V _xn-V _H)×2C+(V _xn-V _L)×C+(V _xn-V _cm)×C＝Q _n

Above-mentioned two formulas of abbreviation can get: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}-\frac{1}{4}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}+\frac{1}{8}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

This moment, comparator compared normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn, and result is outputed to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely

Binary coding lowest order B1 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely

Binary coding lowest order B1 is set to 0.

When B2 was set to 0, control circuit produced corresponding control signal according to the Output rusults of comparator, makes an end of the 4th capacitor C 12 in anti-phase network be connected to low level VL by the 4th K switch 12, and the positive network is constant, as shown in Fig. 4 (E4).This moment, the electric charge in positive network and anti-phase network on electric capacity can occur heavily to distribute, thereby causes comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change due to the variation of voltage.According to principle of charge conservation, the stored quantity of electric charge of sample phase should remain unchanged, thereby obtains following equation:

Q _xp＝(V _xp-V _L)×2C+(V _xp-V _H)×C+(V _xp-V _cm)×C＝Q _p

Q _xn＝(V _xn-V _H)×2C+(V _xn-V _L)×2C＝Q _n

Above-mentioned two formulas of abbreviation can get: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}-\frac{1}{8}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ V _xn＝2V _cm-V _ip。

This moment, comparator compared normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn, and result is outputed to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely

Binary coding lowest order B1 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely

Binary coding lowest order B1 is set to 0.

(2) for B4 be 0 situation:

When highest order B4 is set to 0, control circuit produces corresponding control signal according to the Output rusults of comparator, make an end of the 3rd capacitor C 3 in the positive network be connected to high level VH by the 3rd K switch 3, one end of the 6th capacitor C 32 in anti-phase network is connected to low level VL by the 6th K switch 32, as shown in Fig. 2 (C2).This moment, the electric charge in positive network and anti-phase network on electric capacity can occur heavily to distribute, thereby causes comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change due to the variation of voltage.According to principle of charge conservation, the stored quantity of electric charge of sample phase should remain unchanged, thereby obtains following equation:

Q _xp＝(V _xp-V _H)×2C+(V _xp-V _cm)×2C＝Q _p

Q _xn＝(V _xn-V _L)×2C+(V _xn-V _cm)×2C＝Q _n

Above-mentioned two formulas of abbreviation can get: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}+\frac{1}{4}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}-\frac{1}{4}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

This moment, comparator compared normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn, and result is outputed to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely

Binary coding time high-order B3 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely Binary coding time high-order B3 is set to 0.

Be 01 situation for B4B3:

When inferior high-order B3 is set to 1, control circuit produces corresponding control signal according to the Output rusults of comparator, make an end of the second capacitor C 2 in the positive network be connected to low level VL by second switch K2, one end of the 5th capacitor C 22 in anti-phase network is connected to high level VH by the 5th K switch 22, as shown in Fig. 2 (D3).This moment, the electric charge in positive network and anti-phase network on electric capacity can occur heavily to distribute, thereby causes comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change due to the variation of voltage.According to principle of charge conservation, the stored quantity of electric charge of sample phase should remain unchanged, thereby obtains following equation:

Q _xp＝(V _xp-V _L)×C+(V _xp-V _H)×2C+(V _xp-V _cm)×C＝Q _p

Q _xn＝(V _xn-V _H)×C+(V _xn-V _L)×2C+(V _xn-V _cm)×2C＝Q _n

Above-mentioned two formulas of abbreviation can get: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}+\frac{1}{8}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}-\frac{1}{8}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

This moment, comparator compared normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn, and result is outputed to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely

With binary coding again high-order B2 be set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely

With binary coding again high-order B2 be set to 0.

When B2 was set to 1, control circuit produced corresponding control signal according to the Output rusults of comparator, makes an end of the first capacitor C 1 in the positive network be connected to low level VL by the first K switch 1, and anti-phase network is constant, as shown in Fig. 5 (E5).This moment, the electric charge in positive network and anti-phase network on electric capacity can occur heavily to distribute, thereby causes comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change due to the variation of voltage.According to principle of charge conservation, the stored quantity of electric charge of sample phase should remain unchanged, thereby obtains following equation:

Q _xp＝(V _xp-V _L)×2C+(V _xp-V _H)×2C＝Q _p

Q _xn＝(V _xn-V _H)×C+(V _xn-V _L)×2C+(V _xn-V _cm)×2C＝Q _n

Above-mentioned two formulas of abbreviation can get: V _xp=2V _cm-V _in, $V_{\mathrm{xn}}=2V_{\mathrm{cm}}-\frac{1}{8}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

This moment, comparator compared normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn, and result is outputed to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely

Binary coding lowest order B1 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely

Binary coding lowest order B1 is set to 0.

When B2 was set to 0, control circuit produced corresponding control signal according to the Output rusults of comparator, makes an end of the 4th capacitor C 12 in anti-phase network be connected to low level VL by the 4th K switch 12, and the positive network is constant, as shown in Fig. 5 (E6).This moment, the electric charge in positive network and anti-phase network on electric capacity can occur heavily to distribute, thereby causes comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change due to the variation of voltage.According to principle of charge conservation, the stored quantity of electric charge of sample phase should remain unchanged, thereby obtains following equation:

Q _xp＝(V _xp-V _L)×C+(V _xp-V _H)×2C+(V _xp-V _cm)×C＝Q _p

Q _xn＝(V _xn-V _H)×C+(V _xn-V _L)×3C＝Q _n

Above-mentioned two formulas of abbreviation can get: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}+\frac{1}{8}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}-\frac{1}{4}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

This moment, comparator compared normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn, and result is outputed to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely

Binary coding lowest order B1 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely

Binary coding lowest order B1 is set to 0.

Be 00 situation for B4B3:

When inferior high-order B3 is set to 0, control circuit produces corresponding control signal according to the Output rusults of comparator, make an end of the second capacitor C 2 in the positive network be connected to high level VH by second switch K2, one end of the 5th capacitor C 22 in anti-phase network is connected to low level VL by the 5th K switch 22, as shown in Fig. 2 (D4).This moment, the electric charge in positive network and anti-phase network on electric capacity can occur heavily to distribute, thereby causes comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change due to the variation of voltage.According to principle of charge conservation, the stored quantity of electric charge of sample phase should remain unchanged, thereby obtains following equation:

Q _xp＝(V _xp-V _H)×3C+(V _xp-V _cm)×C＝Q _p

Q _xn＝(V _xn-V _L)×3C+(V _xp-V _cm)×C＝Q _n

Above-mentioned two formulas of abbreviation can get: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}+\frac{3}{8}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}-\frac{3}{8}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

This moment, comparator compared normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn, and result is outputed to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely

With binary coding again high-order B2 be set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely

With binary coding again high-order B2 be set to 0.

When B2 was set to 1, control circuit produced corresponding control signal according to the Output rusults of comparator, makes an end of the first capacitor C 1 in the positive network be connected to low level VL by the first K switch 1, and anti-phase network is constant, as shown in Fig. 6 (E7).This moment, the electric charge in positive network and anti-phase network on electric capacity can occur heavily to distribute, thereby causes comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change due to the variation of voltage.According to principle of charge conservation, the stored quantity of electric charge of sample phase should remain unchanged, thereby obtains following equation:

Q _xp＝(V _xp-V _H)×3C+(V _xp-V _L)×C＝Q _p

Q _xn＝(V _xn-V _L)×3C+(V _xp-V _cm)×C＝Q _n

Above-mentioned two formulas of abbreviation can get: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}+\frac{1}{4}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}-\frac{3}{8}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

This moment, comparator compared normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn, and result is outputed to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely

Binary coding lowest order B1 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely Binary coding lowest order B1 is set to 0.

When B2 was set to 0, control circuit produced corresponding control signal according to the Output rusults of comparator, makes an end of the 4th capacitor C 12 in anti-phase network be connected to low level VL by the 4th K switch 12, and the positive network is constant, as shown in Fig. 6 (E8).This moment, the electric charge in positive network and anti-phase network on electric capacity can occur heavily to distribute, thereby causes comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change due to the variation of voltage.According to principle of charge conservation, the stored quantity of electric charge of sample phase should remain unchanged, thereby obtains following equation:

Q _xp＝(V _xp-V _H)×3C+(V _xp-V _cm)×C＝Q _p

Q _xn＝(V _xn-V _L)×4C＝Q _n

Above-mentioned two formulas of abbreviation can get: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}+\frac{3}{8}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}-\frac{1}{2}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

This moment, comparator compared normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn, and result is outputed to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely

Binary coding lowest order B1 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely

Binary coding lowest order B1 is set to 0.At last, in this tetrad code write control circuit register, complete analog-to-digital conversion.

The above is only the preferred embodiment of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (4)

1. a low-power consumption gradual approaching A/D converter, comprise comparator and switched capacitor network; Described switched capacitor network comprises the positive capacitance network that connects described comparator normal phase input end and the inverted capacitance network that is connected described comparator inverting input; It is characterized in that: described positive capacitance network and inverted capacitance network comprise that respectively the binary coding figure place N than analog to digital converter output lacks N-1 the electric capacity of one.

2. a kind of low-power consumption gradual approaching A/D converter according to claim 1 is characterized in that: the electric capacity top crown of described positive capacitance network selects to connect positive input voltage vin, common mode electrical level Vcm, low level VL, high level VH by switch respectively; The be coupled normal phase input end that is connected to described comparator and connect common mode electrical level Vcm by the positive switch of the electric capacity bottom crown of described positive capacitance network; The electric capacity top crown of described inverted capacitance network selects to connect reverse inter-input-ing voltage Vip, common mode electrical level Vcm, low level VL, high level VH by switch respectively; The be coupled inverting input that is connected to described comparator and connect common mode electrical level Vcm by anti-phase opening of the electric capacity bottom crown of described inverted capacitance network.

3. a kind of low-power consumption gradual approaching A/D converter according to claim 2, is characterized in that: the first capacitor C of described positive capacitance network ₁Capacitance is C, and the second capacitance to N-1 electric capacity is C _i=2 ^i-2C, wherein, i is the natural number of 2≤i≤N-1; The first capacitor C of described inverted capacitance network ₁Capacitance is C, and the second capacitance to N-1 electric capacity is C _i=2 ^i-2C, wherein, i is the natural number of 2≤i≤N-1.

4. D conversion method based on above-mentioned low-power consumption gradual approaching A/D converter, it is characterized in that: its transfer process comprises the steps:

Sample phase:

In switched capacitor network, the bottom crown of all electric capacity connects common mode electrical level Vcm, and the top crown of all electric capacity of positive capacitance network that are connected with the comparator normal phase input end connects the positive input voltage vin; The top crown of all electric capacity of inverted capacitance network that are connected with the comparator inverting input connects end of oppisite phase input voltage Vip;

The AD change-over period:

At first, the bottom crown of all electric capacity of switched capacitor network disconnects and being connected of common mode electrical level Vcm; The top crown of all electric capacity of positive capacitance network that are connected with the comparator normal phase input end connects common mode electrical level Vcm; The top crown of all electric capacity of inverted capacitance network that are connected with the comparator inverting input connects common mode electrical level Vcm; Switched capacitor network carries out after electric charge heavily distributes; Comparator comparison normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn size also output results to control circuit; If Vxp＞Vxn, i.e. V _ip-V _in＞0, control circuit is binary coding extreme higher position 1, if Vxp less than Vxn, i.e. V _ip-V _in＜0, control circuit is with binary coding extreme higher position 0;

According to the signal value of comparator output, the highest order capacitance switch of controlling respectively positive capacitance network and inverted capacitance network by control circuit meets low level VL or high level VH or maintained switch and is failure to actuate, and switched capacitor network begins electric charge and heavily distributes;

When the switched capacitor network electric charge heavily distribute complete after, output signal to control circuit after comparator comparison normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn size, control circuit is with binary coding time high position 1 or set to 0;

Successively relatively go down successively, until binary code extreme lower position 1 or set to 0 after, in this binary code write control circuit register, complete analog-to-digital conversion.

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