CN102034858A

CN102034858A - Bidirectional triode thyristor for electrostatic discharge protection of radio frequency integrated circuit

Info

Publication number: CN102034858A
Application number: CN201010522613.3A
Authority: CN
Inventors: 马飞; 韩雁; 董树荣; 宋波; 苗萌; 李明亮; 吴健; 郑剑锋
Original assignee: Zhejiang University ZJU
Current assignee: Zhejiang University ZJU
Priority date: 2010-10-28
Filing date: 2010-10-28
Publication date: 2011-04-27

Abstract

The invention discloses a bidirectional thyristor for protection against electrostatic discharge of radio frequency integrated circuits, which comprises a P-type substrate, on which a P-well and a first N-well and a first N-well located on both sides of the P-well are arranged on the P-type substrate. The second N well; above the first N well, the first N+ implantation region, the first P+ implantation region and the third N+ implantation region separated by shallow moats are sequentially provided from the outside to the inside, and the third N+ implantation region spans the first N The junction of the well and the P well; the second N+ implantation region, the second P+ implantation region and the fourth N+ implantation region separated by shallow moats are arranged in sequence from outside to inside on the second N well, and the fourth N+ implantation region is horizontal Across the junction of the second N well and the P well; between the third N+ implantation region and the fourth N+ implantation region, the surface of the P well is covered with gate oxide and polysilicon gate stacked sequentially from bottom to top. The bidirectional thyristor of the invention utilizes NMOS source-drain punch-through auxiliary triggering, has small turn-on voltage and parasitic capacitance, strong robust performance, and can provide bidirectional ESD protection.

Description

A kind of bidirectional triode thyristor that is used for the radio frequency integrated circuit electrostatic discharge protective

Technical field

The present invention relates to technical field of integrated circuits, relate in particular to a kind of bidirectional triode thyristor that is used for the radio frequency integrated circuit electrostatic discharge protective.

Background technology

Natural Electrostatic Discharge phenomenon constitutes serious threat to the reliability of integrated circuit.In industrial quarters, the inefficacy 30% of integrated circuit (IC) products all is owing to suffer the static discharge phenomenon caused, enters the integrated circuit after the nanometer era, and thinner gate oxide thickness all makes integrated circuit be subjected to the probability that static discharge destroys to be increased greatly.Therefore, the reliability of improving integrated circuit electrostatic discharge protection has very important effect to the rate of finished products that improves product.

The pattern of static discharge phenomenon is divided into four kinds usually: HBM (human body discharge mode), MM (machine discharge mode), CDM (assembly charging and discharging pattern) and FIM (electric field induction pattern).And the most common two kinds of static discharge patterns that also are the industrial quarters product must pass through are HBM and MM.When static discharge took place, electric charge flowed into and flows out from the another pin from a pin of chip usually, and the electric current that this moment, electrostatic charge produced is usually up to several amperes, and the voltage that produces at the electric charge input pin is up to several volts even tens volts.Can cause the damage of inside chip if bigger ESD electric current flows into inside chip, simultaneously, the high pressure that produces at input pin also can cause internal components generation grid oxygen punch-through, thereby causes circuit malfunction.Therefore, damaged by ESD, all will carry out effective ESD protection, the ESD electric current is released each pin of chip in order to prevent inside chip.

In the evolution of ESD protection, diode, GGNMOS (NMOS of grid ground connection), SCR devices such as (controllable silicons) are used as the ESD protective unit usually.SCR robustness in all devices is best, but trigger voltage is too high, is not suitable for the ESD protection of low-voltage circuit.Input and output pin for high speed circuit, or the input and output pin of radio frequency integrated circuit, because the parasitic capacitance that diode is introduced is less relatively, can add simulator emulation, and it is simple in structure, design easily, therefore often use diode pair to realize the ESD protection of radio frequency high-speed chip pin, but the anti-ESD energy of the diode of unit are force rate SCR is low.

Controllable silicon commonly used is the two traps of P, N on the P type substrate as shown in Figure 1, and two injection regions are all arranged on P trap and the N trap, is respectively N+ injection region and P+ injection region.Wherein the N+ injection region of N trap is arranged on the end away from the P trap, and the P+ injection region of N trap is arranged on the end near the P trap; The P+ injection region of P trap is arranged on the end away from the N trap, and the N+ injection region of P trap is arranged on the end near the N trap.A N+ injection region is arranged on N trap and top, P trap junction and is connected across the cut-in voltage that is used for reducing SCR between N trap and the P trap, uses shallow trench to isolate (STI) between all injection regions.The N+ injection region of N trap and P+ injection region connect electrical anode (Anode), and the N+ injection region of P trap and P+ injection region connect electrical cathode (Cathode).Fig. 2 is and the corresponding electrical schematic diagram of this SCR structure.

Under the normal operating conditions of integrated circuit, electrostatic discharge protector is to be in closing state, can not influence the current potential on the input and output pin.And externally static pours into integrated circuit and when producing moment high-tension, this device can be opened conducting, emits electrostatic induced current rapidly.But this SCR trigger voltage is generally higher, can not effectively protect for 5V and following operating voltage.

Summary of the invention

The invention provides a kind of bidirectional triode thyristor that is used for the radio frequency integrated circuit electrostatic discharge protective, this device trigger voltage is low, and parasitic capacitance is little.

A kind of bidirectional triode thyristor that is used for the radio frequency integrated circuit electrostatic discharge protective comprises P type substrate, a N trap and the 2nd N trap that described P type substrate is provided with the P trap and is positioned at P trap both sides;

The one N trap top is provided with a N+ injection region, a P+ injection region and the 3rd P+ injection region that isolates by shallow trench from outside to inside successively, and the 3rd P+ injection region is across the intersection of a N trap and P trap;

The 2nd N trap top is provided with the 2nd N+ injection region, the 2nd P+ injection region and the 4th N+ injection region that isolates by shallow trench from outside to inside successively, and wherein the 4th N+ injection region is across the intersection of the 2nd N trap and P trap;

P trap surface is covered with grid oxygen and the polysilicon gate that stacks gradually from bottom to up between the 3rd N+ injection region and the 4th N+ injection region.

The present invention also provides the application of above-mentioned bidirectional triode thyristor in electrostatic discharge protective, comprising:

The one N+ injection region is connected electrical anode with a P+ injection region, and the 2nd N+ injection region is connected electrical cathode with the 2nd P+ injection region.

The 3rd N+ injection region is equivalent to the drain electrode of NMOS structure in the bidirectional triode thyristor of the present invention, the 4th N+ injection region is equivalent to the source electrode of NMOS structure, the polysilicon gate of grid oxygen top is equivalent to the grid of NMOS structure, and the p type island region territory of polysilicon gate below is the raceway groove of NMOS structure.

With respect to traditional controllable silicon, bidirectional triode thyristor of the present invention utilizes the NMOS source to leak the break-through auxiliary triggering, and cut-in voltage and parasitic capacitance are little, and robust performance is strong, and the bi-directional ESD protection can be provided.

Description of drawings

Fig. 1 is the structural representation of existing ESD protective device;

Fig. 2 is the equivalent circuit diagram of protective device shown in Figure 1;

Fig. 3 is the profile of bi-directional ESD protective device of the present invention;

Fig. 4 is the vertical view of bi-directional ESD protective device shown in Figure 3;

Fig. 5 is the equivalent circuit diagram of bi-directional ESD protective device shown in Figure 3.

Embodiment

As shown in Figure 3 and Figure 4, a kind of controllable silicon that is used for electrostatic discharge protective, this controllable silicon comprise 4 layers, and wherein bottom is a P type substrate 31, the second layer is P trap 33, a N trap 32a and the 2nd N trap 32b that is arranged on the P type substrate, and wherein a N trap 32a and the 2nd N trap 32b are positioned at the both sides of P trap 33.

The 3rd layer for being arranged on 4 N+ injection regions and 2 the P+ injection regions on the N trap, wherein N trap 32a top is provided with a N+ injection region 35a, a P+ injection region 37a and the 3rd N+ injection region 39a from outside to inside successively, isolate by shallow trench 36a between the one a N+ injection region 35a and the P+ injection region 37a, isolate by shallow trench 38a between the one P+ injection region 37a and the 3rd N+ injection region 39a, the 3rd N+ injection region 39a is across the intersection of a N trap 32a and P trap 33.

The 2nd N trap 32b top is provided with the 2nd N+ injection region 35b, the 2nd P+ injection region 37b and the 4th N+ injection region 39b from outside to inside successively, isolate by shallow trench 36b between the 2nd N+ injection region 35b and the 2nd P+ injection region 37b, isolate by shallow trench 38b between the 2nd P+ injection region 37b and the 4th N+ injection region 39b, the 4th N+ injection region 39b is across the intersection of the 2nd N trap 32a and P trap 33.

P trap 33 surfaces between the 3rd N+ injection region 39a and the 4th N+ injection region 39b are covered with grid oxygen 40 and the polysilicon gate 41 that stacks gradually from bottom to up.

During application, a N+ injection region 35a and a P+ injection region 37a all insert electrical anode, and the 2nd P+ injection region 37b and the 2nd N+ injection region 35b all insert electrical cathode.

From the electrical anode to the electrical cathode, the SCR path is a P+ injection region 37a-N trap 32 and the 3rd N+ injection region 39a-P trap 33-the 2nd N trap 34 and the 4th N+ injection region 39b, constitutes the P-N-P-N SCR structure.From the electrical cathode to the electrical anode, the SCR path is the 2nd P+ injection region 37b-the 2nd N trap 34-P trap 33-the one a N trap 32 and a N+ injection region 35a, constitutes reverse P-N-P-N SCR structure.

As shown in Figure 5, by a P+ injection region 37a, a N trap 32 and P trap 33 constitute PNP parasitic transistor Q1; By a N trap 32, P trap 33 and the 2nd N trap 34 constitute NPN parasitic transistor Q2; Constitute PNP parasitic transistor Q3 by P trap 33, the two N traps 34 and the 2nd P+ injection region 37b.

When the ESD signal appears in anode, being added in voltage bigger on the N trap can cause the source knot of NMOS on the P trap and the depletion region of drain junction to be widened, when the grid of NMOS long less be channel length more in short-term, break-through can take place in the source drain depletion region of NMOS under ESD voltage, the punchthrough current that produces flows to the 2nd N trap from a N trap through the P trap, when electric current flows through the cut-in voltage of the pressure drop of N trap dead resistance generation greater than parasitic PNP triode Q1, PNP parasitic triode Q1 opens, simultaneously because positive feedback is also opened NPN parasitic triode Q2, the whole SCR device that is made of PNP parasitic transistor Q1 and NPN parasitic transistor Q2 is switched on, the ESD electric current that begins to release is clamped down on the device both end voltage simultaneously than electronegative potential.Same principle, because symmetrical configuration when the ESD signal appears in negative electrode, is leaked break-through by the source of P trap top NMOS, the reverse SCR that is made of PNP parasitic transistor Q3 and NPN parasitic transistor Q2 can open smoothly, the ESD electric current of releasing.

In actual applications, the channel length that changes the length of polysilicon gate and grid oxygen in this patent of invention and be NMOS can be adjusted the cut-in voltage of SCR, can adjust the clamp voltage of SCR by adjusting the device anode cathode separation.In application, by rationally being set, NMOS grid length under the normal level signal, can not open, and when the electrostatic induced current signal arrives, smoothly the auxiliary triggering ESD electric current of releasing to guarantee entire device.

Claims

1. A bidirectional thyristor for radio frequency integrated circuit electrostatic discharge protection, comprising a P-type substrate, characterized in that: the P-type substrate is provided with a P well and the first N on both sides of the P well. well and a second N well;

The first N+ implantation region, the first P+ implantation region, and the third N+ implantation region separated by shallow moats are sequentially provided above the first N well from outside to inside, and the third N+ implantation region spans between the first N well and the P well. Junction;

The second N+ implantation region, the second P+ implantation region and the fourth N+ implantation region which are isolated from the outside to the inside by shallow moats are sequentially arranged above the second N well, wherein the fourth N+ implantation region straddles the second N well and the P well at the junction of;

The surface of the P well between the third N+ implantation region and the fourth N+ implantation region is covered with gate oxide and polysilicon gate stacked sequentially from bottom to top.