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CN100470804C - A Protection Circuit Using Polysilicon to Construct ESD Discharge Channel - Google Patents

A Protection Circuit Using Polysilicon to Construct ESD Discharge Channel Download PDF

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CN100470804C
CN100470804C CNB2007100675172A CN200710067517A CN100470804C CN 100470804 C CN100470804 C CN 100470804C CN B2007100675172 A CNB2007100675172 A CN B2007100675172A CN 200710067517 A CN200710067517 A CN 200710067517A CN 100470804 C CN100470804 C CN 100470804C
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polysilicon
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implantation
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CN101017819A (en
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韩雁
崔强
董树荣
霍明旭
黄大海
杜宇禅
曾才赋
洪慧
陈茗
杜晓阳
斯瑞珺
张吉皓
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Zhejiang University ZJU
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Abstract

本发明涉及一种静电放电防护电路。现有的可控硅SCR防静电的效果不理想,触发点电压值不能够灵活调整。本发明在现有的可控硅SCR上设置有多晶硅层,多晶硅层与阱区之间设置SiO2氧化层,多晶硅层两边为P+多晶硅注入区和N+多晶硅注入区,中间为本征多晶硅区。本征多晶硅区和SiO2氧化层上打有通孔,阱区上对应通孔的位置设置有环形浅壕沟隔离STI,环形浅壕沟隔离STI内设置N+注入区。采用本发明结构,相当于一个P-I-N或N-I-P结构的多晶硅和传统的可控硅SCR并联,提高了静电防护的性能,同时可以通过改变本征多晶硅的长度调整P-I-N或N-I-P结构的触发电压值,进而灵活调整该防护电路的触发电压值。

Figure 200710067517

The invention relates to an electrostatic discharge protection circuit. The antistatic effect of the existing thyristor SCR is not ideal, and the voltage value of the trigger point cannot be adjusted flexibly. In the present invention, a polysilicon layer is arranged on the existing thyristor SCR, and an SiO2 oxide layer is arranged between the polysilicon layer and the well region. The two sides of the polysilicon layer are P+ polysilicon implantation regions and N+ polysilicon implantation regions, and the middle is an intrinsic polysilicon region. Through holes are drilled on the intrinsic polysilicon region and the SiO2 oxide layer, and an annular shallow moat isolation STI is arranged at the position corresponding to the through hole on the well region, and an N+ implantation region is arranged in the annular shallow moat isolation STI. Adopting the structure of the present invention, equivalent to a PIN or NIP structure of polysilicon and traditional thyristor SCR in parallel, improves the performance of electrostatic protection, and at the same time can adjust the trigger voltage value of PIN or NIP structure by changing the length of intrinsic polysilicon, and then The trigger voltage value of the protection circuit can be flexibly adjusted.

Figure 200710067517

Description

一种利用多晶硅构建ESD泄放通道的防护电路 A Protection Circuit Using Polysilicon to Construct ESD Discharge Channel

技术领域 technical field

本发明属于集成电路技术领域,特别涉及一种利用多晶硅版图层次构造静电电流泄放通道的静电放电防护电路。The invention belongs to the technical field of integrated circuits, and in particular relates to an electrostatic discharge protection circuit using polysilicon layout layers to construct electrostatic current discharge channels.

背景技术 Background technique

静电放电是在一个集成电路浮接的情况下,大量的电荷从外向内灌入集成电路的瞬时过程,整个过程大约耗时100ns。此外,在集成电路放电时会产生数百甚至数千伏特的高压,这会打穿集成电路中的输入级的栅氧化层。随着集成电路中的MOS管的尺寸越来越小,栅氧化层的厚度也越来越薄,在这种趋势下,使用高性能的静电防护电路来泄放静电放电的电荷以保护栅极氧化层不受损害是十分必需的。Electrostatic discharge is an instantaneous process in which a large amount of charge is poured into the integrated circuit from the outside to the inside when an integrated circuit is floating, and the whole process takes about 100ns. In addition, hundreds or even thousands of volts of high voltage will be generated when the integrated circuit is discharged, which will break through the gate oxide layer of the input stage in the integrated circuit. As the size of MOS transistors in integrated circuits is getting smaller and smaller, the thickness of the gate oxide layer is also getting thinner. Under this trend, high-performance electrostatic protection circuits are used to discharge electrostatic discharge charges to protect the gate. It is essential that the oxide layer is not damaged.

静电放电现象的模式主要有四种:人体放电模式(HBM)、机械放电模式(MM)、器件充电模式(CDM)以及电场感应模式(FIM)。对一般集成电路产品来说,一般要经过人体放电模式,机械放电模式以及器件充电模式的测试。为了能够承受如此高的静电放电电压,集成电路产品通常必须使用具有高性能、高耐受力的静电放电保护器件。There are four main modes of ESD phenomena: Human Body Model (HBM), Mechanical Discharge Mode (MM), Charged Device Mode (CDM) and Field Induction Mode (FIM). For general integrated circuit products, it generally has to go through the tests of human body discharge mode, mechanical discharge mode and device charging mode. In order to be able to withstand such a high ESD voltage, integrated circuit products usually must use ESD protection devices with high performance and high endurance.

为了达成保护芯片抵御静电袭击的目的,目前已有多种静电防护器件被提出,比如二极管,栅极接地的MOS管,其中公认效果比较好的防护器件是可控硅SCR(silicon controlled rectifier)。该防护器件的具体结构如图1所示,P型衬底11上为阱区,阱区包括N阱12和P阱16,N阱12和P阱16上均有两个注入区,分别是N+注入区14和P+注入区15。其中N阱12的N+注入区设置在远离P阱16的一端,P+注入区设置在靠近P阱16的一端;P阱16的P+注入区设置在远离N阱12的一端,N+注入区设置在靠近N阱12的一端。一N+注入区设置在N阱12和P阱16连接处上方并跨接在N阱12和P阱16之间,所有注入区之间是用浅壕沟隔离STI 13进行隔离。N阱12的N+注入区和P+注入区接电学阳极Anode,P阱16的N+注入区和P+注入区接电学阴极Cathode。图2是和这个SCR结构相对应的电原理图。在集成电路的正常操作下,静电放电保护器件是处于关闭的状态,不会影响集成电路输入输出接合垫上的电位。而在外部的静电灌入集成电路而产生瞬间的高电压的时候,这个器件会开启导通,迅速地排放掉静电电流。但是该可控硅SCR在恶劣的静电环境下防静电的效果不是非常理想,同时该可控硅SCR触发点电压值不能够灵活地调整。In order to achieve the purpose of protecting chips against electrostatic attacks, a variety of electrostatic protection devices have been proposed, such as diodes and MOS transistors with grounded gates. Among them, the silicon controlled rectifier (SCR) is recognized as a better protection device. The specific structure of the protection device is shown in Figure 1. The P-type substrate 11 is a well region, and the well region includes an N well 12 and a P well 16. Both the N well 12 and the P well 16 have two injection regions, respectively N+ implantation region 14 and P+ implantation region 15 . Wherein the N+ implantation region of the N well 12 is arranged at an end away from the P well 16, and the P+ implantation region is arranged at an end close to the P well 16; the P+ implantation region of the P well 16 is arranged at an end far away from the N well 12, and the N+ implantation region is arranged at close to one end of the N well 12. An N+ implantation region is set above the junction of the N well 12 and the P well 16 and bridged between the N well 12 and the P well 16, and all the implantation regions are isolated by shallow moat isolation STI 13. The N+ implantation region and the P+ implantation region of the N well 12 are connected to the electrical anode Anode, and the N+ implantation region and the P+ implantation region of the P well 16 are connected to the electrical cathode Cathode. Figure 2 is an electrical schematic diagram corresponding to this SCR structure. Under normal operation of the integrated circuit, the electrostatic discharge protection device is in a closed state and will not affect the potential on the input and output bonding pads of the integrated circuit. When external static electricity is poured into the integrated circuit to generate an instantaneous high voltage, the device will turn on and discharge the static electricity quickly. However, the anti-static effect of the thyristor SCR in a harsh electrostatic environment is not ideal, and at the same time, the voltage value of the trigger point of the thyristor SCR cannot be adjusted flexibly.

发明内容 Contents of the invention

本发明的目的就是针对现有技术的不足,提供一种可以灵活调整触发点电压值,并且可以有效提高防护静电能力的防护电路。The purpose of the present invention is to provide a protection circuit that can flexibly adjust the voltage value of the trigger point and effectively improve the ability to protect against static electricity, aiming at the deficiencies of the prior art.

本发明的静电放电防护电路包括P型衬底,P型衬底上为阱区,阱区包括N阱和P阱。N阱和P阱上均设有两个注入区,分别是N+注入区和P+注入区。其中N阱的N+注入区设置在远离P阱的一端,P+注入区设置在靠近P阱的一端;P阱的P+注入区设置在远离N阱的一端,N+注入区设置在靠近N阱的一端;N阱和P阱上的N+注入区和P+注入区用浅壕沟隔离STI进行隔离。在阱区上方对应N阱的P+注入区与P阱的N+注入区之间位置设置有多晶硅层,多晶硅层与阱区之间设置SiO2氧化层,多晶硅层的一边掺入P型杂质形成P+多晶硅注入区,另一边掺入N型杂质形成N+多晶硅注入区,中间为本征多晶硅区。本征多晶硅区和SiO2氧化层上打有通孔,阱区上对应通孔的位置设置有环形浅壕沟隔离STI,通孔的内壁与环形浅壕沟隔离STI的外沿相对应,环形浅壕沟隔离STI内设置N+注入区,环形浅壕沟隔离STI和N+注入区跨接在N阱和P阱之间。The electrostatic discharge protection circuit of the present invention includes a P-type substrate, on which is a well region, and the well region includes an N well and a P well. Both the N well and the P well are provided with two implantation regions, which are N+ implantation regions and P+ implantation regions respectively. The N+ implantation region of the N well is set at the end far away from the P well, and the P+ implantation region is set at one end close to the P well; the P+ implantation region of the P well is set at the end far away from the N well, and the N+ implantation region is set at one end close to the N well ; The N+ implantation region and the P+ implantation region on the N well and the P well are isolated by shallow moat isolation STI. A polysilicon layer is arranged between the P+ implantation region corresponding to the N well and the N+ implantation region of the P well above the well region, and a SiO2 oxide layer is arranged between the polysilicon layer and the well region, and one side of the polysilicon layer is doped with P-type impurities to form P+ A polysilicon implantation region, the other side is doped with N-type impurities to form an N+ polysilicon implantation region, and the middle is an intrinsic polysilicon region. There are through holes on the intrinsic polysilicon region and the SiO2 oxide layer, and an annular shallow moat isolation STI is arranged at the position corresponding to the through hole on the well region. The inner wall of the through hole corresponds to the outer edge of the annular shallow moat isolation STI, and the annular shallow moat isolation STI An N+ implantation region is set in the isolation STI, and the annular shallow moat isolation STI and the N+ implantation region are bridged between the N well and the P well.

本发明中的P型衬底、N阱和P阱采用现有的可控硅SCR对应的结构和工艺,SiO2氧化层采用现有通用的淀积等工艺即可实现。The P-type substrate, N well and P well in the present invention adopt the structure and process corresponding to the existing thyristor SCR, and the SiO2 oxide layer can be realized by using the existing common deposition and other processes.

本发明在传统SCR的结构基础上利用了多晶硅版图层次构造静电电流泄放通路。如果在N阱上面的多晶硅外端掺杂P型杂质构成P+多晶硅注入区,在P阱上面的多晶硅外端掺杂N型杂质构成N+多晶硅注入区。这样相当于一个P-I-N结构的多晶硅和传统的可控硅SCR并联。因此,在不增加布局面积的情况下,静电电流的泄放电流的通道增加了,静电防护的性能提高了。同时我们可以通过改变本征多晶硅的长度(P+多晶硅注入区和N+多晶硅注入区的间隔距离)来调整P-I-N结构的触发电压值,进而灵活调整该防护电路的触发电压值。Based on the structure of the traditional SCR, the present invention utilizes polysilicon layout layers to construct electrostatic current discharge paths. If the outer end of the polysilicon above the N well is doped with P-type impurities to form a P+ polysilicon implantation region, the outer end of the polysilicon above the P well is doped with N-type impurities to form an N+ polysilicon implantation region. This is equivalent to a P-I-N structure of polysilicon and a traditional thyristor SCR in parallel. Therefore, without increasing the layout area, the discharge current channel of the electrostatic current is increased, and the performance of electrostatic protection is improved. At the same time, we can adjust the trigger voltage value of the P-I-N structure by changing the length of the intrinsic polysilicon (the distance between the P+ polysilicon implant region and the N+ polysilicon implant region), and then flexibly adjust the trigger voltage value of the protection circuit.

如果在N阱上面的多晶硅外端掺杂N型杂质构成N+多晶硅注入区,在P阱上面的多晶硅外端掺杂P型杂质构成P+多晶硅注入区。这样相当于一个N-I-P结构的多晶硅和传统的可控硅SCR并联。因此,在不增加布局面积的情况下,静电电流的泄放电流的通道增加了,静电防护的性能提高了。同时我们可以通过改变本征多晶硅的长度(P+多晶硅注入区和N+多晶硅注入区的间隔距离)来调整N-I-P结构的触发电压值,进而灵活调整该防护电路的触发电压值。If the outer end of the polysilicon above the N well is doped with N-type impurities to form an N+ polysilicon implantation region, the outer end of the polysilicon above the P well is doped with P-type impurities to form a P+ polysilicon implantation region. This is equivalent to an N-I-P structure of polysilicon and a traditional thyristor SCR in parallel. Therefore, without increasing the layout area, the discharge current channel of the electrostatic current is increased, and the performance of electrostatic protection is improved. At the same time, we can adjust the trigger voltage value of the N-I-P structure by changing the length of the intrinsic polysilicon (the distance between the P+ polysilicon implant region and the N+ polysilicon implant region), and then flexibly adjust the trigger voltage value of the protection circuit.

附图说明 Description of drawings

图1为现有技术的可控硅SCR静电放电防护器件的剖面图;1 is a cross-sectional view of a prior art thyristor SCR electrostatic discharge protection device;

图2为图1的等效电原理图;Fig. 2 is the equivalent electrical schematic diagram of Fig. 1;

图3为本发明实施例的剖面图;Fig. 3 is the sectional view of the embodiment of the present invention;

图4为图3的俯视图;Fig. 4 is the top view of Fig. 3;

图5为图3的等效电原理图。FIG. 5 is an equivalent electrical schematic diagram of FIG. 3 .

具体实施方式 Detailed ways

结合说明书附图和实施例对本发明做进一步说明。The present invention will be further described in conjunction with the drawings and embodiments of the description.

如图3和图4所示,一种利用多晶硅构建ESD泄放通道的防护电路包括P型衬底30,P型衬底30上为阱区,阱区包括N阱31和P阱39。N阱31和P阱39上均设有两个注入区,分别是N+注入区32a和P+注入区34。其中N阱31的N+注入区32a设置在远离P阱39的一端,P+注入区34设置在靠近P阱39的一端;P阱39的P+注入区34设置在远离N阱31的一端,N+注入区32a设置在靠近N阱31的一端;N阱31和P阱39上的N+注入区32a和P+注入区34用浅壕沟隔离STI 33a进行隔离。在阱区上方对应N阱31的P+注入区34与P阱39的N+注入区32a之间位置设置有多晶硅层,多晶硅层与阱区之间设置SiO2氧化层38,多晶硅层的一边掺入P型杂质形成P+多晶硅注入区35,另一边掺入N型杂质形成N+多晶硅注入区37,中间为本征多晶硅区36。本征多晶硅区36和SiO2氧化层38上打有通孔41,阱区上对应通孔41的位置设置有环形浅壕沟隔离STI 33b,通孔41的内壁与环形浅壕沟隔离STI 33b的外沿相对应,环形浅壕沟隔离STI 33b内设置N+注入区32b,环形浅壕沟隔离STI33b和N+注入区32b跨接在N阱31和P阱39之间。As shown in FIG. 3 and FIG. 4 , a protection circuit using polysilicon to construct an ESD discharge channel includes a P-type substrate 30 on which is a well region, and the well region includes an N well 31 and a P well 39 . Both the N well 31 and the P well 39 are provided with two implanted regions, which are N+ implanted region 32 a and P+ implanted region 34 . Wherein the N+ implantation region 32a of the N well 31 is arranged on one end away from the P well 39, and the P+ implantation region 34 is arranged on one end close to the P well 39; Region 32a is disposed near one end of N well 31; N+ implant region 32a and P+ implant region 34 on N well 31 and P well 39 are isolated by shallow trench isolation STI 33a. A polysilicon layer is arranged between the P+ implantation region 34 of the N well 31 and the N+ implantation region 32a of the P well 39 above the well region, and a SiO2 oxide layer 38 is arranged between the polysilicon layer and the well region, and one side of the polysilicon layer is doped with P-type impurities form a P+ polysilicon implantation region 35 , the other side is doped with N-type impurities to form an N+ polysilicon implantation region 37 , and the middle is an intrinsic polysilicon region 36 . The intrinsic polysilicon region 36 and the SiO2 oxide layer 38 are drilled with a through hole 41, and the position corresponding to the through hole 41 on the well region is provided with an annular shallow moat isolation STI 33b, and the inner wall of the through hole 41 is separated from the outer surface of the annular shallow moat isolation STI 33b. Correspondingly, an N+ implantation region 32b is provided in the annular shallow trench isolation STI 33b , and the annular shallow trench isolation STI 33b and the N+ implantation region 32b are bridged between the N well 31 and the P well 39 .

工作中,如果在N阱上面的多晶硅外端掺杂P型杂质构成P+多晶硅注入区,在P阱上面的多晶硅外端掺杂N型杂质构成N+多晶硅注入区。这样相当于一个P-I-N结构的多晶硅和传统的可控硅SCR并联(如图5所示)。当电学阳极输入正常信号电平时,该防护器件不会导通干扰芯片内部电路的正常工作。而在危险的静电信号到来的时候,本征多晶硅正向贯通从而泄放静电电流,从而使输入缓冲器51能够抵御外界的静电冲击。In operation, if the outer end of the polysilicon above the N well is doped with P-type impurities to form a P+ polysilicon implantation region, the outer end of the polysilicon above the P well is doped with N-type impurities to form an N+ polysilicon implantation region. This is equivalent to a P-I-N structure of polysilicon and a traditional thyristor SCR in parallel (as shown in Figure 5). When the electrical anode inputs a normal signal level, the protection device will not conduct and interfere with the normal operation of the internal circuit of the chip. When a dangerous static signal arrives, the intrinsic polysilicon penetrates forward to discharge the static current, so that the input buffer 51 can resist the external static impact.

Claims (1)

1、一种利用多晶硅构建ESD泄放通道的防护电路,包括P型衬底(30),P型衬底(30)上为阱区,阱区包括N阱(31)和P阱(39),其特征在于N阱(31)和P阱(39)上均设有两个注入区,分别是N+注入区(32a)和P+注入区(34);其中N阱(31)的N+注入区(32a)设置在远离P阱(39)的一端,P+注入区(34)设置在靠近P阱(39)的一端;P阱(39)的P+注入区(34)设置在远离N阱(31)的一端,N+注入区(32a)设置在靠近N阱(31)的一端;N阱(31)和P阱(39)上的N+注入区(32a)和P+注入区(34)用浅壕沟隔离STI(33a)进行隔离;1. A protection circuit utilizing polysilicon to construct an ESD discharge channel, comprising a P-type substrate (30), a well region on the P-type substrate (30), and the well region comprising an N well (31) and a P well (39) , it is characterized in that two injection regions are arranged on the N well (31) and the P well (39), which are respectively an N+ implant region (32a) and a P+ implant region (34); wherein the N+ implant region of the N well (31) (32a) is arranged on one end away from the P well (39), and the P+ implantation region (34) is arranged on one end near the P well (39); the P+ implantation region (34) of the P well (39) is arranged on the N well (31) ), the N+ implantation region (32a) is arranged at one end near the N well (31); the N+ implantation region (32a) and the P+ implantation region (34) on the N well (31) and the P well (39) use a shallow moat isolate STI (33a) for isolation; 在阱区上方对应N阱(31)的P+注入区(34)与P阱(39)的N+注入区(32a)之间位置设置有多晶硅层,多晶硅层与阱区之间设置SiO2氧化层(38),多晶硅层的一边掺入P型杂质形成P+多晶硅注入区(35),另一边掺入N型杂质形成N+多晶硅注入区(37),中间为本征多晶硅区(36);A polysilicon layer is arranged between the P+ implantation region (34) of the N well (31) and the N+ implantation region (32a) of the P well (39) above the well region, and a SiO2 oxide layer is arranged between the polysilicon layer and the well region (38), one side of the polysilicon layer is doped with P-type impurities to form a P+ polysilicon implantation region (35), and the other side is doped with N-type impurities to form an N+ polysilicon implantation region (37), and the middle is an intrinsic polysilicon region (36); 本征多晶硅区(36)和SiO2氧化层(38)上打有通孔(41),阱区上对应通孔(41)的位置设置有环形浅壕沟隔离STI(33b),通孔(41)的内壁与环形浅壕沟隔离STI(33b)的外沿相对应;环形浅壕沟隔离STI(33b)内设置N+注入区(32b),环形浅壕沟隔离STI(33b)和N+注入区(32b)跨接在N阱(31)和P阱(39)之间。Intrinsic polysilicon region (36) and SiO Oxide layer (38) is drilled with through hole (41), and the position corresponding to through hole (41) on the well region is provided with annular shallow moat isolation STI (33b), through hole (41 ) corresponding to the outer edge of the annular shallow trench isolation STI (33b); the annular shallow trench isolation STI (33b) is provided with an N+ injection region (32b), and the annular shallow trench isolation STI (33b) and the N+ implantation region (32b) It is connected between the N well (31) and the P well (39).
CNB2007100675172A 2007-03-05 2007-03-05 A Protection Circuit Using Polysilicon to Construct ESD Discharge Channel Expired - Fee Related CN100470804C (en)

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