CN102034798B - Packaging structure and packaging process - Google Patents

Abstract

The invention discloses a packaging structure and a packaging process, wherein the packaging structure comprises a circuit substrate, a first chip module, a second chip module and a packaging colloid. The circuit substrate has a carrying surface, and the first chip module and the second chip module are adjacently arranged on the carrying surface. The first chip module has a plurality of first external contacts, and the first external contacts have a first pitch. The second wafer module is provided with a plurality of second pairs of external connection points, a second distance is formed between the second pairs of external connection points, and the first distance is larger than the second distance. The packaging colloid is arranged on the bearing surface and covers the first chip module and the second chip module, and the packaging colloid is provided with a plurality of first openings and a plurality of second openings. The first openings respectively expose the first pair of external contacts, and the second openings respectively expose the second pair of external contacts.

Description

Packaging structure and packaging process

technical field

The present invention relates to a packaging structure and a packaging process, and in particular to a packaging structure and a packaging process using side by side chip configuration.

Background technique

System-in-package technology (SIP) is a technology that integrates two or more chips with independent functions at the wafer level into a single package. Its advantages include not only small size, but also the fact that each functional chip can be developed independently, so the Packaging technology has faster development speed and lower development cost than System-on-Chip (SoC).

Stacked package (Package on Package, POP) process is a common assembly method in system-in-package technology, which is to stack the packaging units of chips with different functions, such as stacking the memory chip packaging unit on the logic chip packaging unit. However, various memory chip package units with different specifications usually have different pin layouts. Without additional circuit layout adjustments, the pin layout of the underlying chip package unit (such as the logic chip package unit) can only be used to carry a specific memory chip package unit. In this way, the compatibility and expandability of the system-in-package technology are relatively limited.

Contents of the invention

The invention provides a packaging structure, which can effectively integrate multiple chip modules with different pin layouts, so as to improve the compatibility and expandability of the subsequent stacked packaging process.

The present invention also provides the manufacturing process of the aforementioned packaging structure, which is used to integrate multiple chip modules with different pin layouts, so as to provide good compatibility and expandability.

In order to specifically describe the content of the present invention, a package structure is proposed here, including a circuit substrate, a first chip module, a second chip module, and an encapsulant. The circuit substrate has a carrying surface, and the first chip module and the second chip module are adjacently arranged on the carrying surface. The first chip module has a plurality of first outer junctions, and there is a first distance between every two adjacent first outer junctions. The second chip module has a plurality of second outer junctions, and there is a second distance between every two adjacent second outer junctions, wherein the first distance is greater than the second distance. In addition, the encapsulant is disposed on the carrying surface and covers the first chip module and the second chip module, and the encapsulant has a plurality of first openings and a plurality of second openings. The first openings respectively expose the first external contacts, and the second openings respectively expose the second external contacts.

In one embodiment, the first chip module includes a first chip and a plurality of first solder balls. The first chip is arranged on the carrying surface, and the circuit board has a plurality of first welding pads arranged on the carrying surface on the periphery of the first chip, and the first chip is electrically connected to the first welding pads. The first solder balls are respectively arranged on the first solder pads to serve as first external contacts.

In one embodiment, the first chip module includes a first chip and a plurality of first solder balls. The first chip is disposed on the carrying surface, and a top surface of the first chip has a plurality of first welding pads. The first solder balls are respectively arranged on the first solder pads to serve as first external contacts.

In one embodiment, the second chip module includes a second chip and a plurality of second solder balls. The second chip is arranged on the carrying surface, and the circuit substrate has a plurality of second welding pads arranged on the carrying surface on the periphery of the second chip, and the second chip is electrically connected to the second welding pads. The second solder balls are respectively arranged on the second solder pads to serve as second external contacts.

In one embodiment, the second chip module includes a second chip and a plurality of second solder balls. The second chip is arranged on the carrying surface, and a top surface of the second chip has a plurality of second welding pads. The second solder balls are respectively arranged on the second solder pads to serve as second external contacts.

In one embodiment, the package structure further includes a first external component disposed above the first chip and bonded to the first external contact.

In one embodiment, the package structure further includes a second external component disposed above the second chip and bonded to the second external contact.

In one embodiment, the package structure further includes a plurality of third solder balls disposed on a bottom surface of the circuit substrate opposite to the carrying surface.

The invention also proposes a packaging process. Firstly, a circuit substrate is provided, and the circuit substrate has a carrying surface. Next, a first chip module and a second chip module are arranged adjacently on the carrying surface. The first chip module has a plurality of first outer junctions, and there is a first distance between every two adjacent first outer junctions. The second chip module has a plurality of second outer junctions, and there is a second distance between every two adjacent second outer junctions, wherein the first distance is not equal to the second distance. Then, an encapsulation compound is formed on the carrying surface to cover the first chip module and the second chip module. Afterwards, a plurality of first openings and a plurality of second openings are formed in the encapsulant, the first openings respectively expose the first external contacts, and the second openings respectively expose the second external contacts.

In one embodiment, the circuit substrate has a plurality of first bonding pads and a plurality of second bonding pads on the carrying surface, and the method for arranging the first chip module and the second chip module adjacently includes: A plurality of first solder balls are formed on the first pads to serve as first external contacts, and a plurality of second solder balls are respectively formed on the second pads to serve as second external contacts; and a first first solder ball is adjacently arranged. A chip and a second chip are placed on the carrying surface, and the first chip and the second chip are bonded to the circuit substrate. The first bonding pad is located on the carrying surface of the first chip and is electrically connected to the first chip, and the second bonding pad is located on the carrying surface of the second chip and is electrically connected to the second chip.

In one embodiment, the circuit substrate has a plurality of first pads on the carrying surface, and the method for arranging the first chip module and the second chip module adjacently includes: forming a plurality of pads on the first pads respectively. The first solder ball is used as the first external connection point; a first chip and a second chip are adjacently arranged on the carrying surface, and the first chip and the second chip are bonded to the circuit substrate, wherein the first pad is located on the second chip. On the carrying surface of a chip periphery and electrically connected to the first chip, and a top surface of the second chip has a plurality of second soldering pads; and, forming a plurality of second soldering balls on the second soldering pads respectively, as The second pair of junctions.

In one embodiment, the method for arranging a first chip module and a second chip module adjacently includes: arranging a first chip and a second chip adjacently on a carrier surface, and bonding the first chip and the second chip Two wafers to circuit substrates, wherein a top surface of the first wafer has a plurality of first welding pads, and a top surface of the second wafer has a plurality of second welding pads; respectively form a plurality of first welding pads on the first welding pads balls as the first external contact points; and forming a plurality of second solder balls on the second solder pads respectively to serve as the second external contact points.

In one embodiment, the packaging process further includes forming a plurality of third solder balls on a bottom surface of the circuit substrate opposite to the carrying surface.

In one embodiment, the method of forming the first opening and the second opening in the encapsulant includes laser ablation.

In one embodiment, the packaging process further includes disposing a first external component above the first chip module, and bonding the first external component to the first external contact.

In one embodiment, the packaging process further includes disposing a second external component above the second chip module, and bonding the second external component to the second external contact.

Based on the above, the packaging structure and packaging process of the present invention integrate multiple chip modules with different pin layouts (that is, different contact pitches), so they can be compatible with a variety of external components of different specifications at the same time, and have good compatibility. sex and expandability.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Description of drawings

Fig. 1 is a kind of packaging structure of an embodiment of the present invention;

FIG. 2 is a stacked packaging structure obtained after the packaging structure in FIG. 1 is subjected to a stacked packaging process;

Fig. 3 is the manufacturing process of the packaging structure in Fig. 1 and Fig. 2;

FIG. 4 is a package structure of another embodiment of the present invention;

FIG. 5 is a stacked packaging structure obtained after the packaging structure in FIG. 4 is subjected to a stacked packaging process;

Fig. 6 is the manufacturing process of the packaging structure in Fig. 4 and Fig. 5;

FIG. 7 is a packaging structure according to another embodiment of the present invention;

FIG. 8 is a stacked packaging structure obtained after the packaging structure in FIG. 7 is subjected to a stacked packaging process;

FIG. 9 is a manufacturing process of the package structure shown in FIG. 7 and FIG. 8 .

Explanation of reference signs

100, 400, 700: package structure; 110, 410, 710-circuit substrate;

112, 412, 712 - bearing surface; 114, 414, 726 - first pad;

116, 436, 736-the second welding pad; 118, 418, 718-the bottom surface;

119, 419, 719-the third welding pad; 120, 420, 720-the first chip module;

122, 422, 722-first chip; 124, 424, 724-first solder ball;

132, 432, 732-second chip; 134, 434, 734-second solder ball;

140, 440, 740-encapsulation colloid; 142, 442, 742-first opening;

144, 444, 744-the second opening; 130, 430, 730-the second chip module;

160, 460, 760 - third solder ball; 170, 470, 770 - first external component;

172, 472, 772-welding pads; 180, 480, 780-second external components;

182, 482, 782-welding pads; 432a, 722a, 732a-top surface;

P1-first pitch; P2-second pitch;

152, 154, 452, 454, 752, 754-wire.

Detailed ways

In the present invention, a first chip module and a second chip module with different pin layouts are adjacently arranged on the carrying surface of a circuit substrate. More specifically, there is, for example, a first distance between the plurality of first external connections of the first chip module, and there is, for example, a second distance between the plurality of second external connections of the second chip module, and the first The first pitch is greater than the second pitch. In addition, the encapsulant covering the carrying surface exposes the first external contact point and the second external contact point for bonding the first chip module and the second chip module to external components.

The packaging structure and packaging process can be applied to system-in-package (SIP) or other applicable technical fields. The first chip module and the second chip module are, for example, logic chip modules, and are used for bonding with an upper memory chip module. In addition, as the specifications of the upper components are different, the pins of the first chip module and the second chip module can choose to adopt fan-in or fan-out design. Several embodiments will be given below to illustrate the various design changes.

FIG. 1 is a package structure of an embodiment of the present invention. As shown in FIG. 1 , the package structure 100 includes a circuit substrate 110 , a first chip module 120 , a second chip module 130 and an encapsulant 140 . Both the first chip module 120 and the second chip module 130 of this embodiment adopt a fan-out pin design. The circuit substrate 110 has a carrying surface 112 and a plurality of first bonding pads 114 and a plurality of second bonding pads 116 located on the carrying surface 112 . There is a first pitch P1 between every two adjacent first pads 114 , and there is a second pitch P2 between every two adjacent second pads 116 , and the first pitch P1 is greater than the second pitch P2 .

More specifically, the first chip module 120 includes a first chip 122 and a plurality of first solder balls 124, wherein the first chip 122 is disposed on the carrying surface 112, and the first solder pads 114 are located on the periphery of the first chip 122. . The first solder ball 124 is disposed on the first solder pad 114 . In this embodiment, the first chip 122 is electrically connected to the circuit substrate 110 through a plurality of wires 152 by wire bonding, and then electrically connected to the first pad through the internal circuit (not shown) of the circuit substrate 110. 114. Of course, the first chip 122 can also be electrically connected to the circuit substrate 110 by flip-chip bonding or other possible ways. In addition, the first solder balls 124 are respectively disposed on the first solder pads 114 to serve as the aforementioned first external contacts, and they also have the first pitch P1.

In addition, the second chip module 130 includes a second chip 132 and a plurality of second solder balls 134 , wherein the second chip 132 is disposed on the carrying surface 112 , and the second solder pads 116 are located on the periphery of the second chip 132 . The second solder ball 134 is disposed on the second solder pad 116 . In this embodiment, the second chip 132 is electrically connected to the circuit substrate 110 through a plurality of wires 154 by wire bonding, and then electrically connected to the second pad through the internal circuit (not shown) of the circuit substrate 110 116. Of course, the second chip 132 can also be electrically connected to the circuit substrate 110 by flip-chip bonding or other possible ways. In addition, the second solder balls 134 are respectively disposed on the second solder pads 116 to serve as the aforementioned second external contacts, and they also have the second pitch P2.

The encapsulant 140 is disposed on the carrying surface 112 and covers the first chip 122 and the second chip 132 . In addition, the encapsulant 140 has a plurality of first openings 142 and a plurality of second openings 144 for exposing the first solder balls 124 and the second solder balls 134 respectively.

Please refer to FIG. 1 again, the circuit substrate 110 can further have a bottom surface 118 opposite to the carrying surface 112 and a plurality of third pads 119 disposed on the bottom surface 118 . A third solder ball 160 may be disposed on each third pad 119 for connecting the package structure 100 to an external circuit, such as a printed circuit board.

FIG. 2 is a stacked package structure obtained after the package structure 100 in FIG. 1 is subjected to a package on package (Package on Package, POP) process. As shown in FIG. 2 , a first external component 170 and a second external component 180 are disposed above the first chip 122 and the second chip 132 respectively. Here, the first external component 170 and the second external component 180 are, for example, chip stacked packaging units. The first external component 170 has a plurality of solder pads 172 corresponding to the first pitch P1, and is bonded to the first solder ball 124 through the solder pads 172 and possibly additional solder balls formed on the solder pads 172 . The second external component 180 has a plurality of solder pads 182 corresponding to the second pitch P2, and is bonded to the second solder ball 134 through the solder pads 182 and possibly additional solder balls formed on the solder pads 182 . Therefore, the present embodiment can simultaneously stack adjacent first external components 170 and second external components 180 with different pin layouts on the package structure 100 , thereby providing good compatibility and expandability.

FIG. 3 shows the manufacturing process of the package structure shown in FIG. 1 and FIG. 2 , please refer to FIGS. 1-3 at the same time. First, as shown in step 310 , a circuit substrate 110 is provided, wherein the circuit substrate 110 has a carrying surface 112 and a first pad 114 and a second pad 116 on the carrying surface 112 .

Next, as shown in step 320, the first solder balls 124 are respectively formed on the first solder pads 114 to serve as the first external contacts, and the second solder balls 134 are respectively formed on the second solder pads 116 to serve as the second contact points. external contact point.

Then, as shown in step 330, the first chip 122 and the second chip 132 are adjacently disposed on the carrying surface 112, and wire bonding or other possible bonding techniques are used to bond the first chip 122 and the second chip 132 to the circuit substrate 110. The first pad 114 is located on the periphery of the first chip 122 and is electrically connected to the first chip 122 , while the second pad 116 is located on the periphery of the second chip 132 and is electrically connected to the second chip 132 .

In this embodiment, although step 320 is performed first and then step 330 is performed, in fact, the order of step 320 and step 330 can be interchanged.

Next, as shown in step 340 , an encapsulant 140 is formed on the carrying surface 112 to cover the first chip 122 and the second chip 132 . After that, as shown in step 350 , a first opening 142 and a plurality of second openings 144 are formed in the encapsulant 140 . The first openings 142 respectively expose the first solder balls 124 , and the second openings 144 respectively expose the second solder balls 134 . The method used in this embodiment to form the first opening 142 and the second opening 144 is, for example, laser burning or other possible methods such as chemical etching or plasma etching.

In addition, in this embodiment, as shown in step 360 , the first external component 170 is disposed above the first chip 122 , and the first external component 170 is bonded to the first solder ball 124 . In addition, the second external component 180 is disposed above the second chip 132 and bonded to the second solder ball 134 to obtain the package-on-package structure as shown in FIG. 2 .

It is worth mentioning that the packaging process described in this embodiment can be fabricated by using the substrate unit obtained by cutting the array substrate. Alternatively, the uncut array substrate is used for fabrication, and the cutting process is performed after the aforementioned step 350 or step 360 is completed, so as to obtain the package structure as shown in FIG. 1 or FIG. 2 . In addition, after the aforementioned step 350 or step 360 , third solder balls 160 may also be formed on the third solder pads 119 at the bottom of the circuit substrate 110 , and steps such as reflowing the third solder balls 160 may be performed. The steps should be understood by those skilled in the art, and will not be repeated here.

FIG. 4 is a package structure of another embodiment of the present invention. As shown in FIG. 4 , the package structure 400 includes a circuit substrate 410 , a first chip module 420 , a second chip module 430 and an encapsulant 440 . In this embodiment, the first chip module 420 adopts a fan-out pin design, while the second chip module 430 adopts a fan-in pin design. In other words, the circuit substrate 410 has a carrying surface 412 and a plurality of first pads 414 located on the carrying surface 412 . There is a first pitch P1 between every two adjacent first pads 414 .

The first chip module 420 includes a first chip 422 and a plurality of first solder balls 424 , wherein the first chip 422 is disposed on the carrying surface 412 , and the first solder pads 414 are located on the periphery of the first chip 422 . The first solder ball 424 is disposed on the first solder pad 414 . In this embodiment, the first chip 422 is electrically connected to the circuit substrate 410 through a plurality of wires 452 by wire bonding, and then electrically connected to the first pad through the internal circuit (not shown) of the circuit substrate 410. 414. Of course, the first chip 422 can also be electrically connected to the circuit substrate 410 by flip-chip bonding or other possible ways. In addition, the first solder balls 424 are respectively disposed on the first solder pads 414 and also have the first pitch P1.

In addition, the second chip module 430 includes a second chip 432 and a plurality of second solder balls 434, wherein the second chip 432 is disposed on the carrying surface 412, and a top surface 432a of the second chip 432 has a plurality of second solder balls. Solder pads 436 . There is a second pitch P2 between every two adjacent second pads 436 , and the first pitch P1 is greater than the second pitch P2 . In this embodiment, the second chip 432 is electrically connected to the circuit substrate 410 through a plurality of wires 454 by wire bonding. Of course, the second chip 432 can also be electrically connected to the circuit substrate 410 by flip-chip bonding or other possible ways. In addition, the second solder balls 434 are respectively disposed on the second solder pads 436 , which also have the second pitch P2.

The encapsulant 440 is disposed on the carrying surface 412 and covers the first chip 422 and the second chip 432 . In addition, the encapsulant 440 has a plurality of first openings 442 and a plurality of second openings 444 for exposing the first solder balls 424 and the second solder balls 434 respectively.

Referring to FIG. 4 again, the circuit substrate 410 may further have a bottom surface 418 opposite to the carrying surface 412 and a plurality of third pads 419 disposed on the bottom surface 418 . A third solder ball 460 may be disposed on each third pad 419 for connecting the package structure 400 to an external circuit, such as a printed circuit board.

FIG. 5 is a stacked package structure obtained after the package structure 400 in FIG. 4 is subjected to a package on package (Package on Package, POP) process. As shown in FIG. 5 , a first external component 470 and a second external component 480 are disposed above the first chip 422 and the second chip 432 respectively. Here, the first external component 470 and the second external component 480 are, for example, chip stacked packaging units. The first external component 470 has a plurality of solder pads 472 corresponding to the first pitch P1, and is bonded to the first solder ball 424 through the solder pads 472 and possibly additional solder balls formed on the solder pads 472 . The second external component 480 has a plurality of solder pads 482 corresponding to the second pitch P2, and is bonded to the second solder ball 434 through the solder pads 482 and possibly additional solder balls formed on the solder pads 482 . Therefore, the present embodiment can simultaneously stack adjacent first external components 470 and second external components 480 with different pin layouts on the package structure 400 , thereby providing good compatibility and expandability.

FIG. 6 shows the manufacturing process of the package structure shown in FIG. 4 and FIG. 5 , please refer to FIGS. 4-6 at the same time. First, as shown in step 610 , a circuit substrate 410 is provided, wherein the circuit substrate 410 has a carrying surface 412 and a first pad 414 on the carrying surface 412 .

Next, as shown in step 620 , a first solder ball 424 is formed on the first solder pad 414 . Then, as shown in step 630, the first chip 422 and the second chip 432 are adjacently disposed on the carrying surface 412, and wire bonding or other possible bonding techniques are used to bond the first chip 422 and the second chip 432 to the circuit substrate 410. The first bonding pad 414 is located on the periphery of the first chip 422 and is electrically connected to the first chip 422 , while the top surface 432 a of the second chip 432 has a plurality of second bonding pads 436 .

In this embodiment, although step 620 is performed first and then step 630 is performed, in fact, the order of step 620 and step 630 can be interchanged.

Next, as shown in step 640 , a plurality of second solder balls 434 are respectively formed on the second solder pads 436 . Moreover, as shown in step 650 , an encapsulant 440 is formed on the carrier surface 412 to cover the first chip 422 and the second chip 432 .

After that, as shown in step 660 , a first opening 442 and a plurality of second openings 444 are formed in the encapsulant 440 . The first openings 442 respectively expose the first solder balls 424 , and the second openings 444 respectively expose the second solder balls 434 . The method used in this embodiment to form the first opening 442 and the second opening 444 is, for example, laser burning or other possible methods such as chemical etching or plasma etching.

In addition, in this embodiment, as shown in step 670 , the first external component 470 is disposed above the first chip 422 , and the first external component 470 is bonded to the first solder ball 424 . In addition, the second external component 480 is disposed above the second chip 432 and bonded to the second solder ball 434 to obtain the package-on-package structure as shown in FIG. 5 .

It is worth mentioning that the packaging process described in this embodiment can be fabricated by using the substrate unit obtained by cutting the array substrate. Alternatively, the uncut array substrate is used for fabrication, and the cutting process is performed after the aforementioned step 660 or step 670 is completed, so as to obtain the packaging structure as shown in FIG. 4 or FIG. 5 . In addition, after the aforementioned step 660 or step 670 , third solder balls 460 may also be formed on the third solder pads 419 at the bottom of the circuit substrate 410 , and steps such as reflow of the third solder balls 460 may be performed. The steps should be understood by those skilled in the art, and will not be repeated here.

Based on the content of the foregoing embodiments, in another embodiment of the present invention, the first chip module adopts a fan-in pin design, while the second chip module adopts a fan-out pin design instead. Or, viewed from another perspective, the packaging structure and packaging process of this other embodiment are similar to those shown in FIGS. 4-6 , but the more significant difference is that the first pitch P1 is smaller than the second pitch P2 .

FIG. 7 is a package structure according to another embodiment of the present invention. As shown in FIG. 7 , the package structure 700 includes a circuit substrate 710 , a first chip module 720 , a second chip module 730 and an encapsulant 740 . Both the first chip module 720 and the second chip module 730 in this embodiment adopt a fan-in pin design.

The first chip module 720 includes a first chip 722 and a plurality of first solder balls 724, wherein the first chip 722 is disposed on the carrying surface 712, and a top surface 722a of the first chip 722 has a plurality of first solder pads 726. There is a first pitch P1 between every two adjacent first pads 726 . In this embodiment, the first chip 722 is electrically connected to the circuit substrate 710 through a plurality of wires 752 by wire bonding. Of course, the first chip 722 can also be electrically connected to the circuit substrate 710 by flip-chip bonding or other possible ways. In addition, the first solder balls 724 are respectively disposed on the first solder pads 726 , which also have the first pitch P1 .

In addition, the second chip module 730 includes a second chip 732 and a plurality of second solder balls 734, wherein the second chip 732 is disposed on the carrying surface 712, and a top surface 732a of the second chip 732 has a plurality of second solder balls. Solder pad 736. There is a second pitch P2 between every two adjacent second pads 736 , and the first pitch P1 is greater than the second pitch P2 . In this embodiment, the second chip 732 is electrically connected to the circuit substrate 710 through a plurality of wires 754 by wire bonding. Of course, the second chip 732 can also be electrically connected to the circuit substrate 710 by flip-chip bonding or other possible ways. In addition, the second solder balls 734 are respectively disposed on the second solder pads 736 , which also have the second pitch P2.

The encapsulant 740 is disposed on the carrying surface 712 and covers the first chip 722 and the second chip 732 . In addition, the encapsulant 740 has a plurality of first openings 742 and a plurality of second openings 744 for exposing the first solder balls 724 and the second solder balls 734 respectively.

Referring to FIG. 7 again, the circuit substrate 710 may further have a bottom surface 718 opposite to the carrying surface 712 and a plurality of third pads 719 disposed on the bottom surface 718 . A third solder ball 760 may be disposed on each third pad 719 for connecting the package structure 700 to an external circuit, such as a printed circuit board.

FIG. 8 is a package-on-package structure obtained after the package-on-package process 700 in FIG. 7 is performed. As shown in FIG. 8 , a first external element 770 and a second external element 780 are disposed above the first chip 722 and the second chip 732 respectively. Here, the first external component 770 and the second external component 780 are, for example, chip stacking type package units respectively. The first external component 770 has a pin layout corresponding to the first pitch P1, and is bonded to the first solder ball 724 through a plurality of solder pads 772 . The second external component 780 has a pin layout corresponding to the second pitch P2, and is bonded to the second solder ball 734 through a plurality of solder pads 782 . Therefore, the present embodiment can simultaneously stack adjacent first external components 770 and second external components 780 with different pin layouts on the package structure 700 , thereby providing good compatibility and expandability.

FIG. 9 shows the manufacturing process of the package structure shown in FIG. 7 and FIG. 8 , please refer to FIGS. 7-9 at the same time. First, as shown in step 910 , a circuit substrate 710 is provided, wherein the circuit substrate 710 has a carrying surface 712 .

Next, as shown in step 920, the first chip 722 and the second chip 732 are adjacently arranged on the carrying surface 712, and wire bonding or other possible bonding techniques are used to bond the first chip 722 and the second chip 732 to the circuit substrate 710. The top surface 722 a of the first chip 722 has a plurality of first bonding pads 726 , and the top surface 732 a of the second chip 732 has a plurality of second bonding pads 736 .

Then, as shown in step 930 , a plurality of first solder balls 724 are respectively formed on the first solder pads 726 , and a plurality of second solder balls 734 are respectively formed on the second solder pads 736 . Moreover, as shown in step 940 , an encapsulant 740 is formed on the carrier surface 712 to cover the first chip 722 and the second chip 732 .

Afterwards, as shown in step 950 , a first opening 742 and a plurality of second openings 744 are formed in the encapsulant 740 . The first openings 742 respectively expose the first solder balls 724 , and the second openings 744 respectively expose the second solder balls 734 . The method used in this embodiment to form the first opening 742 and the second opening 744 is, for example, laser burning or other possible methods such as chemical etching or plasma etching.

In addition, in this embodiment, as shown in step 960 , the first external component 770 is disposed above the first chip 722 , and the first external component 770 is bonded to the first solder ball 724 . In addition, a second external component 780 is disposed above the second chip 732 and bonded to the second solder ball 734 to obtain a package-on-package structure as shown in FIG. 8 .

It is worth mentioning that the packaging process described in this embodiment can be fabricated by using the substrate unit obtained by cutting the array substrate. Alternatively, the uncut array substrate is used for fabrication, and the cutting process is performed after the aforementioned step 950 or step 960 is completed, so as to obtain the package structure as shown in FIG. 7 or FIG. 8 . In addition, after the aforementioned step 950 or step 960 , third solder balls 760 may also be formed on the third solder pads 719 at the bottom of the circuit substrate 710 , and steps such as reflow of the third solder balls 760 may be performed. The steps should be understood by those skilled in the art, and will not be repeated here.

Although the above-mentioned embodiments are described by taking chip modules integrating two different pin layouts as an example, the present invention does not limit the number of types of chip modules that can be integrated in the package structure, which may vary with the actual vary according to design requirements.

In summary, the packaging structure and packaging process of the present invention integrate a plurality of chip modules with different pin layouts (that is, different contact pitches), and the chip modules are arranged adjacent to each other to serve as a stacked packaging process. The lower packaging unit. In other words, the packaging structure and packaging process of the present invention simultaneously realize the adjacent chip configuration and the stacked packaging technology, and have the advantages of both. In this way, the lower packaging unit can be compatible with a variety of external components with different specifications at the same time, such as memory packaging units with different specifications. Therefore, the packaging structure and packaging process proposed by the present invention have good compatibility and scalability.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that: it still Modifications or equivalent replacements can be made to the technical solutions of the present invention, and these modifications or equivalent replacements cannot make the modified technical solutions deviate from the spirit and scope of the technical solutions of the present invention.

Claims (9)

1. encapsulating structure comprises:

One circuit base plate has a load-bearing surface;

One first wafer module is disposed on this load-bearing surface, and this first wafer module has a plurality of first external contact, and has one first spacing between the per two adjacent first external contacts, and wherein this first wafer module comprises:

One first wafer is disposed on this load-bearing surface, and this circuit base plate has a plurality of first weld pads and is disposed on this load-bearing surface of this first wafer periphery, and this first wafer is electrically connected to described first weld pad; And

A plurality of first soldered balls are disposed at respectively on described first weld pad, with as the described first external contact;

One second wafer module, this first wafer module and this second wafer module are adjacent to be disposed on this load-bearing surface, this second wafer module has a plurality of second external contact, and has one second spacing between the per two adjacent second external contacts, and wherein this second wafer module comprises:

One second wafer is disposed on this load-bearing surface, and this circuit base plate has a plurality of second weld pads and is disposed on this load-bearing surface of this second wafer periphery, and this second wafer is electrically connected to described second weld pad; And,

A plurality of second soldered balls are disposed at respectively on described second weld pad, and with as the described second external contact, wherein this first spacing is greater than this second spacing; And,

One packing colloid, be disposed on this load-bearing surface, this packing colloid covers this first wafer module and this second wafer module, and this packing colloid has a plurality of first perforates and a plurality of second perforate, described first perforate exposes the described first external contact respectively, and described second perforate exposes the described second external contact respectively.

2. encapsulating structure comprises:

One circuit base plate has a load-bearing surface;

One first wafer module is disposed on this load-bearing surface, and this first wafer module has a plurality of first external contact, and has one first spacing between the per two adjacent first external contacts, and wherein this first wafer module comprises:

One first wafer is disposed on this load-bearing surface, and this circuit base plate has a plurality of first weld pads and is disposed on this load-bearing surface of this first wafer periphery, and this first wafer is electrically connected to described first weld pad; And

A plurality of first soldered balls are disposed at respectively on described first weld pad, with as the described first external contact;

One second wafer module, this first wafer module and this second wafer module are adjacent to be disposed on this load-bearing surface, this second wafer module has a plurality of second external contact, and has one second spacing between the per two adjacent second external contacts, and wherein this second wafer module comprises:

One second wafer is disposed on this load-bearing surface, and an end face of this second wafer has a plurality of second weld pads; And,

A plurality of second soldered balls are disposed at respectively on described second weld pad, and with as the described second external contact, wherein this first spacing is greater than this second spacing; And,

One packing colloid, be disposed on this load-bearing surface, this packing colloid covers this first wafer module and this second wafer module, and this packing colloid has a plurality of first perforates and a plurality of second perforate, described first perforate exposes the described first external contact respectively, and described second perforate exposes the described second external contact respectively.

3. encapsulating structure comprises:

One circuit base plate has a load-bearing surface;

One first wafer module is disposed on this load-bearing surface, and this first wafer module has a plurality of first external contact, and has one first spacing between the per two adjacent first external contacts, and wherein this first wafer module comprises:

One first wafer is disposed on this load-bearing surface, and an end face of this first wafer has a plurality of first weld pads; And,

A plurality of first soldered balls are disposed at respectively on described first weld pad, with as the described first external contact;

One second wafer module, this first wafer module and this second wafer module are adjacent to be disposed on this load-bearing surface, this second wafer module has a plurality of second external contact, and has one second spacing between the per two adjacent second external contacts, and wherein this second wafer module comprises:

One second wafer is disposed on this load-bearing surface, and this circuit base plate has a plurality of second weld pads and is disposed on this load-bearing surface of this second wafer periphery, and this second wafer is electrically connected to described second weld pad; And,

A plurality of second soldered balls are disposed at respectively on described second weld pad, and with as the described second external contact, wherein this first spacing is greater than this second spacing; And,

One packing colloid, be disposed on this load-bearing surface, this packing colloid covers this first wafer module and this second wafer module, and this packing colloid has a plurality of first perforates and a plurality of second perforate, described first perforate exposes the described first external contact respectively, and described second perforate exposes the described second external contact respectively.

4. encapsulating structure comprises:

One circuit base plate has a load-bearing surface;

One first wafer module is disposed on this load-bearing surface, and this first wafer module has a plurality of first external contact, and has one first spacing between the per two adjacent first external contacts, and wherein this first wafer module comprises:

One first wafer is disposed on this load-bearing surface, and an end face of this first wafer has a plurality of first weld pads; And,

A plurality of first soldered balls are disposed at respectively on described first weld pad, with as the described first external contact;

One second wafer module, this first wafer module and this second wafer module are adjacent to be disposed on this load-bearing surface, this second wafer module has a plurality of second external contact, and has one second spacing between the per two adjacent second external contacts, and wherein this second wafer module comprises:

One second wafer is disposed on this load-bearing surface, and an end face of this second wafer has a plurality of second weld pads; And,

A plurality of second soldered balls are disposed at respectively on described second weld pad, and with as the described second external contact, wherein this first spacing is greater than this second spacing; And,

One packing colloid, be disposed on this load-bearing surface, this packing colloid covers this first wafer module and this second wafer module, and this packing colloid has a plurality of first perforates and a plurality of second perforate, described first perforate exposes the described first external contact respectively, and described second perforate exposes the described second external contact respectively.

5. according to claim 1,2,3 or 4 described encapsulating structures, also comprise one first outer member, be disposed at this first wafer top and be engaged to the described first external contact.

6. encapsulation procedure comprises:

One circuit base plate is provided, and this circuit base plate has a load-bearing surface;

Be adjacent to dispose one first wafer module and one second wafer module on this load-bearing surface, this first wafer module has a plurality of first external contact, and has one first spacing between the per two adjacent first external contacts, and this second wafer module has a plurality of second external contact, and has one second spacing between the per two adjacent second external contacts, wherein this first spacing is not equal to this second spacing, this circuit base plate has a plurality of first weld pads and a plurality of second weld pad that is positioned on this load-bearing surface, and the method that is adjacent to dispose this first wafer module and this second wafer module comprises:

Form a plurality of first soldered balls at described first weld pad respectively, with as the described first external contact, and respectively at a plurality of second soldered balls of described second weld pad formation, with as the described second external contact; And,

Be adjacent to dispose one first wafer and one second wafer on this load-bearing surface, and engage this first wafer and this second wafer to this circuit base plate, described first weld pad is positioned on this load-bearing surface of this first wafer periphery and is electrically connected to this first wafer, and described second weld pad is positioned on this load-bearing surface of this second wafer periphery and is electrically connected to this second wafer;

Form a packing colloid on this load-bearing surface, to cover this first wafer module and this second wafer module; And,

Form a plurality of first perforates and a plurality of second perforate in this packing colloid, described first perforate exposes the described first external contact respectively, and described second perforate exposes the described second external contact respectively.

7. encapsulation procedure comprises:

One circuit base plate is provided, and this circuit base plate has a load-bearing surface;

Be adjacent to dispose one first wafer module and one second wafer module on this load-bearing surface, this first wafer module has a plurality of first external contact, and has one first spacing between the per two adjacent first external contacts, and this second wafer module has a plurality of second external contact, and has one second spacing between the per two adjacent second external contacts, wherein this first spacing is not equal to this second spacing, wherein this circuit base plate has a plurality of first weld pads that are positioned on this load-bearing surface, and the method that is adjacent to dispose this first wafer module and this second wafer module comprises:

Form a plurality of first soldered balls at described first weld pad respectively, with as the described first external contact;

Be adjacent to dispose one first wafer and one second wafer on this load-bearing surface, and engage this first wafer and this second wafer to this circuit base plate, described first weld pad is positioned on this load-bearing surface of this first wafer periphery and is electrically connected to this first wafer, and an end face of this second wafer has a plurality of second weld pads; And,

Form a plurality of second soldered balls at described second weld pad respectively, with as the described second external contact;

Form a packing colloid on this load-bearing surface, to cover this first wafer module and this second wafer module; And,

Form a plurality of first perforates and a plurality of second perforate in this packing colloid, described first perforate exposes the described first external contact respectively, and described second perforate exposes the described second external contact respectively.

8. encapsulation procedure comprises:

One circuit base plate is provided, and this circuit base plate has a load-bearing surface;

Be adjacent to dispose one first wafer module and one second wafer module on this load-bearing surface, this first wafer module has a plurality of first external contact, and has one first spacing between the per two adjacent first external contacts, and this second wafer module has a plurality of second external contact, and has one second spacing between the per two adjacent second external contacts, wherein this first spacing is not equal to this second spacing, and the method that wherein is adjacent to dispose this first wafer module and this second wafer module comprises:

Be adjacent to dispose one first wafer and one second wafer on this load-bearing surface, and engage this first wafer and this second wafer to this circuit base plate, one end face of this first wafer has a plurality of first weld pads, and an end face of this second wafer has a plurality of second weld pads;

Form a plurality of first soldered balls at described first weld pad respectively, with as the described first external contact; And,

Form a plurality of second soldered balls at described second weld pad respectively, with as the described second external contact;

Form a packing colloid on this load-bearing surface, to cover this first wafer module and this second wafer module; And,

Form a plurality of first perforates and a plurality of second perforate in this packing colloid, described first perforate exposes the described first external contact respectively, and described second perforate exposes the described second external contact respectively.

9. according to claim 6,7 or 8 described encapsulation procedures, wherein form a plurality of first perforates and the method for a plurality of second perforates in this packing colloid comprises the laser hole burning.

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