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CN102034779B - 具有坚固的拐角凸块的芯片设计 - Google Patents

具有坚固的拐角凸块的芯片设计 Download PDF

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Publication number
CN102034779B
CN102034779B CN2010105006769A CN201010500676A CN102034779B CN 102034779 B CN102034779 B CN 102034779B CN 2010105006769 A CN2010105006769 A CN 2010105006769A CN 201010500676 A CN201010500676 A CN 201010500676A CN 102034779 B CN102034779 B CN 102034779B
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pad
projection
substrate
stress
integrated circuit
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CN102034779A (zh
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陈宪伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种集成电路结构包括半导体芯片，该半导体芯片包括拐角、边缘、和中心。该半导体芯片进一步包括：分布在基板的主表面上的多个凸块焊盘结构；基板的第一区域，在其上形成有第一凸块焊盘结构，该第一凸块焊盘结构具有与其相连的第一数量的支撑金属焊盘；以及基板的第二区域，在其上形成有第二凸块结构，该第二凸块结构具有与其相关的第二数量的支撑金属焊盘，该第二数量大于该第一数量。

Description

具有坚固的拐角凸块的芯片设计
本申请要求于2009年10月8日提交的美国临时申请第61/249,902号名称为“Chip Design with Robust Corner Bumps”的优先权，该申请被结合于此作为参考。
技术领域
本公开总体来说涉及集成电路、更具体地来说，涉及集成电路的凸块焊盘结构的结构和形成方法。
背景技术
集成电路(IC)芯片通常与封装组件中的封装基板电连接，以提供外部信号交换。一般使用的接合方案是倒装芯片接合。图1示意性地示出了倒装芯片接合结构，其中IC芯片100通过凸块植球104接合到封装基板102上。然而，一般会发现，IC芯片100的热膨胀系数(CTE)与封装基板102的热膨胀系数明显不同。例如，IC芯片100的CTE可以是大约3ppm/℃，而封装基板102的CTE可以是大约15ppm/℃。由于CTE的差异，IC芯片100和封装基板102内部会产生应力，这样会带来翘曲，如图2示意性地示出。
翘曲会导致在IC芯片100中凸块植球104破裂以及低k介电层(未示出)分层。目前，在金属间介电(IMD)层中，许多处理使用低k和超低k介电材料，以减小RC延迟和寄生电容。IMD设计的总体趋势是IMD层的介电常数(k)趋向于从低k态降低到超低k态。这意味着其中形成金属线和通孔的IMD层在机械性质上更加脆弱。而且，在热膨胀导致的应力下，IMD层会分层。该凸块破裂和分层在IC芯片100的拐角处会特别严重。虽然凸块破裂和分层仍会发生，但是传统的底部填充被用于填充IC芯片100和凸块植球104之间的空间，以保护凸块植球104。
发明内容
根据实施例的一个方面，集成电路结构包括：多个凸块焊盘结构，分布在基板的主表面上；基板的第一区域，在其上形成有第一凸块焊盘结构，其具有与其相关的第一数量的支撑金属焊盘；以及基板的第二区域，在其上形成有第二凸块焊盘结构，其具有与其相关的第二数量的支撑金属焊盘，第二数量大于第一数量。
根据本发明的集成电路，其中，所述第二区域是所述基板的边缘区域，并且其中，所述第一区域是所述基板的中心区域。
根据本发明的集成电路，进一步包括：
所述基板的第三区域，在其上形成有第三凸块焊盘结构，所述第三凸块焊盘结构具有与其相关的第三数量的支撑金属焊盘，所述第三数量大于所述第二数量。
根据本发明的集成电路，其中，所述第三区域是拐角区域。
根据本发明的集成电路，其中，所述基板承受应力，并且其中，所述第二区域比所述第一区域受到更大的应力。
根据本发明的集成电路，其中，多个凸块焊盘结构形成在所述基板上，并且按逻辑地分为多行，至少一个最接近所述基板的拐角的行具有形成在其中的至少一个第三凸块焊盘结构，至少一个最接近所述基板的边缘的行具有形成在其中的至少一个第二凸块焊盘结构，并且至少一个远离所述基板的所述拐角和所述边缘的行具有形成在其中的至少一个凸块焊盘结构。
根据本发明的集成电路，其中，所述支撑金属焊盘的第一数量是1，所述支撑金属焊盘的第二数量是2，并且所述支撑金属焊盘的第三数量是3。
根据本发明实施例的一种集成电路，包括：
拐角；
边缘；
中心；
第一凸块焊盘结构，相比于其他凸块焊盘结构最接近所述拐角，并且具有第一焊盘结构；
第二凸块焊盘结构，相比于其他凸块焊盘结构最接近所述边缘，并且具有与所述第一焊盘结构不同的第二焊盘结构；以及
第三凸块焊盘结构，相比于其他凸块焊盘结构最接近所述中心，并且具有与所述第一焊盘结构和第二焊盘结构不同的第三焊盘结构。
根据本发明的集成电路，其中，所述第一凸块焊盘结构是单固体焊盘结构，所述第二凸块焊盘结构是双固体焊盘结构，并且所述第三凸块焊盘结构是三固体焊盘结构。
根据本发明的集成电路，其中，所述凸块焊盘结构在集成电路上分成行并且包括：
第一行凸块焊盘结构，邻近所述拐角，并且包括三固体焊盘结构；以及
第二行凸块焊盘结构，邻近所述第一行凸块焊盘结构，并且包括双固体焊盘结构。
根据本发明的集成电路，其中，所述凸块焊盘结构在集成电路上分成行并且包括：
第一行凸块焊盘结构，邻近所述拐角，并且包括双固体焊盘结构；以及
第二行凸块焊盘结构，邻近所述第一行凸块焊盘结构，并且包括单固体焊盘结构。
根据本发明的集成电路，进一步包括焊锡凸块焊料凸块，形成在所述第一凸块焊盘结构顶上并且与所述第一凸块焊盘结构电连接。
根据本发明实施例一种集成电路，包括：
基板，具有承受第一应力的第一区域和承受更大的第二应力的第二区域；
形成在所述基板上的多个凸块焊盘，所述多个凸块焊盘包括：
第一凸块焊盘，具有形成在所述第一区域中的第一应力改善结构；以及
第二凸块焊盘，具有形成在所述第二区域中的与所述第一应力改善结构不同的第二应力改善结构。
根据本发明的集成电路，其中，所述基板进一步包括第三区域，所述第三区域比所述第二区域承受更大的应力，并且其中所述多个凸块焊盘进一步包括：
第三凸块焊盘，具有形成在所述第三区域中的不同于所述第一应力改善结构和所述第二应力改善结构的第三应力改善结构。
根据本发明的集成电路，其中：
所述第三区域是所述基板的拐角；
所述第二区域是所述基板的边缘；以及
所述第一区域远离所述基板的所述拐角和所述边缘。
根据本发明的集成电路，其中：
所述第一应力改善结构是单固体焊盘；以及
所述第二应力改善结构是双固体焊盘。
根据本发明的集成电路，其中，多个凸块焊盘按行排列，并且其中：
最接近所述基板的拐角的行中的凸块焊盘包括所述第三应力改善结构；
最接近所述基板的边缘的行中的凸块焊盘包括所述第二应力改善结构；以及
远离所述基板的所述拐角和所述边缘的行中的凸块焊盘包括所述第一应力改善结构。
根据本发明的集成电路，其中，所述基板的表面积在100mm2至225mm2之间。
根据本发明的集成电路，具有在最接近所述基板的拐角的行中的至少三个凸块焊盘。
根据本发明的集成电路，进一步包括形成在所述第一凸块焊盘顶上的焊料凸块。
附图说明
为了更好地理解本披露及其优点，现在将结合附图进行的以下描述作为参考，其中：
图1和图2示出了传统倒装封装组件的横截面图；
图3A、图3B、和图3C分别是单固体焊盘结构、双固体焊盘结构、和三固体焊盘结构的横截面图。
图4示出了图3A、图3B和/或图3C中所示结构的顶视图；
图5示出了仿真结果，其中不同凸块焊盘结构的节点释放能量与各自支撑金属焊盘的数量有关。
图6示出了根据实施例的具有凸块焊盘结构的芯片的顶视图。
图7和图8示出了芯片的拐角部分和凸块焊盘结构的拐角-行(corner-row)；以及
图9和图10示出了根据可选实施例的芯片的顶视图，其中，示出了凸块焊盘结构的边缘-行(side-row)。
具体实施方式
以下详细描述本发明实施例的制造和使用。然而，应该想到，实施例提供可以在多种特定环境中具体化的多种可应用发明思想。
一种半导体芯片可以包括多个焊料凸块，该焊料凸块被用于将半导体芯片中的集成电路与外部电路电连接。根据一个实施例，图3A、图3B和图3C示出了示例性凸块焊盘结构，在该凸块焊盘结构上形成凸块42。贯穿说明书，术语“凸块焊盘结构”指的是以下结构：包括UBM40、金属焊盘38、底部焊盘(underlying pad)56和60(以及附加支撑焊盘，如果有，则请参考图3A到3C)，以及连接通孔。
图3A示出了包括基板30的芯片20的一部分，在基板30上形成有源电路32。基板30可以是常用半导体材料(诸如硅、硅锗等等)形成的半导体基板。有源电路32可以包括互补金属氧化物半导体(CMOS)晶体管、电阻器、电容器等等。互连结构33形成在有源电路32之上并且用于与有源电路32的部分进行互连，并且将有源电路32与凸块42相连接。互连结构33包括多个金属化层，金属化层包括多个介电层中的金属线和通孔(未示出)。互连结构33中的介电层可以是低k介电层。
钝化层34和36形成在互连结构33之上。钝化层34和36在本领域通常分别称为钝化-1和钝化-2，并且可以由诸如氧化硅、氮化硅、未掺杂硅酸盐玻璃(USG)、聚酰亚胺、和/或其多层的材料形成。金属焊盘38的底部可以处于钝化层34中。而且，金属焊盘38的顶部可以与钝化层36的底部处于同一水平线上，并且直接位于钝化层36的上部中的开口之下。金属焊盘38可以包含铝，并且因此还可以称为铝焊盘38，但是该金属焊盘38也可以由其他材料形成或者包括其他材料，诸如铜、银、金、镍、钨、其合金、和/或其多层。在一个实施例中，金属焊盘38由Al-Cu形成。金属焊盘38可以与有源电路32电连接，例如，通过底部互连结构33。
在钝化层36中形成开口。凸块下金属层(UBM)40填充该开口并且与金属焊盘38接触。在一个实施例中，UBM 40由复合层形成，该复合层包括钛层、铜层、镍层、或者其结合。在其他实施例中，UBM 40可以包括其他金属，诸如金。UBM 40可以包括钝化层36中的一部分和钝化层36之上的一部分。
凸块42形成在UBM 40之上并且与其电连接，并且可能与UBM 40相接触。凸块42可以由共晶焊料、无铅焊料、铜、含铜合金等形成。在一个实施例中，凸块42由焊锡材料形成，在凸块42上执行回流步骤，这样凸块42具有球状上部，其下部的尺寸和形状分别由UBM 40的尺寸和形状限定。
互连结构33中的金属化层包括顶部金属化层Mtop，该顶部金属化层Mtop包括顶部介电层53、以及顶部介电层53中的Mtop焊盘52。顶部介电层53可以由未掺杂硅酸盐玻璃或者低k介电材料形成。Mtop 52可以如图3A所示直接与金属焊盘38接触，或者可以通过多个通孔(未示出，与图3B中的通孔54相似)与金属焊盘38相连接，该通孔与金属焊盘38和Mtop焊盘52相接触。由于只有一个金属焊盘(Mtop焊盘52)直接处于金属焊盘38之下，图3A中所示的凸块焊盘结构被称为单固体焊盘结构。贯穿说明书，直接处于金属焊盘38之下并与金属焊盘38连接或者直接或通过多个通孔与其电连接的金属焊盘被称为支撑金属焊盘。因此，金属焊盘52、56和60(图3B和图3C)都是支撑金属焊盘。可以认识到，当力被施加到金属焊盘38上时，力会作用到Mtop层52和下部支撑金属焊盘(如果有的话)，并且因此会降低凸块破裂和低k介电层的分层的可能性。在图
3A中，没有附加支撑金属焊盘直接处于Mtop焊盘52之下。
图3B示出了双固体焊盘结构。除了具有直接处于Mtop焊盘52之下的附加Mtop-1焊盘56之外，图3B所示的结构与图3A所示的结构相似。Mtop-1焊盘56形成在金属化层Mtop-1中，其直接处于顶部金属化层Mtop之下。Mtop-1焊盘56和Mtop焊盘52通过多个通孔54相连接。Mtop-1焊盘56和Mtop焊盘52大部分可以相互重叠。在一个实施例中，如图4所示，Mtop-1焊盘56和Mtop焊盘52可以具有相同的尺寸和相同的形状，并且可以(也可以不)相互完全重叠。可以认识到，当力被施加到金属焊盘38上时，力会通过Mtop-1焊盘52被施加到Mtop-1焊盘56上，并且因此Mtop-1焊盘56还在结构上支撑金属焊盘38。没有附加支撑金属焊盘直接处于金属焊盘56之下。
图3C示出了三固体焊盘结构。除了具有直接处于Mtop-1焊盘56之下的附加Mtop-2焊盘60之外，图3C所示的结构与图3B中所示的结构相似。Mtop-2焊盘60形成在金属化层Mtop-2中，该金属化层Mtop-2直接处于金属化层Mtop-1之下。Mtop-1焊盘56和Mtop-2焊盘60通过多个通孔58相连接。同样如图4所示，Mtop-1焊盘56、Mtop焊盘52和Mtop-2焊盘60大部分可以相互重叠。在一个实施例中，金属焊盘52、56和60具有相同的尺寸和相同的形状，并且可以(或可以不)相互完全重叠。没有附加支撑金属焊盘直接处于金属焊盘60之下并且通过通孔与Mtop-2焊盘60相连接。
图4示出了图3A所示结构的顶视图，其中，图3A、3B和/或3C的横截面图沿着图4中穿过线3A/3B/3C-3A/3B/3C的平面。
在可选实施例中，一个、两个、或者甚至三个附加支撑金属焊盘可以直接形成在Mtop-2焊盘60之下，并且通过通孔在结构上与Mtop-2焊盘60相接合。本领域普通技术人员通过应用上述段落中所提供的教导将实现其各自的结构。
进行仿真以研究如图3A、图3B和图3C所示的凸块焊盘结构的节点释放能量(NREs)。凸块焊盘的NRE等于施加在部件(feature)上的力乘以凸块焊盘结构的位移。NRE较大表示凸块焊盘结构的位移较大，并且因此出现分层和凸块破裂的可能性会比较大。仿真结果如图5所示，其中，Y轴表示NRE，X轴表示凸块结构的类型。注释“只有铝焊盘”表示在金属焊盘38之下不具有Mtop焊盘52的结构，而注释“单固体焊盘”和“双固体焊盘”分别表示图3A和图3B中示出的结构。该仿真结果显示出，当支撑金属焊盘的数量增加时，各自凸块焊盘结构的NRE减小，这意味着各自半导体芯片会产生较少的开裂和分层，并且因此更加可靠。应该注意，如果支撑金属焊盘的数量进一步增加，则可能施加到金属焊盘38和低k介电层的应力较好地分布，并且各自的半导体芯片20将会更加可靠。
图6示出了芯片20的顶视图，其中示出了多个凸块焊盘结构。该凸块焊盘结构被示为小空心圆，并且示出为凸块焊盘200-1、200-2和200-3(还参考图7到图10)。凸块焊盘结构200-1是单固体焊盘结构并且与图3A中所示的结构相对应。凸块焊盘200-2是双固体焊盘结构并且与图3B中所示的结构相对应。凸块焊盘200-3是三固体焊盘结构并且与图3C中所示的结构相对应。芯片20包括四个拐角202和四条边缘204。芯片20的中心被表示为中心206。在拐角到中心方向(通过箭头208表示)上，施加在凸块焊盘结构200上的应力减小。而且，在边缘到中心方向(通过箭头210表示)上，施加在凸块焊盘结构200上的应力也减小。因此，为了改进芯片20的可靠性，具有较多数量的支撑金属焊盘的凸块焊盘结构可以用在受到更大应力的位置(诸如拐角)，而具有较少数量的支撑金属焊盘的凸块焊盘结构可以用在受到较小应力的位置(诸如芯片20的中心)。附加支撑金属焊盘具有改善应力的功能，例如，将应力分布到更多层和更多部件，使得多余应力施加在金属焊盘38上的可能性降低。可以想到，随着增加支撑金属焊盘的方法被公开，其他应力改善结构也包括在本公开的预期范围内。
图7示出芯片20的拐角部分。在一个实施例中，在拐角到中心方向208上，凸块焊盘结构200分为拐角-行，接近各个拐角202的拐角-行具有较多数量的支撑金属焊盘，而远离各个拐角202的拐角-行具有较少数量的支撑金属焊盘。在一个示例性实施例中，只有第一拐角-行(仅具有一个凸块焊盘结构200-3)具有三固体焊盘结构。第二拐角-行(具有两个凸块焊盘结构200-2)具有双固体焊盘结构。第三拐角-行(具有三个凸块焊盘结构200-1)具有单固体焊盘结构。请注意，以“200-1/200-2”表示的凸块焊盘结构可以是单固体焊盘结构或者双固体焊盘结构，这是由于事实上它们在以下段落的叙述中处在第一边缘-行中。所有其他接近芯片20(参考图6)的中心206的拐角-行都可以具有单固体焊盘结构。还应当了解，从芯片20的拐角202到中心206(参考图6)，三固体焊盘结构的拐角-行的期望数量和/或双固体焊盘结构的拐角-行的数量可以大于1。例如，在图8中，有存在三固体焊盘结构200-3的两个拐角-行。然而，仍期望接近中心206的拐角-行中的凸块焊盘结构不会比远离中心206的拐角-行中的凸块焊盘结构具有更多的支撑金属焊盘。
返回参考图6，注意到，施加到接近芯片20的边缘204的凸块焊盘结构200的应力在施加到接近拐角202的凸块焊盘结构200的应力和施加到接近中心206的凸块焊盘结构200的应力之间。因此，在边缘到中心方向上，将凸块焊盘结构200划分为平行于各个边缘204的边缘-行，接近各个边缘204的边缘-行具有较多数量的支撑金属焊盘，而远离各个边204的边缘-行具有较小数量的支撑金属焊盘。在一个示例性实施例中，只有第一边缘-行具有双固体焊盘结构。比第一边缘-行更接近芯片20(参考图6)的中心206的所有其他行都可以具有单固体焊盘结构。在可选实施例中，具有双固体焊盘结构的边缘-行数量可以大于1，这取决于应力的大小。然而，仍期望接近中心206的边缘-行中的凸块焊盘结构不会比远离中心206的边缘-行中的凸块焊盘结构具有更多数量的支撑金属焊盘。
施加到芯片20的拐角202的应力取决于芯片20的尺寸和凸块42的材料(以及机械强度)。因此，如果芯片20比较小，则可以使用较少的三固体焊盘结构。实验结果显示出，如果芯片20的面积小于大约100mm2，则每个拐角202处就只需要一个三固体焊盘结构。由于三固体焊盘结构比双固体焊盘结构具有更大的面积开销(area penalty)，而双固体焊盘结构比单固体焊盘结构具有更大的面积开销，因此减小三固体焊盘结构和双固体焊盘结构的数量可以减小面积开销。然而，只能在不牺牲芯片20的可靠性的情况下实现三固体焊盘结构和双固体焊盘结构数量的减小。这样，就需要找到三固体焊盘结构的理想数量和双固体焊盘结构的理想数量。
图9和图10示出了在拐角处具有不同数量的三固体焊盘结构的示例性实施例。在图9和图10中，在每个拐角202处具有至少一个三固体焊盘结构200-3。参考图9，沿着芯片20的每条边缘存在双固体焊盘结构202-2的一个边缘-行(如虚线矩形200-2内所示)，其中拐角凸块焊盘结构200-3在整个说明书中都不认为是在边缘-行中。芯片20中的所有剩余焊盘结构都是单固体焊盘结构。图10示出了在每个拐角202处都具有三个三固体焊盘结构200-3的示例性芯片。沿着芯片20的每条边缘可以存在双固体焊盘结构200-2的一个边缘-行，并且每个拐角处都具有双固体焊盘结构200-2的一个拐角-行。芯片20中所有剩余焊盘结构都是单固体焊盘结构。如果芯片20的面积在大约100mm2和大约225mm2之间，如果凸块42是共晶凸块(图9)，每个拐角202处可以存在一个三固体焊盘结构200-3，而如果凸块42是无铅凸块(图10)，每个拐角202处可以具有三个三固体焊盘结构。如果芯片20的面积大于大约225mm2，不论凸块42是共晶凸块还是无铅凸块，每个拐角202处(图10)都可以存在三个三固体焊盘结构200-3。进一步增加芯片20的尺寸，三固体焊盘结构的期望数量和双固体焊盘结构的期望数量也会进一步增加。
这些实施例具有许多有益特征。将单固体焊盘结构、双固体焊盘结构、和三固体焊盘结构集成在同一芯片中显著地改善了半导体芯片的可靠性。然而，不存在附加处理步骤和相关制造成本。这些实施例考虑到芯片尺寸和凸块材料，从而可以以最小芯片面积消耗来实现理想效果。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本披露的精神和范围的情况下，做出各种不同的改变、替换和更改。而且，本申请的范围并不旨在限于本说明书中描述的处理、机器、制造、物质组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本披露，现有的或今后开发的用于执行与根据本披露所采用的所述相应实施例基本相同的功能或获得基本相同结果的处理、机器、制造，物质组分、装置、方法或步骤，根据本发明可以被使用。因此，所附权利要求应该包括在这样的处理、机器、制造、物质组分、装置、方法或步骤的范围内。

Claims (19)

1.一种集成电路，包括：
多个凸块焊盘结构，分布在基板的主表面上，所述基板承受应力；所述基板的承受第一应力的第一区域，在其上形成有第一凸块焊盘结构，所述第一凸块焊盘结构具有金属焊盘和与应力相关的第一数量的支撑金属焊盘，所述第一数量的支撑金属焊盘位于所述金属焊盘之下并通过通孔与所述金属焊盘接合；以及
所述基板的承受第二应力的第二区域，在其上形成有第二凸块焊盘结构，所述第二凸块焊盘结构具有金属焊盘和与应力相关的第二数量的支撑金属焊盘，所述第二数量的支撑金属焊盘位于所述金属焊盘之下并通过通孔与所述金属焊盘接合，所述第二区域比所述第一区域受到更大的应力，所述第二数量大于所述第一数量。
2.根据权利要求1所述的集成电路，其中，所述第二区域是所述基板的边缘区域，并且其中，所述第一区域是所述基板的中心区域。
3.根据权利要求1所述的集成电路，进一步包括：
所述基板的第三区域，在其上形成有第三凸块焊盘结构，所述第三凸块焊盘结构具有与应力相关的第三数量的支撑金属焊盘，所述第三数量大于所述第二数量。
4.根据权利要求3所述的集成电路，其中，所述第三区域是拐角区域。
5.根据权利要求3所述的集成电路，其中，多个凸块焊盘结构形成在所述基板上，并且按逻辑地分为多行，至少一个最接近所述基板的拐角的行具有形成在其中的至少一个第三凸块焊盘结构，至少一个最接近所述基板的边缘的行具有形成在其中的至少一个第二凸块焊盘结构，并且至少一个远离所述基板的所述拐角和所述边缘的行具有形成在其中的至少一个第一凸块焊盘结构。
6.根据权利要求3所述的集成电路，其中，所述支撑金属焊盘的第一数量是1，所述支撑金属焊盘的第二数量是2，并且所述支撑金属焊盘的第三数量是3。
7.一种集成电路，包括：
第三区域，所述第三区域是拐角；
第二区域，所述第二区域是边缘；
第一区域，所述第一区域是中心，其中所述第二区域比所述第一区域受到更大的应力，所述第三区域比所述第二区域受到更大的应力；
第一凸块焊盘结构，相比于其他凸块焊盘结构最接近所述拐角，并且具有第一焊盘结构；
第二凸块焊盘结构，相比于其他凸块焊盘结构最接近所述边缘，并且具有与所述第一焊盘结构不同的第二焊盘结构，所述第二凸块焊盘结构具有第二数量的支撑金属焊盘；以及
第三凸块焊盘结构，相比于其他凸块焊盘结构最接近所述中心，并且具有与所述第一焊盘结构和第二焊盘结构不同的第三焊盘结构，所述第三凸块焊盘结构具有第一数量的支撑金属焊盘，所述第二数量大于所述第一数量。
8.根据权利要求7所述的集成电路，其中，所述第一凸块焊盘结构是单固体焊盘结构，所述第二凸块焊盘结构是双固体焊盘结构，并且所述第三凸块焊盘结构是三固体焊盘结构。
9.根据权利要求7所述的集成电路，其中，所述凸块焊盘结构在集成电路上分成行并且包括：
第一行凸块焊盘结构，邻近所述拐角，并且包括三固体焊盘结构；以及
第二行凸块焊盘结构，邻近所述第一行凸块焊盘结构，并且包括双固体焊盘结构。
10.根据权利要求7所述的集成电路，其中，所述凸块焊盘结构在集成电路上分成行并且包括：
第一行凸块焊盘结构，邻近所述拐角，并且包括双固体焊盘结构；以及
第二行凸块焊盘结构，邻近所述第一行凸块焊盘结构，并且包括单固体焊盘结构。
11.根据权利要求7所述的集成电路，进一步包括焊锡凸块焊料凸块，形成在所述第一凸块焊盘结构顶上并且与所述第一凸块焊盘结构电连接。
12.一种集成电路，包括：
基板，具有承受第一应力的第一区域和承受更大的第二应力的第二区域；
形成在所述基板上的多个凸块焊盘，所述多个凸块焊盘包括：
第一凸块焊盘，具有形成在所述第一区域中的第一应力改善结构，所述第一应力改善结构具有第一数量的支撑金属焊盘；以及
第二凸块焊盘，具有形成在所述第二区域中的与所述第一应力改善结构不同的第二应力改善结构，所述第二应力改善结构具有第二数量的支撑金属焊盘，所述第二数量大于所述第一数量。
13.根据权利要求12所述的集成电路，其中，所述基板进一步包括第三区域，所述第三区域比所述第二区域承受更大的应力，并且其中所述多个凸块焊盘进一步包括：
第三凸块焊盘，具有形成在所述第三区域中的不同于所述第一应力改善结构和所述第二应力改善结构的第三应力改善结构。
14.根据权利要求13所述的集成电路，其中：
所述第三区域是所述基板的拐角；
所述第二区域是所述基板的边缘；以及
所述第一区域远离所述基板的所述拐角和所述边缘。
15.根据权利要求12所述的集成电路，其中：
所述第一应力改善结构是单固体焊盘；以及
所述第二应力改善结构是双固体焊盘。
16.根据权利要求13所述的集成电路，其中，多个凸块焊盘按行排列，并且其中：
最接近所述基板的拐角的行中的凸块焊盘包括所述第三应力改善结构；
最接近所述基板的边缘的行中的凸块焊盘包括所述第二应力改善结构；以及
远离所述基板的所述拐角和所述边缘的行中的凸块焊盘包括所述第一应力改善结构。
17.根据权利要求12所述的集成电路，其中，所述基板的表面积在100mm2至225mm2之间。
18.根据权利要求16所述的集成电路，具有在最接近所述基板的拐角的行中的至少三个凸块焊盘。
19.根据权利要求12所述的集成电路，进一步包括形成在所述第一凸块焊盘顶上的焊料凸块。
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