CN102034526B

CN102034526B - Method for realizing static and dynamic random access memory (SDRAM) refresh by using field programmable gate array (FPGA)

Info

Publication number: CN102034526B
Application number: CN 201010598447
Authority: CN
Inventors: 李静; 李楠宁; 白宗元; 张磊; 张英文; 纪奎
Original assignee: Dawning Information Industry Co Ltd
Current assignee: Dawning Network Technology Co ltd
Priority date: 2010-12-17
Filing date: 2010-12-17
Publication date: 2013-06-12
Anticipated expiration: 2030-12-17
Also published as: CN102034526A

Abstract

The invention provides a novel method for realizing static and dynamic random access memory (SDRAM) refresh by using field programmable gate array (FPGA). In a memory controller, N chip selections (CS) are required to be refreshed; at a preset refresh time, a refresh command is sent to gate a first chip selection CS0; before the refresh period of the CS0 ends and after the CS0 starts M periods, a refresh command is started to gate a second chip selection CS1; and in the same way, all memories are refreshed. When the technical scheme is adopted, the refresh current and refresh power consumption of SDRAM particles are reduced effectively. The method has obvious power consumption reducing effect particularly when used in a large-capacity and multi-memory system, so the method can effectively reduce the machine power consumption in the system.

Description

A kind of method that SDRAM that realizes with FPGA refreshes

Technical field

The present invention relates to Memory Controller Hub design, be specifically related to a kind of that realize with FPGA, reduce the method that SDRAM refreshes power consumption.

Background technology

Semiconductor storage unit has two kinds of dynamic RAM (DRAM) and static RAMs (SRAM).The inner form storage data that adopt bistable circuit of SRAM do not need refresh circuit can preserve the data of storage inside.The storage unit of DRAM is to be made of transistor and electric capacity, and data are stored in electric capacity, because electric capacity can leak electricity, along with passage of time, can cause the data that are stored in electric capacity destroyed, therefore need to be to being stored in the data recharge periodically in electric capacity.The DRAM that can synchronous working with cpu clock is called SDRAM.

The refreshing to be divided into automatically of SDRAM refreshed (auto refresh, AR) and two kinds of patterns of self-refresh (self refresh, SR).No matter be which kind of refreshes mode, do not need the outside that row address information is provided, row address is selected to be provided by built-in function.The data that SR is mainly used under the park mode low power consumpting state are preserved.Content of the present invention relates to the AR operation.According to the DDR2JTAG standard, approximately need to require to have refreshed 8192 all row every 64ms, the time interval that every like this row refreshes is approximately 7.8us.Stop other operations when refreshing, refresh operation has limit priority, a command signal of SDRAM response external input when refreshing, then enter auto refresh mode, the asynchronism(-nization) that the SDRAM particle refresh command that amount of capacity is different is kept, such as SDRAM time of 256Mb is 75ns, that 512Mb is 105ns, that 1Gb is 127.5ns, and that 2Gb is 197.5ns.SDRAM to refresh electric current larger, bring thus larger power consumption.In large capacity, multi-memory system, the power consumption that memory refresh brings can not look down upon, and needs to reduce the power consumption brought due to the SDRAM refresh operation in large capacity, multi-memory system for this reason as far as possible, improves running efficiency of system, less system cost.

in " selecting the dynamic RAM of the self refresh operation of execution memory bank ", No. 00102790.5 patent mentioned a kind of method that reduces the dynamic RAM power consumption, the method only refreshes for the memory bank of those storage data when refreshing, and be for all memory banks unlike traditional refreshing, like this by selecting to refresh to reduce targetedly system power dissipation, but the method is being applied to large capacity, need to increase circuit design in the time of in multi-memory system, the extra circuit power consumption that has increased again system, and this patent is the power-dissipation-reduced that carries out for self refresh operation.

The method of the reduction bank refresh power consumption of mentioning in No. 200510071912.9 patents self refresh control apparatus and the method thereof of memory bank " in the semiconductor storage based on ", the method is also by optionally refreshing when the self refresh operation, can effectively reduce self-refresh electric current and power consumption, the not mentioned huge power consumption of bringing due to automatic refresh operation that how to reduce of the method, and in large capacity, many internal memories field, also need extra circuits to keep, also brought thus extra power consumption expense.

Summary of the invention

For addressing the above problem, the present invention realizes refreshing of SDRAM with FPGA, when refresh time arrives, send refreshing instruction by FPGA to SDRAM, adopt the method reduction SDRAM particle of the stack of avoiding the peak hour to refresh the power consumption of bringing during SDRAM refreshes AR automatically, and then reduce the power consumption of large capacity, multi-memory system.

A kind of method that sdram memory particle of realizing with FPGA refreshes, step is as follows:

There is sheet to select CS to refresh in A, Memory Controller Hub;

B, when the regulation refresh time arrives, send refresh command, first sheet of gating selects CS0 to refresh;

C, when not complete in the CS0 refresh cycle, CS0 receives refreshing instruction M all after dates, FPGA sends refresh command again, second sheet of gating selects CS1;

D, refresh full memory by that analogy.

A preferred technical solution of the present invention is: the value of M is variable.

Another optimal technical scheme of the present invention is: in the different situation of internal memory model, utilize the FPGA programmable features, the refresh cycle of CSn can be adjusted at any time.

By adopting this scheme, can effectively reduce refreshing electric current and refreshing power consumption of SDRAM particle.In large capacity, multi-memory system (N 〉=4), particularly remarkable to the reduction of power consumption, can effectively reduce system's Overall Power Consumption.

Description of drawings

Fig. 1 is that the present invention refreshes schematic diagram

Embodiment

As shown in Figure 1.if there are three sheets to select CS to refresh in current Memory Controller Hub, when the refresh time of regulation arrives, as shown in the 1st clock period in figure, FPGA sends refresh command, first sheet of gating selects CS0, not complete in the CS0 refresh cycle, CS0 starts and refreshes 5 all after dates, send second refresh command, second sheet of gating selects CS1, refresh 5 all after dates at the CS1 gating equally, send the 3rd refresh command, the 3rd sheet of gating selects CS2 simultaneously, because the internal memory model is identical, under the prerequisite that satisfies in refresh cycle of CS2, the refresh cycle of CS0 and CS1 also must satisfy.Under normal circumstances, after startup CS0 refreshes, if the refresh cycle is T, must wait for after refresh cycle T finishes could starting refreshing of CS1, the like refresh these three sheets to select the time of needs be 3T, and under this refresh mode, after starting CS0 and refreshing to having refreshed CS2, altogether do not want the time (being T+10 cycle as accompanying drawing) of 2T, refresh time reduces greatly, can effectively reduce and refresh electric current and refresh the power consumption of bringing.

Claims

1. method that the sdram memory particle of realizing with FPGA refreshes, it is characterized in that: step is as follows:

Have sheet to select that in CS, memory grain need to refresh in A, Memory Controller Hub, when the regulation refresh time arrived, FPGA sent refresh command, and first sheet of gating selects CS0;

B, not complete in the CS0 refresh cycle, CS0 start M all after date, start refresh command, and second sheet of gating selects CS1;

C, refresh full memory by that analogy.

2. a kind of method that refreshes of sdram memory particle of realizing with FPGA as claimed in claim 1, it is characterized in that: the value of M is variable.

3. a kind of method that refreshes of sdram memory particle of realizing with FPGA as claimed in claim 1, it is characterized in that: in the different situation of internal memory model, utilize the FPGA programmable features, in CSn, the refresh cycle of memory grain can be adjusted at any time.