CN102426850A - Method for reducing DDR2 initialization time - Google Patents
Method for reducing DDR2 initialization time Download PDFInfo
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- CN102426850A CN102426850A CN2011104150288A CN201110415028A CN102426850A CN 102426850 A CN102426850 A CN 102426850A CN 2011104150288 A CN2011104150288 A CN 2011104150288A CN 201110415028 A CN201110415028 A CN 201110415028A CN 102426850 A CN102426850 A CN 102426850A
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Abstract
The invention provides a method for reducing DDR2 initialization time, which adopts a refreshing method of peak offset superposition. According to the method for reducing the DDR2 initialization time, the time interval between the first refresh command and the second refresh command is far smaller than T, so that the DDR2 initialization time is greatly reduced, the initialization efficiency is improved, and the power consumption is reduced.
Description
Technical field
The invention belongs to DDR2 Memory Controller Hub design field, a kind of DDR2 method of initialization time that reduces.
Background technology
In the design of general DDR2 Memory Controller Hub, be to carry out in strict accordance with the JEDEC standard to the power-up initializing of DDR2.Can find out that from accompanying drawing 1 initialization procedure must be carried out refresh operation at least 2 times, and the refresh time expense of DDR2 internal memory particle is maximum in the initialization operation of DDR2.Single refresh time expense from 75ns to 197.5ns between.Can draw thus after the initialized time of DDR2 removes the set time expense, the most of the time expense is to cause by refreshing.And DDR2 internal memory particle to refresh electric current maximum in the operation of DDR2, if it is long more to refresh elapsed time, power consumption is then big more.The present invention can solve the long problem of refresh time of the prior art, simplifies refresh process, improves initialization efficient.
Patent No. CN200910253837.6 (initial method of memory component) discloses a kind of initial method of memory component, comprises that transmitting at least N+1 clock period gives this memory component, and wherein N exports serial data figure place for this memory component.During the clock period in these clock period, transmit first the beginning and the end signal and give this memory component.During another clock period in these clock period, transmit second the beginning and the end signal and give this memory component.
Patent No. CN02131526.4 (producing the method for initializing signal in the semiconductor storage) discloses a kind of method that is used to produce initializing signal, and this initializing signal can prevent owing to apply the initial irregular operation that is installed in the internal circuit in the semiconductor storage that external power source causes.The method comprising the steps of: (a) reception is used for semiconductor storage is carried out precharge precharge instruction; (b) activate initializing signal according to the precharge instruction that is received and reach first level; (c) receiving that precharge instruction back receives the refreshing instruction that is used to refresh semiconductor storage; (d) pattern that after receiving refreshing instruction, receives the operational mode be used to be provided with semiconductor storage is provided with instruction; And (e) instruction deactivation initializing signal is set and reaches second level according to the pattern that is received.
The DDR2 power-up initializing of prior art is carried out in proper order, and time overhead has no and reduces.
Summary of the invention
The present invention overcomes the prior art deficiency, adopts a kind of method for refreshing of the stack of avoiding the peak hour.
The invention provides a kind of DDR2 of the minimizing method of initialization time, adopt the method for refreshing of the stack of avoiding the peak hour.
The DDR2 method of initialization time that reduces provided by the invention when initialization refreshes, is providing some all after dates of first refresh command, and then provides second refresh command.
The method of minimizing provided by the invention DDR2 initialization time, be the refresh cycle T of internal memory particle second refresh command effective time.
The time interval between the method for minimizing provided by the invention DDR2 initialization time, first and second refresh command is far smaller than T.
The time interval between the method for minimizing provided by the invention DDR2 initialization time, first and second refresh command is 5 clock period.
The method of minimizing provided by the invention DDR2 initialization time, in save as SDRAM.
Compared with prior art, beneficial effect of the present invention is: because the time interval between first and second refresh command is far smaller than T, significantly reduce DDR2 initialization time, improve initialization efficient, reduce power consumption.
Description of drawings
Fig. 1 is a DDR2 power-up initializing sequential schematic of the present invention;
Fig. 2 is a clock period synoptic diagram of the present invention.
Embodiment
In the design of general DDR2 Memory Controller Hub, be to carry out in strict accordance with the JEDEC standard to the power-up initializing of DDR2.Can find out that from accompanying drawing 1 initialization procedure must be carried out refresh operation at least 2 times, and the refresh time expense of DDR2 internal memory particle is maximum in the operation of DDR2.Single refresh time expense from 75ns to 197.5ns between.Can draw thus after the initialized time of DDR2 removes the set time expense, the most of the time expense is to cause by refreshing.And DDR2 internal memory particle to refresh electric current maximum in the operation of DDR2, if it is long more to refresh elapsed time, power consumption is then big more.
Adopt a kind of method for refreshing of the stack of avoiding the peak hour, under the situation that does not influence function, can effectively reduce the refresh time expense of DDR2, further reduce the initialization time of DDR2.Shown in accompanying drawing 2, the principle sketch of the stack of avoiding the peak hour is following:
When initialization refreshed, the some Later Zhou Dynasty, one of the Five Dynasties after date after providing first refresh command (being 5 cycles in the accompanying drawing) and then provided second refresh command, and be the refresh cycle T of internal memory particle second refresh command effective time.These 2 refresh time expenses are T+5tck, and if according to normal method for refreshing, then the refresh time expense should be 2T; And T＞＞5tck; Save the refresh time expense so greatly, effectively reduced DDR2 initialization time, further improved initialization efficient.
The time interval between first and second refresh command can be selected flexibly.And be not limited only to 5 clock period in the accompanying drawing 2.
Above embodiment is only in order to technical scheme of the present invention to be described but not to its restriction; Although the present invention has been carried out detailed explanation with reference to the foregoing description; The those of ordinary skill in said field is to be understood that: still can specific embodiments of the invention make amendment or replacement on an equal basis; And do not break away from any modification of spirit and scope of the invention or be equal to replacement, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (6)
1. one kind is reduced the DDR2 method of initialization time, it is characterized in that, adopts the method for refreshing of the stack of avoiding the peak hour.
2. the method for claim 1 is characterized in that, when initialization refreshes, is providing some all after dates of first refresh command, and then provides second refresh command.
3. the method for claim 1-2 is characterized in that, be the refresh cycle T of internal memory particle second refresh command effective time.
4. the method for claim 1-3 is characterized in that, the time interval between first and second refresh command is far smaller than T.
5. the method for claim 1-4 is characterized in that, the time interval between first and second refresh command is 5 clock period.
6. the method for claim 1-5 is characterized in that, in save as SDRAM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011104150288A CN102426850A (en) | 2011-12-13 | 2011-12-13 | Method for reducing DDR2 initialization time |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011104150288A CN102426850A (en) | 2011-12-13 | 2011-12-13 | Method for reducing DDR2 initialization time |
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| CN102426850A true CN102426850A (en) | 2012-04-25 |
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| CN2011104150288A Pending CN102426850A (en) | 2011-12-13 | 2011-12-13 | Method for reducing DDR2 initialization time |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6438055B1 (en) * | 1999-10-20 | 2002-08-20 | Fujitsu Limited | Dynamic memory circuit with automatic refresh function |
| CN101266833A (en) * | 2007-03-16 | 2008-09-17 | 富士通株式会社 | Semiconductor memory, operating method thereof, memory controller and system |
| CN102034526A (en) * | 2010-12-17 | 2011-04-27 | 天津曙光计算机产业有限公司 | Novel method for realizing static and dynamic random access memory (SDRAM) refresh by using field programmable gate array (FPGA) |
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2011
- 2011-12-13 CN CN2011104150288A patent/CN102426850A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6438055B1 (en) * | 1999-10-20 | 2002-08-20 | Fujitsu Limited | Dynamic memory circuit with automatic refresh function |
| CN101266833A (en) * | 2007-03-16 | 2008-09-17 | 富士通株式会社 | Semiconductor memory, operating method thereof, memory controller and system |
| CN102034526A (en) * | 2010-12-17 | 2011-04-27 | 天津曙光计算机产业有限公司 | Novel method for realizing static and dynamic random access memory (SDRAM) refresh by using field programmable gate array (FPGA) |
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Application publication date: 20120425 |