CN101989593B - Packaging substrate and its manufacturing method and packaging structure - Google Patents

Abstract

A package substrate and its manufacturing method and package structure, provide a substrate body, its at least surface has multiple electrical contact pads and circuits, form the insulating layer covered on said electrical contact pads, circuits and body surface of the substrate, and the thickness of the insulating layer is smaller than the thickness of the said electrical contact pads, and form multiple insulating layer open pores that expose every electrical contact pad correspondingly, finally, form the first metal lug on every exposed upper surface of electrical contact pad, thus can help to control the amount of welding flux easily, and then help the encapsulation of the fine pitch, and does not need to form the anti-welding layer on the substrate, make electrical contact pad and circuit keep good shape without roughening the manufacturing process, so have good qualification rate and reliability.

Description

Packaging substrate and its manufacturing method and packaging structure

technical field

The invention relates to a packaging substrate, its manufacturing method and packaging structure, in particular to a packaging substrate, packaging structure and its manufacturing method which do not need to form a solder mask layer on the substrate.

Background technique

In the current flip chip (flip chip) semiconductor packaging technology, a plurality of electrode pads are provided on the semiconductor chip, metal bumps are provided on each of the electrode pads, and a packaging substrate with a plurality of electrical contact pads is provided. , and correspondingly electrically connect the metal bump and the electrical contact pad through solder.

Compared with the traditional wire bonding (Wire Bond) technology, the flip chip technology is characterized in that the electrical connection between the semiconductor chip and the package substrate is made of metal bumps instead of ordinary gold wires, and this flip chip technology The advantage of the flip-chip technology is that it can increase the packaging density to reduce the package component size; at the same time, this kind of flip-chip technology does not need to use longer gold wires, but can improve the performance of electrical connections to reduce impedance.

As more and more product designs tend to be miniaturized, the flip-chip technology is also developing towards the trend of high output/input (I/O) count and fine pitch. However, as the pitch of the metal bumps shrinks, the reliability and yield of the packaging substrate are difficult to maintain at the original level.

Please refer to FIG. 1A to FIG. 1D , which are schematic cross-sectional views illustrating a manufacturing method of a conventional packaging structure.

As shown in FIG. 1A , a substrate body 10 is provided, at least one surface 10 a of which has a plurality of electrical contact pads 112 and circuits 111 .

As shown in FIG. 1B , a solder mask 12 is formed on the substrate body 10 , and a solder mask opening 120 is formed in the solder mask 12 to expose the electrical contact pads 112 and some circuits 111 .

As shown in FIG. 1C , solder 14 is formed on each of the electrical contact pads 112 .

As shown in FIG. 1D, a semiconductor chip 20 having an active surface 20a is placed above the substrate body 10, and the active surface 20a of the semiconductor chip 20 has a plurality of electrode pads 21, and metal bumps are provided on each of the electrode pads 21. Block 22 , making these metal bumps 22 electrically connected to each of the electrical contact pads 112 through solder 14 ′.

However, in the existing packaging structure manufacturing method, when forming the solder 14 on each of the electrical contact pads 112, it is not easy to accurately control the amount of the solder 14, which often makes the amount of the solder 14 too much (for example, the right side of FIG. 1C The solder 14) causes bridging phenomenon, or the amount of the solder 14 is too small (for example, the solder 14 on the left side of FIG. 1C ) resulting in insufficient bonding and poor electrical connection effect, which will lead to subsequent problems when the semiconductor chip 20 is packaged. Problems, such as bridging to the side (as in solder 14' on the right in FIG. 1D ) or poor connections (as in solder 14' on the left in FIG. 1D ), lead to reliability issues.

Furthermore, the metal bump 22 is arranged on the chip side, which has a higher cost, and since the solder 14 on the package substrate is only a few microns (μm) thick, the contact formed in the application of high I/O count There are often problems with poor adhesion and reliability; in addition, before forming the solder resist layer 12 on the substrate body 10, it is usually necessary to perform a roughening process to improve the bonding between the substrate body 10 and the solder resist layer 12 However, the roughening process easily causes the electrical contact pads 112 and the circuit 111 to deform, thereby affecting the overall electrical properties (especially at high frequencies), and will cause difficulties in the electrical connection of the semiconductor chip 20 .

Therefore, how to provide a packaging substrate and its manufacturing method and packaging structure, so as to avoid the difficult control of the amount of solder in the prior art, the formation of metal bumps on the chip end, and the need to form a solder mask on the substrate. To increase the bonding force with the solder mask layer by simplifying the lines or electrical contact pads, resulting in deformation of the line shape, as well as a decrease in yield and reliability, has become an urgent problem to be overcome in the industry.

Contents of the invention

In view of the defects of the prior art, an object of the present invention is to provide a packaging substrate and its manufacturing method and packaging structure, which can avoid problems such as difficult control of solder amount, yield and reliability reduction, and the like.

Another object of the present invention is to provide a packaging substrate and its manufacturing method and packaging structure, which can avoid the metal bumps from being provided entirely by the chip end, and do not need to form a solder mask on the substrate to avoid deformation of the circuit, and Yield and reliability decline and other issues.

In order to achieve the above purpose and other purposes, the present invention provides a packaging substrate, comprising: a substrate body, at least one surface of which has a plurality of electrical contact pads and circuits; an insulating layer, arranged on the surface of the substrate body, the electrical On the electrical contact pad and the circuit, and the thickness of the insulating layer is smaller than the thickness of the electrical contact pad, and has a plurality of corresponding openings in the insulating layer exposing the upper surface of each electrical contact pad; and a plurality of first The metal bump is corresponding to the upper surface of the electrical contact pad arranged in each opening of the insulating layer, and protrudes from the insulating layer.

According to the packaging substrate, the openings in the insulating layer can correspondingly expose part or all of the upper surfaces of the electrical contact pads.

According to the described structure, it may also include solder or a surface treatment layer, which is provided on the first metal bump; the material for forming the solder may be tin (Sn), lead (Pb), gold (Au), copper (Cu ), nickel (Ni), silver (Ag), and one of their group alloys, and the material forming the surface treatment layer can be nickel/gold (Ni/Au), nickel palladium immersion gold (Electroless Nickel One of /ElectrolessPalladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag), and gold (Au).

The present invention also provides another packaging substrate, including: a substrate body, at least one surface of which has a plurality of electrical contact pads and circuits; a plurality of first metal bumps, correspondingly arranged on each of the electrical contact pads; and an insulating layer , provided on the surface of the substrate body, the electrical contact pads, the circuit and the first metal bump, and the thickness of the insulating layer is smaller than the thickness of the electrical contact pads, and has a plurality of corresponding exposed Holes are opened in the insulating layer on the upper surface of the first metal bump.

According to the packaging substrate, the openings in the insulating layer can correspondingly expose part or all of the upper surfaces of the first metal bumps.

According to the described structure, it may also include solder or a surface treatment layer, which is provided on the first metal bump; the material for forming the solder may be tin (Sn), lead (Pb), gold (Au), copper (Cu ), nickel (Ni), silver (Ag), and one of their group alloys, and the material forming the surface treatment layer can be nickel/gold (Ni/Au), nickel palladium immersion gold (Electroless Nickel One of /ElectrolessPalladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag), and gold (Au).

The present invention also provides a method for manufacturing a packaging substrate, including: providing a substrate body, at least one surface of which has a plurality of electrical contact pads and circuits; layer, and the thickness of the insulating layer is smaller than the thickness of the electrical contact pad; a plurality of insulating layer openings are formed in the insulating layer corresponding to expose the upper surface of each of the electrical contact pads; and in each of the electrical contact pads The exposed upper surface of the contact pad forms a first metal bump.

According to the manufacturing method, the openings in the insulating layer can correspondingly expose part or all of the upper surfaces of the electrical contact pads.

According to the manufacturing method of the packaging substrate, it may also include forming solder or a surface treatment layer on the first metal bump; the material for forming the solder may be tin (Sn), lead (Pb), gold (Au), One of copper (Cu), nickel (Ni), silver (Ag), and their group alloys, and the material forming the surface treatment layer can be nickel/gold (Ni/Au), nickel palladium immersion gold (Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag), and gold (Au).

The present invention also provides another method for manufacturing a packaging substrate, including: providing a substrate body, at least one surface of which has a conductive layer; forming a first resistance layer on the conductive layer, and the first resistance layer has a plurality of patterned Opening areas; forming a circuit layer in these opening areas, the circuit layer includes a plurality of electrical contact pads and circuits; forming a second resistance layer on the first resistance layer and the circuit layer, the second resistance layer has a plurality of corresponding Exposing the resistance layer openings of each of the electrical contact pads; forming a first metal bump in each of the resistance layer openings; removing the second resistance layer, the first resistance layer and the covered conductive layer; An insulating layer is formed on the first metal bump, the electrical contact pad, the circuit and the substrate body, and the thickness of the insulating layer is smaller than the thickness of the electrical contact pad; and a plurality of corresponding exposed surfaces are formed in the insulating layer Holes are opened in the insulating layer on the upper surface of each of the first metal bumps.

According to the manufacturing method, the openings in the insulating layer can correspondingly expose part or all of the upper surfaces of the first metal bumps.

According to the method for making the packaging substrate, it may also include forming solder or a surface treatment layer on the upper surface of the first metal bump exposed from the opening of each insulating layer; the material for forming the solder can be tin (Sn), lead (Pb), gold (Au), copper (Cu), nickel (Ni), silver (Ag), and one of their group alloys, and the material forming the surface treatment layer can be nickel/gold (Ni /Au), nickel-palladium immersion gold (Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag), and gold (Au).

The present invention provides a packaging structure, comprising: a substrate body, at least one surface of which has a plurality of electrical contact pads and circuits; an insulating layer is provided on the surface of the substrate body, the electrical contact pads and circuits, and the The thickness of the insulating layer is smaller than the thickness of the electrical contact pads, and has a plurality of openings in the insulating layer corresponding to expose the upper surface of each electrical contact pad; a plurality of first metal bumps are correspondingly arranged on each insulating layer. The surface of the electrical contact pad in the opening of the layer protrudes from the insulating layer; and the semiconductor chip has an active surface, and the active surface has a plurality of electrode pads, and a second metal bump is arranged on each of the electrode pads. block, these second metal bumps are electrically connected to each of the first metal bumps through solder, and the material for forming the solder can be tin (Sn), lead (Pb), gold (Au), copper (Cu) , nickel (Ni), silver (Ag), and one of their group alloys.

According to the packaging structure, the openings in the insulating layer can correspondingly expose part or all of the upper surfaces of the electrical contact pads.

According to the above structure, an underfill material may also be included, disposed between the substrate body and the semiconductor chip; or, a molding compound may also be included, disposed between the substrate body and the semiconductor chip, and covering the semiconductor chip. chip.

The present invention also provides another packaging structure, comprising: a substrate body, at least one surface of which has a plurality of electrical contact pads and circuits; a plurality of first metal bumps, correspondingly provided on each of the electrical contact pads; an insulating layer, It is provided on the surface of the substrate body, the electrical contact pads, the circuit and the first metal bump, and the thickness of the insulating layer is smaller than the thickness of the electrical contact pads, and has a plurality of corresponding exposed first metal bumps. An insulating layer opening on the upper surface of a metal bump; and a semiconductor chip, which has an active surface, and the active surface has a plurality of electrode pads, and second metal bumps are arranged on each of the electrode pads, and these second metal bumps The block is electrically connected to each of the first metal bumps through solder, and the material for forming the solder can be tin (Sn), lead (Pb), gold (Au), copper (Cu), nickel (Ni), silver (Ag), one of its group alloys.

According to the packaging structure, the insulating layer openings can correspondingly expose part or all of the upper surfaces of the first metal bumps.

According to the above structure, an underfill material may also be included, disposed between the substrate body and the semiconductor chip; or, a molding compound may also be included, disposed between the substrate body and the semiconductor chip, and covering the semiconductor chip. chip.

As can be seen from the above, the packaging substrate of the present invention and its manufacturing method and packaging structure mainly form an insulating layer on the surface of the electrical contact pad, circuit and substrate body, and then form an insulating layer opening in the insulating layer. The upper surface of the electrical contact pad is exposed, then, a first metal bump and solder are formed on the electrical contact pad in the opening of the insulating layer, and finally, the semiconductor chip is connected through the solder.

Therefore, in the packaging substrate and its manufacturing method and packaging structure of the present invention, the solder is not easy to produce bridging phenomenon, which is beneficial to the packaging of fine pitches; The structure of the first metal bump can be elastically adjusted to obtain stable reliability and packaging quality, and at the same time, the cost is relatively lower; in addition, the present invention does not need to form a solder resist layer on the substrate, thereby reducing the number of connections between the substrate and the substrate. The stress caused by the mismatch of coefficient of thermal expansion (CTE) between filling materials, semiconductor chips, and molding compounds, and the electrical contact pads or lines do not need to be roughened, but can have a good The shape of the line and the shape of the metal bump.

Description of drawings

1A to 1D are schematic cross-sectional views of a conventional packaging structure manufacturing method;

2A to 2F are schematic cross-sectional views of the first embodiment of the packaging substrate and its manufacturing method and packaging structure of the present invention; wherein, FIG. 2C' is another embodiment of FIG. 2C, and FIG. 2D' is another embodiment of FIG. 2D Embodiment, Fig. 2E' is another embodiment of Fig. 2E, Fig. 2F' is another embodiment of Fig. 2F;

3A to 3H are schematic cross-sectional views of the second embodiment of the packaging substrate and its manufacturing method and packaging structure of the present invention; wherein, FIG. 3F' is another embodiment of FIG. 3F, and FIG. 3G' is another embodiment of FIG. 3G Embodiment, Fig. 3H' is another embodiment of Fig. 3H.

Description of main component symbols:

10, 30, 50 substrate body

10a, 30a, 50a surface

111, 311, 531 lines

112, 312, 532 electrical contact pads

12 solder mask

120 solder mask opening

14, 14', 34a, 34', 57a, 57' solder

20, 40 semiconductor chip

20a, 40a action surface

21, 41 electrode pads

22 metal bumps

312a, 55a upper surface

32, 56 insulating layer

320, 560 insulating layer openings

33, 55 first metal bump

34b, 57b surface treatment layer

42 second metal bump

43 Bottom filling material

44 molding compound

51 conductive layer

52 first resistance layer

520 opening area

53 line layer

54 second resistance layer

540 resistance layer opening

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

first embodiment

Please refer to FIG. 2A to FIG. 2F , which are cross-sectional schematic diagrams of a first embodiment of the packaging substrate, its manufacturing method, and packaging structure of the present invention.

As shown in FIG. 2A , firstly, a substrate body 30 is provided, at least one surface 30 a of which has a plurality of electrical contact pads 312 and circuits 311 , and the electrical contact pads 312 and circuits 311 can be copper materials.

As shown in FIG. 2B, an insulating layer 32 is formed on the surface 30a of the electrical contact pads 312, the circuit 311 and the substrate body 30, and the thickness of the insulating layer 32 is smaller than the thickness of the electrical contact pads 312 and the circuit 311. ; The insulating layer 32 can be an organic resin with good bonding force with copper, and the better thickness of the insulating layer 32 can be 0.5 to 8 microns (μm); in addition, the method for forming the insulating layer 32 can be spraying (spray ), liquid immersion (dip), coating (coating) or printing.

As shown in FIG. 2C, a plurality of insulating layer openings 320 are formed in the insulating layer 32 corresponding to parts of the upper surface 312a of each of the electrical contact pads 312; Therefore, the insulating layer opening 320 can be formed by laser ablation, plasma or pumice. Alternatively, as shown in FIG. 2C', a plurality of insulating layer openings 320 correspondingly exposing the entire upper surface 312a of each of the electrical contact pads 312 may be formed in the insulating layer 32.

As shown in FIG. 2D and FIG. 2D', continuing from FIG. 2C and FIG. 2C' respectively, a first metal bump 33 is formed on the exposed upper surface 312a of each of the electrical contact pads 312; The method can be electroplating or electroless plating. Subsequent steps are only described with the structure shown in FIG. 2D.

As shown in FIG. 2E and FIG. 2E', solder 34a is formed on the first metal bump 33, as shown in FIG. 2E; or, a surface treatment layer 34b is formed on the first metal bump 33, as shown in FIG. 2E' shown; the following steps are only described with the structure shown in FIG. 2E.

In this embodiment, the material of the solder 34a can be tin (Sn), lead (Pb), gold (Au), copper (Cu), nickel (Ni), silver (Ag), and the groups thereof One of the alloy, and the material of the surface treatment layer 34b can be nickel/gold (Ni/Au), nickel palladium immersion gold (Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG), tin (Sn), One of silver (Ag) and gold (Au).

2F and FIG. 2F', a semiconductor chip 40 with an active surface 40a is placed above the substrate body 30, and the active surface 40a of the semiconductor chip 40 has a plurality of electrode pads 41, on each of which electrode pads 41 There are second metal bumps 42, and these second metal bumps 42 are electrically connected to each of the first metal bumps 33 through solder 34'; then, between the surface 30a of the substrate body 30 and the semiconductor chip 40 Form the bottom filling material 43, as shown in Figure 2F; Alternatively, form a molding compound (molding compound) 44 between the surface 30a of the substrate body 30 and the semiconductor chip 40, and the molding compound 44 also covers the semiconductor chip 40 , as shown in Figure 2F'.

The present invention also provides a packaging substrate, including: a substrate body 30, at least one surface 30a of which has a plurality of electrical contact pads 312 and circuits 311; an insulating layer 32, arranged on the surface 30a of the substrate body 30, the On the contact pad 312 and the circuit 311, and the thickness of the insulating layer 32 is smaller than the thickness of the electrical contact pad 312, and has a plurality of corresponding insulating layer openings 320 that expose the upper surface 312a of each electrical contact pad 312 and a plurality of first metal bumps 33 corresponding to the surface of the electrical contact pads 312 in the openings 320 of the insulating layer and protruding from the insulating layer 32 .

According to the package substrate, the insulating layer opening 320 can expose part of the upper surface 312 a or the entire upper surface 312 a of the electrical contact pad 312 .

In the described structure, it may also include solder 34a or surface treatment layer 34b, which is arranged on the first metal bump 33; the material for forming the surface treatment layer 34b may be nickel/gold (Ni/Au), nickel One of Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), tin (Sn), silver (Ag), and gold (Au).

The present invention may also include a semiconductor chip 40 having an active surface 40a, on which a plurality of electrode pads 41 are provided, and second metal bumps 42 are arranged on each of the electrode pads 41, and these second metal bumps 42 pass through The solder 34' is electrically connected to each of the first metal bumps 33; the material forming the solder 34a, 34' can be tin (Sn), lead (Pb), gold (Au), copper (Cu), nickel (Ni), silver (Ag), and one of the group alloys formed therefrom.

In the described structure, an underfill material 43 may also be included, disposed between the substrate body 30 and the semiconductor chip 40; or, a molding compound 44 may also be included, disposed between the substrate body 30 and the semiconductor chip 40 , and wrap the semiconductor chip 40 .

second embodiment

Please refer to FIG. 3A to FIG. 3H , which are schematic cross-sectional views of a second embodiment of the packaging substrate, its manufacturing method, and packaging structure of the present invention.

As shown in FIG. 3A , first, a substrate body 50 is provided, at least one surface 50 a of which has a conductive layer 51 .

As shown in FIG. 3B, a first resistive layer 52 is formed on the conductive layer 51, and a plurality of patterned opening regions 520 are formed in the first resistive layer 52; The circuit layer 53 is formed by electroplating, and the circuit layer 53 includes a plurality of electrical contact pads 532 and the circuit 531 , and the circuit layer 53 can be made of copper material.

As shown in FIG. 3C, a second resistive layer 54 is formed on the first resistive layer 52 and the circuit layer 53, and a plurality of resistive layer openings are formed in the second resistive layer 54 to expose the electrical contact pads 532. Hole 540.

As shown in FIG. 3D , a first metal bump 55 is formed in each of the resist openings 540 ; the method of forming the first metal bump 55 can be electroplating or electroless plating.

As shown in FIG. 3E, the second resistance layer 54, the first resistance layer 52 and the conductive layer 51 covered therewith are removed to expose the surface of the substrate body 50, the circuit layer 53, and the electrical contact pad formed on 532 on the first metal bump 55; after that, an insulating layer 56 is formed on the first metal bump 55, the electrical contact pad 532, the circuit 531 and the surface 50a of the substrate body 50, and the thickness of the insulating layer 56 Less than the thickness of the electrical contact pad 532; the insulating layer 56 can be an organic resin with good bonding force with copper, and the more preferable thickness of the insulating layer 56 can be 0.5 to 8 microns (μm); in addition, forming the The insulating layer 56 can be sprayed, dipped, coated or printed.

As shown in FIG. 3F , a plurality of insulating layer openings 560 are formed in the insulating layer 56 to correspondingly expose part of the upper surface 55a of each of the first metal bumps 55; because the insulating layer 56 is larger than the existing solder resist The layer is thin, so laser ablation, plasma or pumice can be used to form the insulating layer opening 560 . Alternatively, as shown in FIG. 3F', a plurality of insulating layer openings 560 may be formed in the insulating layer 56 to expose the entire upper surface 55a of each of the first metal bumps 55 correspondingly. Subsequent steps are only described with the structure shown in FIG. 3F.

As shown in FIG. 3G and FIG. 3G', solder 57a is formed on the upper surface 55a of the first metal bump 55 exposed by each opening 560 of the insulating layer, as shown in FIG. 3G; or, a hole is opened in each insulating layer 560 to form a surface treatment layer 57b on the upper surface 55a of the exposed first metal bump 55 , as shown in FIG. 3G ′; the following steps are only described with the structure shown in FIG. 3G .

In this embodiment, the material of the solder 57a can be tin (Sn), lead (Pb), gold (Au), copper (Cu), nickel (Ni), silver (Ag), and the groups thereof One of the alloy, and the material of the surface treatment layer 57b can be nickel/gold (Ni/Au), nickel palladium immersion gold (Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG), tin (Sn), One of silver (Ag) and gold (Au).

As shown in Fig. 3H and Fig. 3H', a semiconductor chip 40 with an active surface 40a is placed above the substrate body 50, and the active surface 40a of the semiconductor chip 40 has a plurality of electrode pads 41, on each of which electrode pads 41 There are second metal bumps 42, and these second metal bumps 42 are electrically connected to each of the first metal bumps 55 through solder 57'; then, between the surface 50a of the substrate body 50 and the semiconductor chip 40 Form an underfill material 43, as shown in FIG. 3H; or, form a molding compound 44 between the surface 50a of the substrate body 50 and the semiconductor chip 40, and the molding compound 44 covers the semiconductor chip 40, as shown in FIG. 3H 'shown.

The present invention also provides another packaging substrate, including: a substrate body 50, at least one surface 50a of which has a plurality of electrical contact pads 532 and circuits 531; on the surface of the pad 532; and an insulating layer 56, which is arranged on the surface 50a of the substrate body 50, the electrical contact pad 532, the circuit 531 and the first metal bump 55, and the thickness of the insulating layer 56 is smaller than the The thickness of the electrical contact pad 532 has a plurality of insulating layer openings 560 correspondingly exposing the upper surface 55 a of each of the first metal bumps 55 .

According to the package substrate, the insulating layer opening 560 can expose part of the upper surface 55 a or the entire upper surface 55 a of the first metal bump 55 .

In the described structure, solder 57a or surface treatment layer 57b may also be included, which is arranged on the first metal bump 55; the material for forming the surface treatment layer 57b may be nickel/gold (Ni/Au), nickel One of Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), tin (Sn), silver (Ag), and gold (Au).

The present invention may also include a semiconductor chip 40 having an active surface 40a, and the active surface 40a has a plurality of electrode pads 41, and second metal bumps 42 are arranged on each of the electrode pads 41, and these second metal bumps 42 pass through Solder 57' is electrically connected to each of the first metal bumps 55; the material forming the solder 57a, 57' can be tin (Sn), lead (Pb), gold (Au), copper (Cu), nickel (Ni), silver (Ag), and one of the group alloys formed therefrom.

In the described structure, an underfill material 43 may also be included, disposed between the substrate body 50 and the semiconductor chip 40; or, a molding compound 44 may also be included, disposed between the substrate body 50 and the semiconductor chip 40 , and wrap the semiconductor chip 40 .

To sum up, the packaging substrate of the present invention and its manufacturing method and packaging structure are mainly to form an insulating layer on the surface of the electrical contact pad, circuit and substrate body, and then form an insulating layer opening in the insulating layer; then, Form the first metal bump and solder on the electrical contact pad in the opening of the insulating layer; finally, connect the semiconductor chip through the solder, so as to avoid the solder bridge phenomenon and facilitate the packaging of fine pitch; and the The first metal bump is formed on the substrate body, and the first metal bump can be elastically designed according to different situations, so it is easy to obtain stable reliability and packaging quality, and the cost is relatively low; Form a solder resist layer, which can reduce the stress caused by the mismatch of coefficient of thermal expansion (CTE) with the underfill material, semiconductor chip, and molding compound, and because the electrical contact pad or line does not need to be roughened. Manufacturing process , so a good line shape and metal bump shape can be formed.

The embodiments are only illustrative to illustrate the principle of the present invention and its effect, but not to limit the present invention. Any person skilled in the art can modify and change the embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope of the claims.

Claims (8)

1. A packaging substrate, characterized in that, comprising: A substrate body, at least one surface of which has a plurality of electrical contact pads and circuits; The insulating layer is arranged on the surface of the substrate body, the electrical contact pads and the circuit, and the thickness of the insulating layer is smaller than the thickness of the electrical contact pads, and has a plurality of corresponding exposed electrical contact pads. insulation openings on the entire upper surface of the A plurality of first metal bumps correspond to the upper surfaces of the electrical contact pads disposed in the openings of the insulating layer and protrude from the insulating layer. 2. The package substrate according to claim 1, further comprising a solder or a surface treatment layer disposed on the first metal bump. 3. A packaging substrate, characterized in that, comprising: A substrate body, at least one surface of which has a plurality of electrical contact pads and circuits; A plurality of first metal bumps are correspondingly provided on each of the electrical contact pads; and The insulating layer is arranged on the surface of the substrate body, the electrical contact pads, the circuit and the first metal bump, and the thickness of the insulating layer is smaller than the thickness of the electrical contact pads, and has a plurality of corresponding exposed Holes are opened in the insulating layer on the upper surface of each of the first metal bumps. 4 . The packaging substrate according to claim 3 , wherein the openings in the insulating layer correspond to exposing part or all of the upper surfaces of the first metal bumps. 5. The package substrate according to claim 3, further comprising solder or a surface treatment layer disposed on the first metal bump. 6. A packaging structure, characterized in that, comprising: A substrate body, at least one surface of which has a plurality of electrical contact pads and circuits; The insulating layer is arranged on the surface of the substrate body, the electrical contact pads and the circuit, and the thickness of the insulating layer is smaller than the thickness of the electrical contact pads, and has a plurality of corresponding exposed electrical contact pads. The insulation layer openings on the entire upper surface of the A plurality of first metal bumps are correspondingly arranged on the surface of the electrical contact pads in the openings of the insulating layer and protrude from the insulating layer; and The semiconductor chip has an active surface, and the active surface has a plurality of electrode pads, and second metal bumps are arranged on each of the electrode pads, and the second metal bumps are electrically connected to each of the first metal bumps through solder. Metal bumps. 7. A packaging structure, characterized in that, comprising: A substrate body, at least one surface of which has a plurality of electrical contact pads and circuits; A plurality of first metal bumps are correspondingly arranged on each of the electrical contact pads; The insulating layer is arranged on the surface of the substrate body, the electrical contact pads, the circuit and the first metal bump, and the thickness of the insulating layer is smaller than the thickness of the electrical contact pads, and has a plurality of corresponding exposed openings in the insulating layer on the upper surface of each of the first metal bumps; and The semiconductor chip has an active surface, and the active surface has a plurality of electrode pads, and a second metal bump is arranged on each of the electrode pads, and the second metal bump is electrically connected to each of the first metal bumps through solder. bump. 8 . The package structure according to claim 7 , wherein the openings in the insulating layer correspond to exposing part or all of the upper surfaces of the first metal bumps.

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