CN101977039B - Congestion control based monostable circuit - Google Patents

Abstract

The present invention relates to a monostable circuit based on blocking control, the source of the first PMOS transistor P1 is connected to the power supply voltage, the drain is connected to the source of the second PMOS transistor P2, and the gate is controlled by the input voltage; The gate of the two PMOS transistor P2 is controlled by the signal at the output terminal of the inverter I2, and its drain is connected with the output terminal of the transmission gate T1, the input terminal of the inverter I1 and one end of the capacitor N1; the other end of the capacitor N1 is grounded; The output end of the phaser I1 is connected with the input end of the transmission gate T2; the output end of the transmission gate T2 is connected with the input end of the inverter I2; the output end of the inverter I2 is connected with the input end of the inverter I3 The output terminal of the inverter I3 is the output terminal VOUT of the monostable circuit, and this output terminal is connected to the input terminal of the transmission gate T1 by feedback; the two transmission gates are respectively controlled by the two transmission gates The input signal of the control terminal makes only one transmission gate conduction at the same time to realize blocking control.

Description

A Monostable Circuit Based on Blocking Control

technical field

The invention relates to a monostable circuit, in particular to a monostable circuit based on blocking control.

Background technique

A monostable circuit has only one stable state. Under the action of an external trigger pulse, the circuit turns from a steady state to a transient state. After the transient state is maintained for a period of time, it returns to a steady state and generates a rectangular pulse at the output.

Since the transient time of the monostable circuit is determined by the internal parameters of the circuit, the monostable flip-flop is widely used in pulse shaping, delay and timing. The transient state of the monostable trigger is usually maintained by the charging and discharging process of the RC circuit. The RC circuit can be connected into two forms: differential and integral circuit forms.

Traditional monostable circuits mainly have two structures: integral type and differential type. The schematic diagram of the integral monostable flip-flop circuit is shown in Figure 1. When V _i changes from low level to high level in the traditional integral monostable circuit, after passing through the inverter G1, the output of V ₀₁ is switched from high level to high level. When V _A is lower than the threshold voltage _of G2, V ₀ changes from low to high and returns _to a steady state. state. The low-level pulse width in this process is determined by the RC constant in the circuit. Signals with different pulse widths can be obtained by adjusting the RC constant. The schematic diagram of the differential type monostable flip-flop circuit is shown in Figure 2. The working principle of the differential type monostable flip-flop is similar to that of the integral type, except that the mechanism for controlling the steady state time is different. Generally speaking, the transient time in a monostable circuit is determined by the size of the RC parameter in the circuit.

However, regardless of the monostable circuit structure of the integral type or the differential type, if a longer transient time is to be generated, the value of RC in the circuit will also become larger. If the monostable circuit is to be integrated into the chip, due to the influence of resistors and capacitors, it will occupy a lot of chip area, which is very unfavorable for integrated design. Especially the differential monostable circuit, which uses more resistive and capacitive devices. In addition, once the application requirements are determined, the size of the RC parameters is also determined at the same time, which cannot be changed, and the reuse rate is poor. Finally, even if the RC value is small, it can be integrated into the entire system to generate characteristic pulse waveforms, and the transient time of the circuit will have an error of about 50% due to the drastic change of RC in different processes. The application environment with precise control of time is extremely unfavorable.

Contents of the invention

The purpose of the present invention is to solve the disadvantages of the existing monostable circuit and design a monostable circuit which is convenient for system integration and can accurately generate and easily control the transient time.

In order to achieve the purpose of the above invention, the present invention proposes a monostable circuit based on blocking control, which is characterized in that the monostable circuit includes: a first PMOS transistor P1, a second PMOS transistor P2, a first transmission gate T1, a second Two transmission gates T2, a capacitor N1, a first inverter I1, a second inverter I2 and a third inverter I3;

The source of the first PMOS transistor P1 is connected to the power supply voltage, its drain is connected to the source of the second PMOS transistor P2, and its gate is controlled by the input voltage;

The gate of the second PMOS transistor P2 is controlled by the signal at the output end of the second inverter I2, and its drain is connected to the output end of the first transmission gate T1 and the input end of the first inverter I1 connected to one end of the capacitor N1;

The other end of the capacitor N1 is grounded;

The output end of the first inverter I1 is connected to the input end of the second transmission gate T2; the output end of the second transmission gate T2 is connected to the input end of the second inverter I2; the The output end of the second inverter I2 is connected to the input end of the third inverter I3;

The output terminal of the third inverter I3 is the output terminal VOUT of the monostable circuit, and the output terminal is feedback-connected to the input terminal of the first transmission gate T1;

The first transmission gate T1 and the second transmission gate T2 are respectively controlled by the input signals of the control terminals of the first transmission gate T1 and the second transmission gate T2, so that only one transmission gate is turned on at the same time to realize blocking control.

The capacitor N1 is a MOS capacitor, the gate of the MOS capacitor is connected to the output terminal of the first transmission gate T1, the input terminal of the first inverter I1 and the drain of the second PMOS transistor P2 , the source and drain of the MOS capacitor are connected and grounded.

The monostable circuit based on blocking control also includes a fourth inverter I4, the output end of the fourth inverter I4 is connected to the input end of the second inverter I2, and the fourth inverter I4 is connected to the input end of the second inverter I2. The input end of the inverter I4 is connected to the output end of the second inverter I2.

As an option of the present invention, the second transmission gate T2 adopts an NMOS structure, and the monostable circuit based on blocking control also includes a NOR gate and a fifth inverter I5, and the NOR gate One input terminal is connected with the input terminal of the second inverter I2, the other input terminal of the NOR gate is connected with the clock signal CLK, and the output of the NOR gate is the first signal NCLK1, which is connected with the fifth NCLK1. The input terminal of the inverter I5 is connected, the output of the fifth inverter I5 is the second signal CLK1, and the second signal CLK1 is used as the input signal of the control terminal of the second transmission gate T2 to control the second transmission gate T2 .

As another option of the present invention, the second transmission gate T2 adopts a CMOS structure, and the monostable circuit based on blocking control also includes a NOR gate and a fifth inverter I5, and the NOR gate One input end of the NOR gate is connected to the input end of the second inverter I2, the other input end of the NOR gate is connected to the clock signal CLK, and the output of the NOR gate is the first signal NCLK1, which is related to the first signal NCLK1. The input terminals of the five inverters I5 are connected, the output of the fifth inverter I5 is the second signal CLK1, and the first signal NCLK1 and the second signal CLK1 are used as the input signal of the control terminal of the second transmission gate T2 to control the Describe the second transmission gate T2.

As another option of the present invention, the second transmission gate T2 adopts a PMOS structure, and the monostable circuit based on blocking control further includes a NOR gate, and an input terminal of the NOR gate is connected to the The input end of the second inverter I2 is connected, the other input end of the NOR gate is connected to the clock signal CLK, the output of the NOR gate is the first signal NCLK1, and the first signal NCLK1 is used as the second The input signal at the control terminal of the transmission gate T2 controls the second transmission gate T2.

The monostable circuit based on blocking control also includes a second NMOS transistor N2 and a sixth inverter I6, the input terminal of the sixth inverter I6 is connected to the output terminal VOUT of the monostable circuit , the output terminal of the sixth inverter I6 is connected to the gate of the second NMOS transistor N2, the source of the second NMOS transistor N2 is grounded, and the drain of the second NMOS transistor N2 is connected to the gate of the second NMOS transistor N2. The input terminals of the first transmission gate T1 are connected together. in,

When the first transmission gate T1 is a transmission gate of CMOS structure, the gate of the PMOS transistor of the first transmission gate T1 is a control terminal, and the control terminal is connected to the clock signal CLK, and the gate of the NMOS transistor of the first transmission gate T1 Extremely another control terminal, which is connected to the reverse signal NCLK of the clock signal CLK;

The second transmission gate T2 is a transmission gate of a CMOS structure, and the gate of the PMOS transistor of the second transmission gate T2 is a control terminal, which is connected to the inverse signal NCLK of the clock signal or the output of the NOR gate The gate of the NMOS transistor of the second transmission gate T2 is another control terminal, and the control terminal is connected to the clock signal CLK or the second signal CLK1 output by the inverter; or

The second transmission gate T2 is a transmission gate with a PMOS structure, and the control terminal of the second transmission gate T2 is connected to the inverse signal NCLK of the clock signal or the first signal NCLK1 output by the NOR gate; or

The second transmission gate T2 is a transmission gate of NMOS structure, and a control terminal of the second transmission gate T2 is connected to the clock signal CLK or the first signal CLK1 output by the inverter.

When the first transmission gate T1 is a transmission gate with a PMOS structure, the control terminal of the first transmission gate T1 is connected to the clock signal CLK;

The second transmission gate T2 is a transmission gate with a CMOS structure, and the gate of the PMOS transistor of the second transmission gate T2 is a control terminal, which is connected to the reverse signal NCLK of the clock signal CLK or the output of the NOR gate. The first signal NCLK1, the gate of the NMOS transistor in the second transmission gate T2 is another control terminal, and the control terminal is connected to the clock signal CLK or the second signal CLK1 output by the inverter; or

The second transmission gate T2 is a transmission gate with a PMOS structure, and the control terminal of the transmission gate T2 is connected to the inverse signal NCLK of the clock signal CLK or the first signal NCLK1 output by the NOT gate; or

The second transmission gate T2 is a transmission gate of NMOS structure, and the control terminal of the second transmission gate T2 is connected to the clock signal CLK or the second signal CLK1 output by the inverter.

When the first transmission gate T1 is a transmission gate with an NMOS structure, the control terminal of the first transmission gate T1 is connected to the reverse signal NCLK of the clock signal CLK;

The second transmission gate T2 is a transmission gate of a CMOS structure, and the gate of the PMOS transistor of the second transmission gate T2 is a control terminal, which is connected to the inverse signal NCLK of the clock signal or the output of the NOR gate The gate of the NMOS transistor of the second transmission gate T2 is another control terminal, and the control terminal is connected to the clock signal CLK or the second signal CLK1 output by the inverter; or

The second transmission gate T2 is a transmission gate with a PMOS structure, and the control terminal of the second transmission gate T2 is connected to the inverse signal NCLK of the clock signal or the first signal NCLK1 output by the inverter; or

The second transmission gate T2 is a transmission gate of NMOS structure, and the control terminal of the second transmission gate T2 is connected to the clock signal CLK or the second signal CLK1 output by the inverter.

To achieve the purpose of the above invention, the present invention also proposes a monostable circuit based on blocking control, which is characterized in that the monostable circuit includes: a first NMOS transistor N1, a second NMOS transistor N2, a first transmission gate T1, The second transmission gate T2, the capacitor P1, the first inverter I1, the second inverter I2 and the third inverter I3;

The source of the second NMOS transistor N2 is grounded, its drain is connected to the source of the first NMOS transistor N1, and its gate is controlled by an input voltage;

The gate of the first NMOS transistor N1 is controlled by the signal from the output terminal of the second inverter I2, feedback controls the discharge process of the second NMOS transistor N2, and its drain is connected to the second transmission gate The output terminal of T1, the input terminal of the first inverter I1 and one end of the capacitor P1 are connected;

The other end of the capacitor P1 is connected to a power supply voltage;

The output terminal of the first inverter I1 is connected to the input terminal of the second transmission gate T2;

The output end of the second transmission gate T2 is connected to the input end of the second inverter I2;

The output end of the second inverter I2 is connected to the input end of the third inverter I3;

The output terminal of the third inverter I3 is the output terminal VOUT of the monostable circuit, and the output signal is fed back and connected to the input terminal of the first transmission gate T1;

The first transmission gate T1 and the second transmission gate T2 are respectively controlled by the input signal of the transmission gate control terminal, so that only one transmission gate is turned on at the same time to realize blocking control.

The capacitor P1 is a MOS capacitor, the gate of the MOS capacitor is connected to the output terminal of the first transmission gate T1, the input terminal of the first inverter I1 and the drain of the first NMOS transistor N1 , the source and drain of the MOS capacitor are connected and connected to the power supply voltage.

The monostable circuit based on blocking control also includes a fourth inverter I4, the output end of the fourth inverter I4 is connected to the input end of the second inverter I2, and the fourth inverter I4 is connected to the input end of the second inverter I2. The input end of the inverter I4 is connected to the output end of the second inverter I2.

As an option of the present invention, the second transmission gate T2 adopts an NMOS structure, and the monostable circuit based on blocking control also includes a NOR gate and a fifth inverter I5, and the NOR gate One input end is connected to the output end of the second inverter I2, the other input end of the NOR gate is connected to the clock signal CLK, and the output of the NOR gate is the first signal NCLK1, which is the same as the first signal NCLK1. The input terminals of five inverters I5 are connected, the output clock signal of the fifth inverter I5 is the second signal CLK1, and the second signal CLK1 is used as the input signal of the control terminal of the second transmission gate T2 to control the second Transmission gate T2.

As another option of the present invention, the second transmission gate T2 adopts a CMOS structure, and the monostable circuit based on blocking control also includes a NOR gate and a fifth inverter I5, and the NOR gate One input end of the NOR gate is connected to the output end of the second inverter I2, the other input end of the NOR gate is connected to the clock signal CLK, and the output of the NOR gate is the first signal NCLK1, which is related to the first signal NCLK1. The input terminals of the five inverters I5 are connected, the output of the fifth inverter I5 is the second signal CLK1, and the first signal NCLK1 and the second signal CLK1 are used as the input signal of the control terminal of the second transmission gate T2 to control the Describe the second transmission gate T2.

As another option of the present invention, the second transmission gate T2 adopts a PMOS structure, and the monostable circuit based on blocking control further includes a NOR gate, and an input terminal of the NOR gate is connected to the The output end of the second inverter I2 is connected, the other input end of the NOR gate is connected to the clock signal CLK, the output of the NOR gate is the first signal NCLK1, and the first signal NCLK1 is used as the second The input signal at the control terminal of the transmission gate T2 controls the second transmission gate T2.

The monostable circuit based on blocking control also includes a PMOS transistor P2 and a sixth inverter I6, the input terminal of the sixth inverter I6 is connected to the output terminal VOUT of the monostable circuit, so The output terminal of the sixth inverter I6 is connected to the gate of the PMOS transistor P2, the source of the PMOS transistor P2 is connected to the power supply voltage, and the drain of the PMOS transistor P2 is connected to the first transmission gate T1. connected to the input. in,

When the first transmission gate T1 is a transmission gate of CMOS structure, the gate of the PMOS transistor of the first transmission gate T1 is a control terminal, and the control terminal is connected to the clock signal CLK, and the gate of the NMOS transistor of the first transmission gate T1 Extremely another control terminal, which is connected to the reverse signal NCLK of the clock signal;

The second transmission gate T2 is a transmission gate of CMOS structure, the gate of the PMOS transistor in the second transmission gate T2 is a control terminal, and the control terminal is connected to the output of the NOR gate of the reverse signal NCLK of the clock signal The gate of the NMOS transistor of the second transmission gate T2 is another control terminal, and the control terminal is connected to the clock signal CLK or the second signal CLK1 output by the inverter; or

The second transmission gate T2 is a transmission gate with a PMOS structure, and the control terminal in the second transmission gate T2 is connected to the inverse signal NCLK of the clock signal or the first signal NCLK1 output by the NOR gate; or

The second transmission gate T2 is a transmission gate of NMOS structure, and the control terminal of the second transmission gate T2 is connected to the clock signal CLK or the second signal CLK1 output by the inverter.

When the first transmission gate T1 is a transmission gate with a PMOS structure, the control terminal of the first transmission gate T1 is connected to the clock signal CLK;

The second transmission gate T2 is a transmission gate of CMOS structure, the gate of the PMOS transistor in the second transmission gate T2 is a control terminal, and the control terminal is connected to the inverse signal NCLK of the clock signal CLK or the output of the NOR gate The gate of the NMOS transistor in the second transmission gate T2 is another control terminal, and the control terminal is connected to the clock signal CLK or the second signal CLK1 output by the inverter; or

The second transmission gate T2 is a transmission gate with a PMOS structure, and the control terminal of the second transmission gate T2 is connected to the inverse signal NCLK of the clock signal CLK or the first signal NCLK1 output by the NOT gate; or

The second transmission gate T2 is a transmission gate of NMOS structure, and the control terminal of the second transmission gate T2 is connected to the clock signal CLK or the second signal CLK1 output by the inverter.

When the first transmission gate T1 is a transmission gate with an NMOS structure, the control terminal in the first transmission gate T1 is connected to the reverse signal NCLK of the clock signal;

The second transmission gate T2 is a transmission gate of CMOS structure, the gate of the PMOS transistor in the second transmission gate T2 is a control terminal, and the control terminal is connected to the reverse signal NCLK of the clock signal or the output of the inverter. The first signal NCLK1, the gate of the NMOS transistor in the second transmission gate T2 is another control terminal, and the control terminal is connected to the clock signal CLK or the first signal CLK1 output by the inverter; or

The second transmission gate T2 is a transmission gate with a PMOS structure, and the control terminal of the second transmission gate T2 is connected to the inverse signal NCLK of the clock signal or the first signal NCLK1 output by the inverter; or

The second transmission gate T2 is a transmission gate of NMOS structure, and the control terminal of the second transmission gate T2 is connected to the clock signal CLK or the second signal CLK1 output by the inverter.

The invention has the advantages that the monostable circuit in the invention has no resistance design, is easy to integrate, and the transient time can be adjusted. The greatest feature of the circuit in the present invention is that the transient time variation range is small, which is beneficial to generate precise pulse control.

Description of drawings

Fig. 1 is the schematic diagram of integral monostable flip-flop circuit in the prior art;

Fig. 2 is the schematic diagram of differential monostable flip-flop circuit in the prior art;

Fig. 3 is the circuit diagram between clock signal CLK of the present invention and the reverse signal NCLK of clock signal;

Fig. 4 is the schematic diagram of the monostable circuit based on blocking control under the charging situation of the present invention;

Fig. 5 is the monostable circuit schematic diagram under the improved charging situation of the present invention;

Fig. 6 is the principle diagram of the monostable circuit in the case of charging to prevent retriggering of the present invention;

Fig. 7 is the output waveform of the monostable circuit under the charging situation preventing retriggering of the present invention;

Fig. 8 is the schematic diagram of the monostable circuit based on blocking control under the discharging situation of the present invention;

Fig. 9 is a schematic diagram of the monostable circuit under the improved discharge situation of the present invention;

FIG. 10 is a schematic diagram of a monostable circuit in the case of discharging to prevent retriggering according to the present invention.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

CMOS English full name: Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor; PMOS English full name: Positive Channel Metal Oxide Semiconductor, P-type metal oxide semiconductor; NMOS English full name: Negative Channel Mental Oxide Semiconductor, N-type metal oxide semiconductor.

In this embodiment, the CLK signal is used to represent the external trigger signal of the monostable circuit. The circuit diagram between the clock signal CLK and the reverse signal NCLK of the clock signal is shown in FIG. 3 . The clock signal CLK outputs the signal NCLK after passing through the inverter I1, and this signal is called the reverse signal of the clock signal CLK.

The schematic diagram of the monostable circuit based on blocking control in the case of charging is shown in Figure 4. Description of how the circuit works:

When CLK keeps high level, transmission gate T1 is turned off, transmission gate T2 is turned on, point A is at high level, point B is at low level, point C is at low level, point D is at high level, and VOUT is low, the circuit is in a steady state. When CLK becomes low level, the transmission gate T1 is opened, and the point A is discharged through the transmission gate T1. Since the transmission gate T2 is turned off at this time, the change of the node A causes the information of the level change of the point B to be blocked, and VF is still maintained at this time. High level, continue to turn off the charging path of the first PMOS transistor P1 to point A, so that the level of point A is initialized to low level, and the level of point B jumps high. However, due to the blocking effect of the transmission gate T2, the state of point C and point D will not be affected by the previous stage circuit, and the circuit maintains a steady state. When CLK becomes high again, the transmission gate T2 is opened, point C jumps high under the drive of the previous stage inverter, point D becomes low, and at this time the output VOUT also becomes high, the circuit enters a transient state, and point A starts Charge. However, since the transmission gate T2 is turned off, the possibility of VOUT charging to point A is blocked, and the transient state of the circuit will not be affected by the output state of the circuit at this time. During the transient state, point A starts to be charged by VB and VF controlling the PMOS transistor. When the voltage at point A is higher than the threshold of inverter I1, the voltage at point B jumps low, the voltage at point C jumps low, D becomes high, and VF becomes high to turn off the charging path from transistor P1 to point A, the circuit enters a steady state, and VOUT becomes Low. The pulse width of the output pulse of the overall circuit is determined by the charging time in the transient process. Wherein, the threshold of the inverter I1 is half of the supply voltage.

The schematic diagram of the monostable circuit under the improved charging condition is shown in Figure 5. On the basis of Figure 4, the circuit changes the clock signal controlling the transmission gate T2 by adding a NOR gate, thereby avoiding the error phenomenon caused by the CLK high level time being shorter than the transient time. When T2 adopts a CMOS structure or a PMOS structure, an inverter I5 needs to be added. What the T2 structure in Fig. 5 adopts is CMOS structure. Actual working principle: Since the NOR gate and an inverter are used, once the CLK signal jumps from low level to high level, T2 starts to conduct, so that the circuit enters a transient state, and point A begins to charge, and at A Before the charge at point A ends, point C remains high, so that the NCLK1 signal and CLK1 signal generated by VS and CLK signals will not change when CLK goes low early. Only when point A is charged beyond the inverter threshold, point C becomes When it is low, T2 will be turned off, so as to ensure that the information of transient changes can be transmitted to the output without being blocked by the turn-off of T2.

In the case of charging, the schematic diagram of the monostable circuit to prevent retriggering is shown in Figure 6. This circuit adds an inverter I6 and an NMOS transistor N2 on the basis of Fig. 5 . The so-called repeatable triggering refers to the situation that when the circuit has been triggered by CLK to enter the transient state, once the CLK level jumps low and then jumps high again, causing the circuit to re-enter the transient state. Actual working principle: The circuit detects the output signal through the transistor N2 to detect the state of the circuit. When the circuit is triggered by the CLK signal and enters a transient state, if it has not returned to a steady state, the gate control signal of N2 will remain at a low level, thereby So that point A will not be reset to low level when CLK is low level, thereby preventing the occurrence of triggering again. That is, it is ensured that a second trigger can only be performed after a transition from a transient state to a steady state is performed. The circuit can avoid the circuit state error caused by the glitch of the trigger signal, so that the circuit has a certain immunity to the transient spike and glitch.

In this example, experiments were done with a monostable circuit in the case of charging to prevent retriggering. The waveform diagram of the output monostable circuit is shown in Figure 7. It can be seen from Figure 7 that the monostable circuit ensures that the second trigger can only be performed after a transition from a transient state to a steady state, thereby avoiding the situation where the trigger signal generates glitches that cause circuit state errors, making the circuit Some immunity to transient spikes and glitches.

Under different PVTs (in PVT, P refers to the process technology, V refers to the voltage voltage, and T refers to the temperature temperature), the simulation results of the monostable circuit of the present invention are shown in Table 1. Table 1 shows the variation of the transient delay of 1us produced by the circuit under different PVTs. It can be seen from Table 1 that the biggest feature of the monostable circuit proposed by the present invention is that the transient time variation range is small, which is beneficial to generate precise pulse control. The simulation results show that the error produced by this circuit is only 10%, while the common integral monostable circuit has an error of 50% due to the change of resistance and capacitance when it is integrated on the chip, which is completely unusable in the case of strict time control .

Table 1 Transient delay under different PVT

Temp tt ss ff fnsp snfp -45 0.96 1 0.92 0.9 1 36 1 1.03 0.97 0.95 1.03 125 1.1 1.09 1.1 1.02 1.1

In Table 1, Temp is expressed as temperature in degrees Celsius. tt, ss, ff, fnsp/fs, snfp/sf respectively represent the simulation results under five different process angles. The simulation results in this embodiment are based on the smic18 process, where tt indicates that both NMOS and PMOS transistors are at the typical process angle; ss indicates that both the NMOS and PMOS transistors are at the slow process angle; ff indicates that the NMOS and PMOS transistors are at the slow process angle Both are in the fast process corner; fnsp/fs means that NMOS works in the fast process corner and PMOS works in the slow process corner; snfp/sf means that NMOS works in the slow process corner and PMOS works in the fast process corner.

The schematic diagram of the monostable circuit based on blocking control in the case of discharge is shown in Figure 8. Description of how the circuit works:

When the circuit is in a steady state, point A is turned off through the discharge path of the current source controlled by VF, and VF is at low level at this time, that is, point D in the circuit is also at low level, point C is at high level, and VOUT is at high level , when the CLK signal is low level, only the transmission gate T1 is turned on, then point A is high level at this time, and point B is flipped to low level at the same time, if the CLK signal does not change at this time, the circuit will maintain this state; once When the CLK signal becomes high level, only the transmission gate T2 is turned on, and the circuit enters a transient state. At this time, the state of point B is transmitted to point C via T2, respectively causing the level states of points C and D to flip, so that the level of point D is high, then VF is high at this time, and point A starts to pass through The current source controlled by VF discharges, and at the same time T1 is turned off, point A will not be affected by VOUT, when point A is discharged, the level of point B jumps to high level, and point C is also high level , point D is at low level, and VF turns off the discharge path of point A, so that the circuit ends the transient state and enters a steady state. The pulse width of the output pulse of the overall circuit is determined by the discharge time in the transient process.

The schematic diagram of the monostable circuit under the improved discharge condition is shown in Figure 9. On the basis of Figure 8, this circuit adds a NOR gate to control the clock signal of the transmission gate T2, thereby avoiding the error phenomenon caused by the high level time of CLK being shorter than the transient time. When T2 adopts a CMOS structure or a PMOS structure, an inverter I5 needs to be added. The T2 structure in Fig. 9 adopts a CMOS structure. Actual working principle: Due to the use of a NOR gate and an inverter, after the discharge at point A is completed, the VF level becomes a low level, and at this time the transmission gate T2 is allowed to close. Otherwise, even if the CLK signal jumps to a low level during the discharge time of point A, it will not cause T2 to be closed.

The schematic diagram of the monostable circuit in the case of discharging to prevent retriggering is shown in Figure 10. This circuit adds an inverter I6 and a PMOS transistor P2 on the basis of Fig. 9 . Actual working principle: By adding PMOS transistor P2 to detect the change of the output state to prevent the occurrence of repeated triggering. That is, it is ensured that a second trigger can only be performed after a transition from a transient state to a steady state is performed. Therefore, it is possible to avoid the circuit state error caused by the burr of the trigger signal, so that the circuit has a certain immunity to transient spikes and burrs.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than limit them. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent replacements to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and all of them should be included in the scope of the present invention. within the scope of the claims.

Claims (20)

1. A monostable circuit based on blocking control, characterized in that, the monostable circuit comprises: a first PMOS transistor (P1), a second PMOS transistor (P2), a first transmission gate (T1) and a second Transmission gate (T2), capacitor (N1) and first inverter (I1), second inverter (I2) and third inverter (I3); The source of the first PMOS transistor (P1) is connected to the power supply voltage, its drain is connected to the source of the second PMOS transistor (P2), and its gate is controlled by the input voltage; The gate of the second PMOS transistor (P2) is controlled by the signal at the output end of the second inverter (I2), and its drain is connected to the output end of the first transmission gate (T1), the first inverter The input terminal of the phase device (I1) is connected to one end of the capacitor (N1); The other end of the capacitor (N1) is grounded; The output end of the first inverter (I1) is connected to the input end of the second transmission gate (T2); the output end of the second transmission gate (T2) is connected to the second inverter (I2 ) is connected to the input; the output of the second inverter (I2) is connected to the input of the third inverter (I3); The output terminal of the third inverter (I3) is the output terminal (VOUT) of the monostable circuit, and this output terminal is feedback-connected to the input terminal of the first transmission gate (T1); The first transmission gate (T1) and the second transmission gate (T2) are respectively controlled by the input signals of the control terminals of the first transmission gate (T1) and the second transmission gate (T2), so that only one transmission gate conducts at the same time pass to achieve congestion control. 2. The monostable circuit based on blocking control according to claim 1, characterized in that, the capacitor (N1) is a MOS capacitor, the grid of the MOS capacitor is connected to the gate of the first transmission gate (T1) The output terminal, the input terminal of the first inverter (I1) and the drain of the second PMOS transistor (P2) are connected, and the source and drain of the MOS capacitor are connected and grounded. 3. The monostable circuit based on blocking control according to claim 1, characterized in that, a fourth inverter (I4) is also included in the monostable circuit based on blocking control, and the fourth inverter The output end of the phaser (I4) is connected with the input end of the second inverter (I2), and the input end of the fourth inverter (I4) is connected with the output of the second inverter (I2). end connected. 4. The monostable circuit based on blocking control according to claim 1, characterized in that, the second transmission gate (T2) adopts an NMOS structure, and the monostable circuit based on blocking control also includes one or A NOT gate and the fifth inverter (I5), one input end of the NOR gate is connected with the input end of the second inverter (I2), and the other input end of the NOR gate is connected with a clock signal (CLK), the output of the NOR gate is the first signal (NCLK1), which is connected to the input of the fifth inverter (I5), and the output of the fifth inverter (I5) is the second signal (CLK1), the second signal (CLK1) is used as the input signal of the control terminal of the second transmission gate (T2) to control the second transmission gate (T2). 5. The monostable circuit based on blocking control according to claim 1, characterized in that, the second transmission gate (T2) adopts a CMOS structure, and the monostable circuit based on blocking control also includes one or A NOT gate and the fifth inverter (I5), one input end of the NOR gate is connected with the input end of the second inverter (I2), and the other input end of the NOR gate is connected with a clock signal (CLK), the output of the NOR gate is the first signal (NCLK1), which is connected to the input of the fifth inverter (I5), and the output of the fifth inverter (I5) is the second signal (CLK1), the first signal (NCLK1) and the second signal (CLK1) are used as input signals of the control terminal of the second transmission gate (T2) to control the second transmission gate (T2). 6. The monostable circuit based on blocking control according to claim 1, characterized in that, the second transmission gate (T2) adopts a PMOS structure, and the monostable circuit based on blocking control also includes one or A NOT gate, one input end of the NOR gate is connected with the input end of the second inverter (I2), the other input end of the NOR gate is connected with a clock signal (CLK), the NOR gate The output of is the first signal (NCLK1), and the first signal (NCLK1) is used as the input signal of the control terminal of the second transmission gate (T2) to control the second transmission gate (T2). 7. The monostable circuit based on blocking control according to any one of claims 1, 4, 5 or 6, wherein the monostable circuit based on blocking control also includes a second NMOS transistor (N2) and a sixth inverter (I6), the input terminal of the sixth inverter (I6) is connected with the output terminal (VOUT) of the monostable circuit, and the sixth inverter (I6) ) is connected to the gate of the second NMOS transistor (N2), the source of the second NMOS transistor (N2) is grounded, and the drain of the second NMOS transistor (N2) is connected to the first The input terminals of the transmission gate (T1) are connected. 8. The monostable circuit based on blocking control according to any one of claims 1, 4, 5 or 6, characterized in that, the first transfer gate (T1) is a transfer gate of CMOS structure, the first The gate of the PMOS transistor of the transmission gate (T1) is a control terminal, and the control terminal is connected to the clock signal (CLK), and the gate of the NMOS transistor of the first transmission gate (T1) is another control terminal, and the control terminal is connected to the clock signal. The reverse signal (NCLK) of the signal (CLK); The second transmission gate (T2) is a transmission gate of CMOS structure, and the gate of the PMOS transistor of the second transmission gate (T2) is a control terminal, and the control terminal is connected to the reverse signal (NCLK) of the clock signal or the The first signal (NCLK1) of the output of the NOR gate, the gate of the NMOS transistor of the second transmission gate (T2) is another control terminal, and the control terminal is connected to the clock signal (CLK) or the inverter output second signal (CLK1); or The second transmission gate (T2) is a transmission gate of PMOS structure, and the control terminal of the second transmission gate (T2) is connected to the reverse signal (NCLK) of the clock signal or the first output of the NOR gate. a signal (NCLK1); or The second transmission gate (T2) is a transmission gate of NMOS structure, and the control terminal of the second transmission gate (T2) is connected to the clock signal (CLK) or the second signal (CLK1) output by the inverter. ). 9. according to the monostable circuit based on blocking control described in any one of claim 1,4,5 or 6, it is characterized in that, described first transmission gate (T1) is the transmission gate of PMOS structure, described The control terminal of the first transmission gate (T1) is connected to the clock signal (CLK); The second transmission gate (T2) is a transmission gate of CMOS structure, and the gate of the PMOS transistor of the second transmission gate (T2) is a control terminal, and the control terminal is connected to the reverse signal (NCLK) of the clock signal (CLK) or The first signal (NCLK1) of the output of the NOR gate, the gate of the NMOS transistor in the second transmission gate (T2) is another control terminal, and the control terminal is connected to the clock signal (CLK) or the inverted The second signal (CLK1) of the output of the device; or The second transmission gate (T2) is a transmission gate of PMOS structure, and the control terminal of the second transmission gate (T2) is connected to the reverse signal (NCLK) of the clock signal (CLK) or the first output of the NOT gate. a signal (NCLK1); or The second transmission gate (T2) is a transmission gate of NMOS structure, and the control terminal of the second transmission gate (T2) is connected to the clock signal (CLK) or the second signal (CLK1) of the output of the inverter. ). 10. according to the monostable circuit based on blocking control according to any one of claim 1,4,5 or 6, it is characterized in that, described first transfer gate (T1) is the transfer gate of NMOS structure, described The control terminal of the first transmission gate (T1) is connected to the reverse signal (NCLK) of the clock signal (CLK); The second transmission gate (T2) is a transmission gate of CMOS structure, and the gate of the PMOS transistor of the second transmission gate (T2) is a control terminal, and the control terminal is connected to the reverse signal (NCLK) of the clock signal or the The first signal (NCLK1) of the output of the NOR gate, the gate of the NMOS transistor of the second transmission gate (T2) is another control terminal, which is connected to the clock signal (CLK) or the output of the inverter the second signal (CLK1); or The second transmission gate (T2) is a transmission gate of PMOS structure, and the control terminal of the second transmission gate (T2) is connected to the reverse signal (NCLK) of the clock signal or the first output of the inverter. a signal (NCLK1); or The second transmission gate (T2) is a transmission gate of NMOS structure, and the control terminal of the second transmission gate (T2) is connected to the clock signal (CLK) or the second signal (CLK1) output by the inverter. ). 11. A monostable circuit based on blocking control, characterized in that the monostable circuit comprises: a first NMOS transistor (N1), a second NMOS transistor (N2), a first transmission gate (T1) and a second transmission gate (T2), a capacitor (P1) and first inverter (I1), second inverter (I2) and third inverter (I3); The source of the second NMOS transistor (N2) is grounded, its drain is connected to the source of the first NMOS transistor (N1), and its gate is controlled by an input voltage; The gate of the first NMOS transistor (N1) is controlled by the signal from the output terminal of the second inverter (I2), feedback controls the discharge process of the second NMOS transistor (N2), and its drain is connected to The output terminal of the first transmission gate (T1), the input terminal of the first inverter (I1) and one end of the capacitor (P1) are connected; The other end of the capacitor (P1) is connected to a power supply voltage; The output end of the first inverter (I1) is connected to the input end of the second transmission gate (T2); The output end of the second transmission gate (T2) is connected to the input end of the second inverter (I2); The output end of the second inverter (I2) is connected to the input end of the third inverter (I3); The output terminal of the third inverter (I3) is the output terminal (VOUT) of the monostable circuit, and this output signal is fed back to the input terminal of the first transmission gate (T1); The first transmission gate (T1) and the second transmission gate (T2) are respectively controlled by the input signals of the control terminals of the first transmission gate (T1) and the second transmission gate (T2), so that only one transmission gate conducts at the same time pass to achieve congestion control. 12. The monostable circuit based on blocking control according to claim 11, characterized in that, the capacitor (P1) is a MOS capacitor, and the gate of the MOS capacitor is connected to the output of the first transmission gate (T1) Terminal, the input terminal of the first inverter (I1) and the drain of the first NMOS transistor (N1), the source and drain of the MOS capacitor are connected and connected to the power supply voltage. 13. The monostable circuit based on blocking control according to claim 11, characterized in that, the monostable circuit based on blocking control also includes a 4th inverter (I4), and the 4th inverter The output end of the phaser (I4) is connected with the input end of the second inverter (I2), and the input end of the 4th inverter (I4) is connected with the output of the second inverter (I2). end connected. 14. The monostable circuit based on blocking control according to claim 11, characterized in that, the second transmission gate (T2) adopts an NMOS structure, and the monostable circuit based on blocking control also includes one or A NOT gate and a fifth inverter (I5), one input of the NOR gate is connected to the output of the second inverter (I2), and the other input of the NOR gate is connected to the clock signal (CLK), the output of the NOR gate is the first signal (NCLK1), this signal is connected with the input terminal of the fifth inverter (I5), and the output clock signal of the fifth inverter (I5) is (CLK1), the second signal (CLK1) is used as the input signal of the control terminal of the second transmission gate (T2) to control the second transmission gate (T2). 15. The monostable circuit based on blocking control according to claim 11, characterized in that, the second transmission gate (T2) adopts a CMOS structure, and the monostable circuit based on blocking control also includes one or A NOT gate and the fifth inverter (I5), one input end of the NOR gate is connected with the output end of the second inverter (I2), and the other input end of the NOR gate is connected with a clock signal (CLK), the output of the NOR gate is the first signal (NCLK1), which is connected to the input of the fifth inverter (I5), and the output of the fifth inverter (I5) is the first signal (CLK1), the first signal (NCLK1) and the second signal (CLK1) are used as input signals of the control terminal of the second transmission gate (T2) to control the second transmission gate (T2). 16. The monostable circuit based on blocking control according to claim 11, characterized in that, the second transmission gate (T2) adopts a PMOS structure, and the monostable circuit based on blocking control also includes one or A NOT gate, one input end of the NOR gate is connected with the output end of the second inverter (I2), the other input end of the NOR gate is connected with a clock signal (CLK), the NOR gate The output of is the first signal (NCLK1), and the first signal (NCLK1) is used as the input signal of the control terminal of the second transmission gate (T2) to control the second transmission gate (T2). 17. The monostable circuit based on blocking control according to any one of claims 11, 14, 15 or 16, wherein the monostable circuit based on blocking control also includes a PMOS transistor (P2 ) and a sixth inverter (I6), the input terminal of the sixth inverter (I6) is connected with the output terminal (VOUT) of the monostable circuit, the sixth inverter (I6) The output terminal is connected to the gate of the PMOS transistor (P2), the source of the PMOS transistor (P2) is connected to the power supply voltage, and the drain of the PMOS transistor (P2) is connected to the first transmission gate (T1). connected to the input. 18. The monostable circuit based on blocking control according to any one of claims 11, 14, 15 or 16, characterized in that, the first transfer gate (T1) is a transfer gate of CMOS structure, the first The gate of the PMOS transistor of the transmission gate (T1) is a control terminal, and the control terminal is connected to the clock signal (CLK), and the gate of the NMOS transistor of the first transmission gate (T1) is another control terminal, and the control terminal is connected to the clock signal. The reverse signal of the signal (NCLK); The second transmission gate (T2) is a transmission gate of a CMOS structure, and the gate of the PMOS transistor in the second transmission gate (T2) is a control terminal, which is connected to the reverse signal (NCLK) of the clock signal. The first signal (NCLK1) of the output of the NOR gate, the gate of the NMOS transistor of the second transmission gate (T2) is another control terminal, and the control terminal is connected to the clock signal (CLK) or the inverter output second signal (CLK1); or The second transmission gate (T2) is a transmission gate of PMOS structure, and the control terminal in the second transmission gate (T2) is connected to the reverse signal (NCLK) of the clock signal or the output of the NOR gate the first signal (NCLK1); or The second transmission gate (T2) is a transmission gate of NMOS structure, and the control terminal in the second transmission gate (T2) is connected to the clock signal (CLK) or the second signal ( CLK1). 19. The monostable circuit based on blocking control according to any one of claims 11, 14, 15 or 16, characterized in that, the first transmission gate (T1) is a transmission gate of PMOS structure, and the The control terminal of the first transmission gate (T1) is connected to the clock signal (CLK); The second transmission gate (T2) is a transmission gate of CMOS structure, and the gate of the PMOS transistor in the second transmission gate (T2) is a control terminal, and the control terminal is connected to the reverse signal (NCLK) of the clock signal (CLK) Or the first signal (NCLK1) of the output of the NOR gate, the gate of the NMOS transistor in the second transmission gate (T2) is another control terminal, and the control terminal is connected to the clock signal (CLK) or the inverter the output of the second signal (CLK1); or The second transmission gate (T2) is a transmission gate of PMOS structure, and the control terminal in the second transmission gate (T2) is connected to the reverse signal (NCLK) of the clock signal (CLK) or the output of the NOT gate the first signal (NCLK1); or The second transmission gate (T2) is a transmission gate of NMOS structure, and the control terminal in the second transmission gate (T2) is connected to the clock signal (CLK) or the second signal ( CLK1). 20. The monostable circuit based on blocking control according to any one of claims 11, 14, 15 or 16, characterized in that, the first transfer gate (T1) is a transfer gate of NMOS structure, the the inverse signal (NCLK) of the control termination clock signal in the first transmission gate (T1); The second transmission gate (T2) is a transmission gate of CMOS structure, and the gate of the PMOS transistor in the second transmission gate (T2) is a control terminal, and the control terminal is connected to the reverse signal (NCLK) of the clock signal or the described The first signal (NCLK1) of the output of the inverter, the gate of the NMOS transistor in the second transmission gate (T2) is another control terminal, and the control terminal is connected to the clock signal (CLK) or the output of the inverter the second signal (CLK1); or The second transmission gate (T2) is a transmission gate of PMOS structure, and the control terminal in the second transmission gate (T2) is connected to the reverse signal (NCLK) of the clock signal or the output of the inverter the first signal (NCLK1); or The second transmission gate (T2) is a transmission gate of NMOS structure, and the control terminal in the second transmission gate (T2) is connected to the clock signal (CLK) or the second signal ( CLK1).

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