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CN101960578B - 倒装芯片安装方法和倒装芯片安装装置及其所使用的工具保护膜 - Google Patents

倒装芯片安装方法和倒装芯片安装装置及其所使用的工具保护膜 Download PDF

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Publication number
CN101960578B
CN101960578B CN2009801083511A CN200980108351A CN101960578B CN 101960578 B CN101960578 B CN 101960578B CN 2009801083511 A CN2009801083511 A CN 2009801083511A CN 200980108351 A CN200980108351 A CN 200980108351A CN 101960578 B CN101960578 B CN 101960578B
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Prior art keywords
film
semiconductor chip
pressurized
tool
flip
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CN2009801083511A
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CN101960578A (zh
Inventor
户村善广
熊泽谦太郎
樋口贵之
中村浩二郎
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

一种倒装芯片安装装置，其特征是，在工具保护膜(10)的加压膜(10b)的一侧具有屏蔽膜(18)，在经由工具保护膜(10)对半导体芯片(1)加热加压时，利用膜固定夹具(9)使加压膜(10b)脱离，并利用加压加热工具(11)使加压膜膨胀，从而使加压膜与从半导体芯片(1)的周边溢出的绝缘性树脂膜(5)抵接，对绝缘性树脂膜(5)施加外压力并使其固化。

Description

倒装芯片安装方法和倒装芯片安装装置及其所使用的工具保护膜
技术领域
本发明涉及倒装芯片安装方法和倒装芯片安装装置。
背景技术
近年来，根据电子设备的小型薄型化的要求，要求一种能将裸露(bare)的半导体芯片直接安装(裸芯片安装)于配线基板上的半导体装置。特别地，要求一种将半导体芯片的电路面翻过来以朝向配线基板而安装(倒装芯片安装)的半导体装置。
以往，通过倒装芯片连接将具有金属凸点电极等的内部连接端子的半导体芯片装设于配线基板，来构成倒装芯片类型的半导体装置。
在配线基板的两面形成有配线图案，通过形成于配线基板的通孔(贯穿孔)将两面的配线图案电连接。在配线图案的一方连接有半导体元件的内部连接端子，在另一方连接有焊球等外部连接端子。在半导体元件与配线基板之间、即在将半导体元件的内部连接端子连接于配线图案的区域中，填充有由环氧树脂等构成的热固化树脂，从而保护内部连接端子。
如图14(a)所示，在将配线基板101设于基台100之上，并将半导体芯片102安装于该配线基板101的情况下，将各相异性导电粘接膜103粘贴于半导体芯片102上，并在倒装芯片的状态下对半导体芯片102定位设置。在热压接头部104的内侧，设有作为压接部105的橡胶硬度在40以上80以下的橡胶。
接着，如图14(b)所示，利用热压接头部104经由压接部105对半导体芯片102的顶部和其侧部加热加压，从而能以规定的压力差使各相异性导电粘接膜103加压固化。也就是说，能对配线基板101与半导体芯片102的连接部分施加足够的压力，也能对半导体芯片102周围的倒角部加压以不产生空心。
专利文献1：日本专利特开2005-32952号公报
发明的公开
发明所要解决的技术问题
然而，为了利用热压接头部104经由合成橡胶的压接部105对半导体芯片102加热加压，由于来自热压接头部104的热传导较差而导致温度上升需要较长的时间，因此，对于半导体芯片102与配线基板101之间的各相异性导电粘接膜103的固化需要更长的时间，从而使生产研制周期变长。
另一方面，为了预先提高压接部105的合成橡胶的温度，就必须将热压接头部104维持在温度非常高的状态。由于上述合成橡胶的耐热性、温度偏差导致厚度出现偏差，各相异性导电粘接膜103的固化变得不均匀。
另外，不易表面平行地对热压接头部104和半导体芯片102加压，而且利用负载来控制半导体芯片102的凸点高度均一变得困难。而且，在半导体芯片102为多凸点的情况下，通过上述负载的控制来控制凸点高度变得更加困难。
本发明的目的在于提供一种研制周期短、生产率高的倒装芯片安装方法和倒装芯片安装装置，该倒装芯片安装方法和倒装芯片安装装置能减小半导体芯片的凸点高度偏差，对半导体芯片与配线基板之间的底部填料树脂施加外压并使其在短时间内固化。
解决技术问题所采用的技术方案
本发明的技术方案1所记载的倒装芯片安装方法的特征是，在将热固化性的底部填料树脂设于半导体芯片与配线基板之间、并将半导体芯片倒装芯片安装于配线基板时，对将热固化性的底部填料树脂夹持于上述配线基板与上述半导体芯片之间而被定位设置的上述半导体芯片，从至少由基底膜和加压膜的双层膜结构构成的工具保护膜的上方加压加热，从而使上述半导体芯片下方的上述底部填料树脂固化，并使上述加压膜从除了上述半导体芯片正上方的加压部以外的上述工具保护膜分离，而且上述分离后的加压膜朝上述半导体芯片周围的上述底部填料树脂隆起并与其抵接，且对上述底部填料树脂加压加热而使其固化，从而将上述半导体芯片固定于上述配线基板。
本发明的技术方案2所记载的倒装芯片安装方法是技术方案1所记载的倒装芯片安装方法，其特征是，上述工具保护膜是将固体、液体、气体中的至少一种以上密封于基底膜与加压膜之间而形成的。固体为发泡体材料，例如，最好是将醚类树脂、脂类聚氨酯树脂、热膨胀性胶囊与粘接剂(丙烯酸类树脂、橡胶类树脂、硅酮粘接剂)调合的混合树脂、例如热剥离薄膜(Revalpha)这样的材料。液体为挥发性膨胀材料，例如，最好是乙醇、IPA这样的低沸点的溶剂。气体最好是例如空气(空气、干燥空气)、氮气等惰性气体、氢气等，加热时容易膨胀的气体。
本发明的技术方案3所记载的倒装芯片安装方法的特征是，在将热固化性的底部填料树脂设于半导体芯片与配线基板之间、并将半导体芯片倒装芯片安装于配线基板时，对将热固化性的底部填料树脂夹持于上述配线基板与上述半导体芯片之间而被定位设置的上述半导体芯片，从由基底膜、加压膜和被粘贴于上述加压膜的屏蔽膜的三层膜结构构成的工具保护膜的上方加压加热，从而使上述半导体芯片下方的所述底部填料树脂固化，并使上述加压膜从除了上述半导体芯片正上方的加压部以外的上述工具保护膜分离，上述分离后的加压膜隔着上述屏蔽膜朝上述半导体芯片周围的上述底部填料树脂隆起并与其抵接，且对上述底部填料树脂加压加热并使其固化，从而将上述半导体芯片固定于上述配线基板，并使上述屏蔽膜粘接于上述半导体芯片的一侧。
本发明的技术方案4所记载的倒装芯片安装方法是技术方案3所记载的倒装芯片安装方法，其特征是，上述工具保护膜是将固体、液体、气体中的至少一种以上密封于基底膜与加压膜之间而形成的。
本发明的技术方案5所记载的工具保护膜的特征是，构成为至少由基底膜和加压膜构成的双层膜结构，且在加热时，未被加压部分的上述加压膜从上述基底膜分离并隆起。
本发明的技术方案6所记载的工具保护膜是技术方案5所记载的工具保护膜，其特征是，该工具保护膜是将固体、液体、气体中的至少一种以上密封于上述基底膜与加压膜之间形成的。
本发明的技术方案7所记载的工具保护膜的特征是，构成为至少由基底膜、加压膜和粘贴于上述加压膜的屏蔽膜构成的三层膜结构，且在加热时，未被加压部分的上述加压膜从上述基底膜分离并隆起。
本发明的技术方案8所记载的工具保护膜是技术方案7所记载的工具保护膜，其特征是，该工具保护膜是将固体、液体、气体中的至少一种以上密封于上述基底膜与加压膜之间形成的。
本发明的技术方案9所记载的倒装芯片安装装置是将热固化性的底部填料树脂设于半导体芯片与配线基板之间、并将半导体芯片倒装芯片安装于配线基板的倒装芯片安装装置，其特征是，包括：
膜固定夹具，该膜固定夹具保持至少由基底膜和加压膜构成的双层膜结构或至少由基底膜、加压膜和粘贴于上述加压膜的屏蔽膜构成的三层膜结构的工具保护膜，并把将热固化性的底部填料树脂夹持于上述配线基板与上述半导体芯片之间而被定位设置的上述半导体芯片及其周围盖住；
加压加热工具，该加压加热工具形成有突部，该突部对上述半导体芯片加热且朝上述配线基板按压，并将上述膜固定夹具的内周部与上述半导体芯片的外周部分之间的上述工具保护膜朝上述热固化性的底部填料树脂的外周部分按压。
发明效果
根据该结构，经由双层膜结构或三层膜结构的工具保护膜对半导体芯片加压加热，从而使上述半导体芯片下方的上述底部填料树脂固化，并使上述加压膜从除了半导体芯片正上方的加压部以外的上述工具保护膜分离，上述分离后的加压膜朝上述半导体芯片周围的上述底部填料树脂隆起并与其抵接，对上述底部填料树脂加压加热并使其固化，因此，能制造研制周期短、生产率高、可靠性高的半导体装置。
附图说明
图1是本发明的倒装芯片安装方法的实施方式1的前工序图。
图2A是上述实施方式的后工序的最初的剖视图。
图2B是上述实施方式的后工序的最初的局部剖切俯视图。
图3是上述实施方式的后工序的工序图。
图4是本发明的倒装芯片安装方法的实施方式2的后工序图。
图5是本发明的倒装芯片安装方法的实施方式3中所使用的工具保护膜的俯视图和剖视图。
图6是上述实施方式的后工序的工序图。
图7是本发明的倒装芯片安装方法的实施方式4中所使用的工具保护膜的剖视图。
图8是上述实施方式的后工序的工序图。
图9是本发明的倒装芯片安装方法的实施方式5中所使用的工具保护膜的剖视图。
图10是上述实施方式中所使用的工具保护膜的俯视图及其侧视图。
图11A是上述实施方式的后工序的最初的剖视图。
图11B是上述实施方式的后工序的最初的俯视图。
图12A是上述实施方式的后工序的工序图。
图12B是上述实施方式的后工序的工序图。
图13是上述实施方式的后工序的工序图。
图14是现有例的安装方法的工序图。
具体实施方式
以下，根据具体的各实施方式来说明本发明的倒装芯片安装方法。
(实施方式1)
图1、图2A、图2B及图3表示本发明的实施方式1。
该实施方式1的倒装芯片安装方法是使用工具保护膜的安装方法，由图1(a)～图1(c)所示的将半导体芯片定位于配线基板的前工序和图2A、图2B、图3(a)～图3(e)所示的继前工序之后实施的、通过工具保护膜来按压半导体芯片的后工序构成。
如图1(a)所示，在半导体芯片1的电极焊盘3上设有凸点2。凸点2可通过众所周知的线焊法(wire bonding)来形成钉头凸点、楔型凸点(日文：引きちぎりバンプ)，也可通过镀覆法、印刷法来形成凸点。凸点2主要由金、铜、钯、镍、锡、铝、焊锡等的至少一种材料形成。另外，也可朝用于形成凸点2的金属线中添加微量元素。将该情况下的凸点高度设定为大致50μm。
配线基板6是环氧玻璃基板(也可为芳族聚酰胺基板、硅基板、硅中介层(silicon interposer))，厚度为0.2～0.4mm，端子电极为铜(也可镍+Au镀覆)，半导体芯片1的厚度为0.15～0.2mm。绝缘性树脂膜5的树脂使用环氧树脂、在180℃固化的材料。配线基板6的端子电极4上粘贴有作为底部填料树脂的绝缘性树脂膜5，该绝缘性树脂膜5根据需要被切成比半导体芯片1稍大的尺寸。
接着，利用半导体芯片装设定位装置7使用工具来吸附半导体芯片1，如图1(b)所示，通过识别标记等将半导体芯片1定位于配线基板6上的端子电极4的期望的位置，并将半导体芯片1的凸点2装设成与各相对应的端子电极4重叠。在此时刻，凸点2处于刺入绝缘性树脂膜5的状态。一部分的凸点2贯穿绝缘性树脂膜5，并与端子电极4抵接而变形。定位负载为每一个凸点10g左右。也可利用内置的加热器来加热半导体芯片装设定位装置7，但不能使树脂发生100％的固化。半导体芯片装设定位装置7在装设好半导体芯片1后脱离，形成图1(c)所示的加工品。
在图1(a)中，可事先以50℃左右的温度来加热配线基板6，也可加热粘贴装置的工具(未图示)，从而将绝缘性树脂膜5粘接贴附于配线基板6上。粘贴负载为5～10kgf/cm2。该绝缘性树脂膜5的厚度为50μm。若绝缘性树脂膜5与保护用分离膜(未图示)成为双层结构，则将其剥下。绝缘性树脂膜5的绝缘性树脂例如能使用环氧树脂、酚醛树脂、聚酰亚胺，此外，能使用绝缘性热塑性树脂中的聚苯硫醚(PPS)、聚碳酸酯、改性聚苯醚(PPO)，或者，将上述绝缘性热固性树脂与绝缘性热塑性树脂混合的材料。使用无机填料量为50重量百分比的材料。根据半导体芯片1和配线基板6的热膨胀、翘曲所产生的应力来决定填料量。此外，也能通过吸湿再流焊试验、高湿偏置试验(high humidity bias test)等所得出的耐湿密接性来决定可靠性。另外，绝缘性树脂膜5最好具有回流焊耐热性(265℃10秒时间)。
在图2A中，将图1(c)所示的加工品搬运至加压加热工作台8，并使配线基板6的背面吸附于加压加热工作台8。此外，将由双层膜结构构成的工具保护膜10设置于半导体芯片1的上方，接着，将加压加热工具11设置于该工具保护膜10的上方。符号9是保持工具保护膜10的膜固定夹具。
工具保护膜10的加压加热工具11侧的基底膜10a最好为具有耐热性的膜。基底膜10a的材质例如最好为聚酰亚胺、聚苯硫醚、氟树脂等的耐热性膜。基底膜10a的厚度为5～10μm左右。工具保护膜10的半导体芯片1侧的加压膜10b最好也是具有耐热性(NCF固化温度)的膜。加压膜10b的材质例如为聚酰亚胺、聚苯硫醚、氟树脂等。加压膜10b的厚度为5～10μm左右。
在基底膜10a与加压膜10b之间，密封有作为液体的溶剂12。挥发性膨胀材料中的例如乙醇、IPA这样的低沸点的溶剂容易膨胀，因此，最适于用作溶剂12。
加压加热工具11形成有突部25，该突部25将半导体芯片1朝配线基板6按压并进行加热，并将膜固定夹具9的内周部与半导体芯片1的外周部分之间的工具保护膜10朝上述热固性的绝缘性树脂膜5的外周部分按压，加压加热工具11经由工具保护膜10将热传递至半导体芯片1，接着，为了达到绝缘性树脂膜5的固化温度180℃，将温度设定为210℃。本实施方式中使用了恒温类型的加热工具，但也可使用陶瓷高速升温类型的加热工具。图2B是从加压加热工具11侧观察的俯视图。使用膜固定夹具9将工具保护膜10夹持固定。
如上所述，沿加压加热工具11的外周绕环状形成突部25，因此，能将加压加热工具11的热更快地传递到工具保护膜10。
接着，在图3(a)中，在使用膜固定夹具9使工具保护膜10下降以使其与半导体芯片1接触的同时，利用加压加热工具11将工具保护膜10压紧夹持于半导体芯片1，并对半导体芯片1加压加热。
在图3(b)中，通过使用加压加热工具11来增加负载，使凸点2全部戳破绝缘性树脂膜5，并与配线基板6的端子电极4接触而变形。被膜固定夹具9保持且被压紧于半导体芯片1的工具保护膜10的位于膜固定夹具9的内侧与半导体芯片1的外周部之间的部分，倾斜至配线基板6的附近。
在图3(c)中，工具保护膜10中、基底膜10a与加压膜10b之间的溶剂12被来自加压加热工具11的热加热而气化膨胀。
在图3(d)中，基底膜10a与加压膜10b之间的溶剂12进一步膨胀。而且，使用加压加热工具11来使半导体芯片1的凸点2的高度接近期望的值。加压膜10b在被加压加热工具11、膜固定夹具9与配线基板6围起的空间内鼓起，施加压力从侧面方向按压从半导体芯片1的一端溢出的绝缘性树脂膜5的倒角部19，且利用加压膜10b的外压来抑制对半导体芯片1下方的绝缘性树脂膜5加压加热的状态下的内压，使绝缘性树脂膜5固化。
此时的变形负载为每一个凸点50g左右。通过凸点2的尺寸能控制负载，但在该情况下，凸点高度为25μmt。另外，也可根据需要，加热、或冷却加热加压工作台8，从而控制绝缘性树脂膜5中的内压，来抑制空心的产生。
在图3(e)中，表示了绝缘性树脂膜5在加压膜10b的外压下固化后，解除加压加热工具11而获得的倒装芯片安装件。
这样，通过使用薄的工具保护膜10来加压加热，能容易地将热传递至半导体芯片1和周围，也能使绝缘性树脂膜5固化，并能通过薄的工具保护膜10，使加压加热工具11对半导体芯片1的加压平行均匀地作用负载于半导体芯片1，从而能在短时间内固化。此外，能通过使溶剂12气化膨胀，来将加压膜10b压紧于绝缘性树脂膜，并施加外压来使绝缘性树脂膜固化。
另外，工具保护膜10是薄的膜，因此，与橡胶不同能柔软地弯曲，能将半导体芯片1的周围的绝缘性树脂膜5的倒角部19变小，从而能抑制空心的产生。
也可使用各向异性导电膜(ACF)来代替绝缘性树脂膜5，此外，通过使用对镍粉进行完镀金的材料来作为包含于各向异性导电膜中的导电粒子(未图示)，能使端子电极4与凸点2之间的连接电阻值降低，从而能获得良好的连接可靠性。此外，导电粒子也可使用对树脂粒进行完镀镍、镀金的粒子。此外，通过使用焊锡等的微粒子，导电粒子能从端子电极4与凸点2之间的接触状态的连接变成合金状态的连接，从而能进一步提高连接可靠性。
配线基板6为单面、双面或多层板，与半导体芯片1的凸点2对应的端子电极4形成于表面。材质也可为陶瓷基板、树脂基板、树脂软膜(聚酰亚胺软膜等)、硅的基板。
可在环氧树脂的B阶段(半固体)状态下粘贴膜状的树脂而形成绝缘性树脂膜5。也可通过涂布或印刷糊状的材料而形成绝缘性树脂膜5。另外，绝缘性树脂膜5也可包含无机的(二氧化硅)填料。通过控制填料量，能使绝缘性树脂膜5的粘贴性、热膨胀性、弹性模量变化，并能获得量产性和可靠性。本实施方式中将填料量设定为50重量百分比。
溶剂12不仅仅是液态，也可与粘接剂混合而形成。
(实施方式2)
图1和图4表示本发明实施方式2。
在实施方式1的倒装芯片安装方法中，图2A中，在工具保护膜10的基底膜10a与加压膜10b之间密封有液态的溶剂12、或与粘接剂混合而形成的溶剂12，但在该实施方式2的工具保护膜10的基底膜10a与加压膜10b之间，如图4(a)所示，使用发泡体13来代替溶剂12，在这点上与实施方式1不同。其他部分与实施方式1相同。
继图1之后，在图4(a)中，将图1(c)所示的加工品搬运至加压加热工作台8，并将配线基板背面吸附于加压加热工作台8。将被膜固定夹具9保持的工具保护膜10配置于半导体芯片1的上方。
工具保护膜10采用基底膜10a与加压膜10b的双层膜结构，在基底膜10a与加压膜10b之间，形成有固体的发泡体13。发泡体13例如最好使用将醚类树脂、脂类聚氨酯树脂、热膨胀性胶囊与粘接剂(丙烯类树脂、橡胶类树脂、硅酮粘接剂)调合的混合树脂、例如热剥离薄膜(Revalpha)这样的材料。
发泡体13也可含有下述粒子，该粒子具有通过因加热处理而产生的热膨胀性微粒子的膨胀或发泡而增加表面粗糙度从而减少与粘附体的粘接面积的效果、由于表面膨胀而在粘接界面上产生剥离应力的效果，该粒子对粘附体的粘接力能下降或消失。热膨胀性胶囊是将发泡剂内置于通过使屏蔽性的热塑性树脂共聚合而形成的外壳的微胶囊，通过加热使外壳软化并通过发泡剂的气化压力来膨胀。例如，能举出吴羽(日文：クレハ)株式会社制的微球体等。参照日本专利特许第2898480号公报等。也可以是使在高温下成为气态的挥发性膨胀剂微胶囊化后形成的热膨胀性微胶囊。
发泡体13最好是在常温下具有粘接力而在低温下能膨胀剥离的热剥离膜(具体而言，如日东电工株式会社制的热剥离薄膜(Thermal ReleaseTape REVALPHA)等)。发泡体可以是液体，也可以是半固体、固体。
发泡体13可与粘接剂调合，从而紧贴于基底膜10a和加压膜10b，为使加压膜10b的一侧容易剥离，也可在基底膜10a与加压膜10b之间形成进入有气体的封闭空间。发泡体13也可与丙烯酸类、橡胶类、硅酮粘接剂混合。
加压加热工具11经由工具保护膜10将热传递至半导体芯片1，此外，为了达到绝缘性树脂膜5的固化温度180℃，将温度设定为210℃。
接着，在图4(b)中，使用膜固定夹具9将工具保护膜10夹住并下降以使其与半导体芯片1抵接，同时利用加压加热工具11将工具保护膜10压紧夹持于半导体芯片1，并对半导体芯片1加压加热。
通过使用加压加热工具11来作用负载，使凸点2全部戳破绝缘性树脂膜5，并与配线基板6的端子电极4接触而变形。使用膜固定夹具9将工具保护膜10配置成倾斜至配线基板6附近。此时，如图4(a)所示，加压加热工具11的外周也可朝半导体芯片1周边的倒角部19即绝缘性树脂膜5的侧面倾斜。通过设置倾斜部26，能将加压加热工具11的热更快地传递到工具保护膜10。
通过使加压加热工具11靠近或接触工具保护膜10，并对其加热，使发泡体13被来自加压加热工具11的热加热而发泡膨胀。
在图4(c)中，通过使加压加热工具11进一步下降，并对工具保护膜10加热，发泡体13进一步膨胀。使用膜固定夹具9来夹持固定工具保护膜10。而且，使用加压加热工具11来使半导体芯片1的凸点2的高度接近期望的值。通过使发泡体13在被加压加热工具11、膜固定夹具9与配线基板6围起的空间内膨胀来使加压膜10b隆起，从侧面方向对从半导体芯片1的一端溢出的成为倒角部19的绝缘性树脂膜5施加压力，使绝缘性树脂膜5固化，并通过加压膜10b的外压来抑制半导体芯片1下方的绝缘性树脂膜5被加压加热时的内压，使绝缘性树脂膜5固化。凸点2的变形负载为每一个凸点50g左右。通过凸点2的尺寸能控制负载，但在该情况下，考虑到可靠性，将凸点高度设为25μmt。另外，也可根据需要，加热、或冷却加热加压工作台8，控制绝缘性树脂膜5的内压，从而抑制空心的产生。
在图4(d)中，表示了在利用加压膜10b的外压使绝缘性树脂膜5固化后，将加压加热工具11解除而获得的倒装芯片安装件。
这样，通过使用薄的工具保护膜10来加压加热，能将热容易地传导至半导体芯片1和周边，也能使绝缘性树脂膜5固化，利用薄的工具保护膜10，能使用加压加热工具11加压，从而对半导体芯片1平行均匀地作用负载。绝缘性树脂膜5能在短时间内固化。此外，通过使发泡体13气化膨胀，来将加压膜10b压紧于绝缘性树脂膜5并施加外压，从而使绝缘性树脂膜5固化。藉此，由于工具保护膜10是薄的膜，因此，与橡胶不同，能柔软地弯曲，并能减小半导体芯片1的周边的绝缘性树脂膜5的倒角部19，从而能抑制空心的产生。
(实施方式3)
图1、图5及图6表示本发明实施方式3。
在实施方式1的倒装芯片安装方法中，在图2A中，在工具保护膜10的基底膜10a与加压膜10b之间密封有液态的溶剂12、或与粘接剂混合而形成的溶剂12，但如图5(a)、图5(b)所示，在该实施方式3的工具保护膜10的基底膜10a与加压膜10b之间，形成有供取代溶剂12的气体充填的封闭空间14，在这点上，实施方式3的工具保护膜10与实施方式1的工具保护膜10不同。其它部分与实施方式1相同。
形成工具保护膜10的封闭空间14的气体只要是一般的空气、干燥空气、氮气等惰性气体、氢气等在加热时容易膨胀的气体即可。基底膜10a和加压膜10b的长边侧能通过在加工温度以上的热而产生的层压热粘接、利用耐热性粘接剂等而闭合，只要在加热时能维持袋状态即可。
在图6(a)中，将图1(c)所示的加工品搬运至加压加热工作台8，并将配线基板背面吸附于加压加热工作台8。将被膜固定夹具9保持的工具保护膜10配置于半导体芯片1的上方。此外，将加压加热工具11设置于该工具保护膜10的上方。
在图6(b)中，使用膜固定夹具9将工具保护膜10夹住并下降以使其与半导体芯片1抵接，同时利用加压加热工具11将工具保护膜10压紧夹持于半导体芯片1，并对半导体芯片1加压加热。夹在工具保护膜10的基底膜10a与加压膜10b间的封闭空间14被加压加热工具11挤压，并在半导体芯片1的周边形成隆起。
通过使用加压加热工具11来作用负载，使凸点2全部戳破绝缘性树脂膜5，并与配线基板6的端子电极4接触而变形。使用膜固定夹具9将工具保护膜10配置成倾斜至配线基板6附近。
此时，如图6(b)所示，加压加热工具11的外周也可朝半导体芯片1周边的倒角部19即绝缘性树脂膜5侧倾斜。通过设置倾斜部26，能将加压加热工具11的热更快地传递到工具保护膜10。
通过使加压加热工具11靠近或接触工具保护膜10，并对其加热，封闭空间14被来自加压加热工具11的热加热而膨胀。
在图6(c)中，通过使加压加热工具11进一步下降，并对工具保护膜10加热，使封闭空间14进一步热膨胀。利用膜固定夹具9来夹持固定工具保护膜10，且利用加压加热工具11来使半导体芯片1的凸点2的高度接近期望的值。
通过使封闭空间14在被加压加热工具11、膜固定夹具9与配线基板6围起的空间内膨胀来隆起加压膜10b，从侧面方向对从半导体芯片1的一端溢出的成为倒角部19的绝缘性树脂膜5施加压力来使绝缘性树脂膜5固化，此外，通过加压膜10b的外压来抑制半导体芯片1下方的绝缘性树脂膜5被加压加热时的内压，使绝缘性树脂膜5固化。凸点2的变形负载为每一个凸点50g左右。通过凸点2的尺寸能控制负载，但在该情况下，考虑到可靠性，将凸点高度设为25μmt。另外，也可根据需要，加热、或冷却加热加压工作台8，控制绝缘性树脂膜5的内压，从而抑制空心的产生。
图6(d)是通过加压膜10b的外压使绝缘性树脂膜5固化后，将加热加压工具11解除而获得的倒装芯片安装件。
这样，能通过使用薄的工具保护膜10来加压加热，从而将热容易地传导至半导体芯片1和周边，也能使绝缘性树脂膜5固化，利用薄的工具保护膜10，能使用加压加热工具11加压，从而对半导体芯片1从上方平行均匀地作用负载。而且，能在短时间内使绝缘性树脂膜5固化。此外，通过使封闭空间14气化膨胀隆起，将加压膜10b压紧于绝缘性树脂膜5，并施加外压，使绝缘性树脂膜5固化。藉此，由于工具保护膜10是薄的膜，因此，与橡胶不同，能柔软地弯曲，并能减小半导体芯片1的周边的绝缘性树脂膜5的倒角部19，从而能抑制空心的产生。
(实施方式4)
图1、图7及图8表示本发明实施方式4。
在实施方式1的倒装芯片安装方法中，如图2A所示，在工具保护膜10的基底膜10a与加压膜10b之间密封有液态的溶剂12、或与粘接剂混合而形成的溶剂12，但如图7(a)所示，在该实施方式4的工具保护膜10的基底膜10a与加压膜10b之间，形成有UV固化型粘接剂15来代替溶剂12。将阻挡UV的遮光性的膜用于基底膜10a，工具保护膜10采用仅将使用部分从导向件露出的结构。
在图7(b)中，将遮光罩16配置成UV无法从与半导体芯片1的背面接触的加压膜10b侧射入大致与大致半导体芯片1的背面接触的部分，在该状态下，将UV光17照射到加压膜10b。藉此，使UV固化型粘接剂15局部固化，使该部分的粘接力下降，从而能容易地将加压膜10b从基底膜10a剥离。
在图7(c)中，使与膜固定夹具9的加压膜10b侧抵接的辊子27朝内侧旋转，搓起加压膜10b，从而将加压膜10b部分地从基底膜10a剥离，并使膜朝向工具保护膜的中央部松弛。为了容易地剥离UV固化型粘接剂，加压膜10b最好使用光透过性的膜。也可选定、控制UV固化型粘接剂的粘接剂厚度、粘接力，以通过膜固定夹具的膜剥离动作容易地形成封闭空间。
在图8(a)中，将图1(c)所示的加工品搬运至加压加热工作台8，并将配线基板背面吸附于加压加热工作台8。将图7(c)所示的剥离UV固化型粘接剂15并形成有封闭空间14的工具保护膜10设置于半导体芯片1的上方，此外，将加压加热工具11设置于该工具保护膜10的上方。
在图8(b)中，使用膜固定夹具9将工具保护膜10夹住并下降以使其与半导体芯片1抵接，同时利用加压加热工具11将工具保护膜10压紧夹持于半导体芯片1，并对半导体芯片1加压加热。加压膜10b的松弛在半导体芯片1的周边形成隆起。通过使用加压加热工具11来作用负载，使凸点2全部戳破绝缘性树脂膜5，与配线基板6的端子电极4接触并变形。
使用膜固定夹具9将工具保护膜10配置成倾斜到配线基板6附近。此时，最好将突部25设于加压加热工具11的外周，并设置朝半导体芯片1周边的倒角部19即绝缘性树脂膜5侧倾斜的倾斜部26。通过设置倾斜部26，能将加压加热工具11的热更快地传递到工具保护膜10。
通过使加压加热工具11靠近或接触工具保护膜10并对其加热，基底膜10a与加压膜10b之间的封闭空间14被来自加压加热工具11的热加热而膨胀。
在图8(c)中，通过使加压加热工具11进一步下降，并对工具保护膜10加热，使得基底膜10a与加压膜10b之间的封闭空间14进一步热膨胀。利用膜固定夹具9来夹持固定工具保护膜10，而且，利用加压加热工具11使半导体芯片1的凸点2的高度接近期望的值。通过使封闭空间14在被加压加热工具11、膜固定夹具9与配线基板6围起的空间内膨胀来隆起加压膜10b，从侧面方向对从半导体芯片1的一端溢出的成为倒角部19的绝缘性树脂膜5施加压力，使绝缘性树脂膜5固化，此外，利用加压膜10b的外压来抑制半导体芯片1下方的绝缘性树脂膜5被加压加热时的内压，使绝缘性树脂膜5固化。凸点2的变形负载为每一个凸点50g左右。通过凸点2的尺寸能控制负载，但在该情况下，考虑到可靠性，将凸点高度设为25μmt。另外，也可根据需要，加热、或冷却加热加压工作台8，控制绝缘性树脂膜5的内压，从而抑制空心的产生。
图8(d)是利用加压膜10b的外压使绝缘性树脂膜5固化后，将加热加压工具11解除而获得的倒装芯片安装件。
此处，如图7(b)所示，将UV光17照射到工具保护膜10，之后将图1(c)所示的加工品搬运到加压加热工作台8并使其吸附于加压加热工作台8，但也可并行进行将加工品搬运到加压加热工作台8并使其吸附于加压加热工作台8的工序和朝工具保护膜10照射UV光17的处理，从而能缩短制造节拍。
这样，通过使用薄的工具保护膜10来加压加热，能容易地将热传导至半导体芯片1和周边，也能使绝缘性树脂膜5固化，通过薄的工具保护膜10，利用加压加热工具11加压，能对半导体芯片1从上方平行均匀地作用负载。而且，能在短时间内固化。此外，通过使封闭空间14气化膨胀隆起，能将加压膜10b压紧于绝缘性树脂膜5并对其施加外压，使绝缘性树脂膜5固化。藉此，由于工具保护膜10是薄的膜，因此，与橡胶不同，能柔软地弯曲，并能减小半导体芯片1的周边的绝缘性树脂膜5的倒角部19，从而能抑制空心的产生。
(实施方式5)
图1、图9、图10、图11A、图11B、图12A、图12B及图13表示本发明的实施方式5。
在实施方式4中，工具保护膜10采用基底膜10a与加压膜10b的双层膜结构，在基底膜10a与加压膜10b之间形成有UV固化型粘接剂15，基底膜10a为遮光性的膜，加压膜10b为UV透过性的膜，但图9和图10(a)、图10(b)所示的实施方式5的工具保护膜10采用基底膜10a、加压膜10b和屏蔽膜18的三层膜结构，在基底膜10a与加压膜10b之间形成有UV固化型粘接剂15，且单片化的屏蔽膜18通过弱粘附层24粘接于加压膜10b的外表面。屏蔽膜18也可以是将铝等金属蒸镀于经得住工序中的最高温度的例如聚酰亚胺那样的耐热性树脂膜的材料。基底膜10a由UV透过性的膜构成。这样的工具保护膜10被膜固定夹具9保持。图10(a)是从基底膜10a侧观察工具保护膜10的俯视图，图10(b)是图10(a)的侧视图。
在图9中，预先将遮光罩16设置于工具保护膜10的基底膜10a侧的不对半导体芯片1加热加压的部分，并从基底膜10侧照射UV光17，从而使基底膜10a与加压膜10b的粘接下降。也可将阻挡UV的遮光性的膜用于加压膜10b侧，以使加压膜10b与光不接触。工具保护膜10采用仅使用于热加压的部分从朝膜固定夹具供给的导向件(未图示)露出的装置结构。
在图11(A)中，将图1(c)所示的加工品搬运至加压加热工作台8，并将配线基板背面吸附于加压加热工作台8。将图9所示的具有屏蔽膜18的工具保护膜10对齐并设置于半导体芯片1的上方。
接着，利用膜固定夹具9使工具保护膜10的加压膜10b侧剥离，并使加压膜10b挠曲。具体而言，容易将加压膜10b从因UV光17的照射而粘接力下降的基底膜10a剥离，通过使膜固定夹具9的辊子27朝半导体芯片1侧旋转，将加压膜10b剥离并搓起，从而朝工具保护膜10的中央部产生膜松弛。也可选定、控制UV固化型粘接剂的厚度、粘接力，以通过膜固定夹具9的膜剥离动作容易地形成封闭空间。
在加压膜10b与半导体芯片1开始接触的0.1秒左右后，对加压膜10b稳定地进行加压，然后使膜固定夹具9的辊子27旋转，从而进行加压膜10b的剥离。图11B表示图11A的俯视图。在该实施方式中，配置四个膜固定夹具9的辊子27，以包围半导体芯片1的外周。在这点上，实施方式4中的膜固定夹具9的辊子27也是相同的。
接着，在图12A中，使用膜固定夹具9将工具保护膜10夹住并下降以使其与半导体芯片1接触，并利用加压加热工具11将工具保护膜10压紧夹持于半导体芯片1，对半导体芯片1加压加热。加压膜10b的松弛在半导体芯片1的周边形成隆起。
通过使用加压加热工具11来作用负载，使凸点2全部戳破绝缘性树脂膜5，且与配线基板6的端子电极4接触并变形。使用膜固定夹具9将工具保护膜10配置成倾斜至配线基板6的附近。
此时，如图12A所示，加压加热工具11的外周最好朝半导体芯片1周边的倒角部19即绝缘性树脂膜5侧倾斜。通过设置倾斜部26，能将加压加热工具11的热更快地传递到工具保护膜10。
通过使加压加热工具11靠近或接触工具保护膜10，并对其加热，使得基底膜10a与加压膜10b之间的封闭空间14被来自加压加热工具11的热加热而膨胀，并将屏蔽膜18押紧且紧贴于倒角部19。
此外，通过使加压膜10b的松弛、即封闭空间14进一步热膨胀，使得加压膜10b在被加压加热工具11、膜固定夹具9和配线基板6围起的空间内隆起，并使用屏蔽膜18施加压力而从侧面方向按压从半导体芯片1的一端溢出的绝缘性树脂膜5的倒角部19，且利用加压膜的外压来抑制半导体芯片1下方的绝缘性树脂膜5被加压加热状态下的内压，来使绝缘性树脂膜5固化。图12B是图12A的俯视图。
在图13(a)中，通过使加压加热工具11进一步下降，并对工具保护膜10加热，来使基底膜10a与加压膜10b之间的封闭空间14进一步热膨胀。利用膜固定夹具9来夹持固定工具保护膜10，而且，利用加压加热工具11使半导体芯片1的凸点2的高度接近期望的值。通过使封闭空间14在被加压加热工具11、膜固定夹具9和配线基板6围起的空间内膨胀来隆起加压膜10b，从而从侧面方向施加压力并按压紧贴，以使屏蔽膜18压紧于从半导体芯片1的一端溢出的倒角部19且一部分埋入绝缘性树脂膜5。利用加压膜10b的外压来抑制半导体芯片1下方的绝缘性树脂膜5被加压加热时的内压，并进行绝缘性树脂膜5的固化。凸点2的变形负载为每一个凸点50g左右。利用凸点2的尺寸能控制负载，但在该情况下，考虑到可靠性，将凸点高度设为25μmt。另外，也可根据需要，加热或冷却加热加压工作台8，从而控制绝缘性树脂膜5的内压，来抑制空心的产生。
图13(b)表示绝缘性树脂膜5在加压膜10b的外压的作用下固化，且利用屏蔽膜18覆盖通过解除加热加压工具11而获得的半导体芯片而形成的倒装芯片安装件的剖视图。图13(c)是图13(b)的俯视图。
这样，通过使用薄的工具保护膜10来加压加热，能容易地将热传导至半导体芯片1和周边，也能使绝缘性树脂膜5固化，并能通过薄的工具保护膜10，利用加压加热工具11加压，从而从上方对半导体芯片1平行均匀地作用负载。而且，能在短时间内固化。此外，通过使封闭空间14气化膨胀隆起，来将加压膜10b压紧于绝缘性树脂膜5，并施加外压来使绝缘性树脂膜5固化。藉此，由于工具保护膜10是薄的膜，因此，与橡胶不同，能柔软地弯曲，并减小半导体芯片1的周边的绝缘性树脂膜5的倒角部19，从而能抑制空心的产生。
若屏蔽膜18带金属覆膜，则能屏蔽电磁波，若是树脂，则半导体芯片的上表面、侧面能应对外力、恶劣环境，从而能形成可靠性高的倒装芯片安装结构件。
作为基底膜10a最好是具有耐热性的膜。例如，聚酰亚胺、聚苯硫醚、氟树脂等。作为加压膜10b最好也是具有耐热性(NCF固化温度以上)的膜。例如，聚酰亚胺、聚苯硫醚、氟树脂等。基底膜10a和加压膜10b的厚度为5～10μm左右。
作为屏蔽膜18也可为绝缘性的金属薄板膜或对导电性的金属薄板膜进行绝缘覆膜处理后的材料。此外，除了电屏蔽以外，根据可靠性用途，也可为绝缘性、耐热性、低吸水率、阻气性的树脂膜。通过使用该树脂膜，除了能提高半导体芯片1与绝缘性树脂膜5的紧贴以外，还能提高热、应力下的机械的、耐湿性的可靠性。
在该实施方式5中，在图11A中，将加压膜10b部分地剥离，但当以作为将加工品搬运至加压加热工作台8并将其吸附于加压加热工作台8的工序前的工序进行时，因为能实现工序生产节拍的缩短，因此，最好采用该工序。
在该实施方式5中，将UV固化型粘接剂15设于基底膜10a与加压膜10b之间，但也能设置微粘附型粘接剂以代替UV固化型粘接剂15。
在该实施方式5中，使用弱粘附层24将屏蔽膜18与加压膜10b粘接，但也能通过静电使屏蔽膜18紧贴于加压膜10b。
在上述各实施方式中，在形成有封闭空间的工序中，仅使封入该封闭空间的材料热膨胀，但也可使封入该封闭空间的材料热膨胀，并通过强制地注射气体来控制封闭空间的尺寸和扩大。
在上述实施方式5中，预先将屏蔽膜18安装于工具保护膜10的一侧，并使该屏蔽膜18移动到半导体芯片1。利用微粘附性树脂将屏蔽膜18粘贴于半导体芯片1的上方，然后如实施方式1～实施方式4那样，利用工具保护膜10对该半导体芯片1加热加压，也能实现完成形状与实施方式5非常相似的零件。
工业上的可利用性
能将本发明用于将半导体元件倒装芯片安装于多层电路基板的小型、薄型的半导体装置等中。

Claims (5)

1.一种倒装芯片安装方法，其特征在于，
在将热固化性的底部填料树脂设于半导体芯片与配线基板之间、并将半导体芯片倒装芯片安装于配线基板时，
对将热固化性的底部填料树脂夹持于所述配线基板与所述半导体芯片之间而被定位设置的所述半导体芯片，从将固体、液体、气体中的至少一种以上密封于基底膜与加压膜之间而形成的工具保护膜的上方加压加热，从而使所述半导体芯片下方的所述底部填料树脂固化，并使所述加压膜从除了所述半导体芯片正上方的加压部以外的所述工具保护膜分离，所述分离后的加压膜朝所述半导体芯片周围的所述底部填料树脂隆起并与其抵接，对所述底部填料树脂加压加热并使其固化，从而将所述半导体芯片固定于所述配线基板。
2.一种倒装芯片安装方法，其特征在于，
在将热固化性的底部填料树脂设于半导体芯片与配线基板之间、并将半导体芯片倒装芯片安装于配线基板时，
对将热固化性的底部填料树脂夹持于所述配线基板与所述半导体芯片之间而被定位设置的所述半导体芯片，从由基底膜、加压膜和被粘贴于所述加压膜的屏蔽膜的三层膜结构构成的且将固体、液体、气体中的至少一种以上密封于所述基底膜与所述加压膜之间而形成的工具保护膜的上方加压加热，从而使所述半导体芯片下方的所述底部填料树脂固化，并使所述加压膜从除了所述半导体芯片正上方的加压部以外的所述工具保护膜分离，所述分离后的加压膜隔着所述屏蔽膜朝所述半导体芯片周围的所述底部填料树脂隆起并与其抵接，对所述底部填料树脂加压加热并使其固化，从而将所述半导体芯片固定于所述配线基板，并将所述屏蔽膜粘接于所述半导体芯片的一侧。
3.一种工具保护膜，其特征在于，
构成为至少由基底膜和加压膜构成的双层膜结构，将固体、液体、气体中的至少一种以上密封于所述基底膜与所述加压膜之间，且在加热时，未被加压部分的所述加压膜从所述基底膜分离并隆起。
4.一种工具保护膜，其特征在于，
构成为至少由基底膜、加压膜和被粘贴于所述加压膜的屏蔽膜构成的三层膜结构，将固体、液体、气体中的至少一种以上密封于所述基底膜与加压膜之间，且在加热时，未被加压部分的所述加压膜从所述基底膜分离并隆起。
5.一种倒装芯片安装装置，是将热固化性的底部填料树脂设于半导体芯片与配线基板之间、并将半导体芯片倒装芯片安装于配线基板的倒装芯片安装装置，其特征在于，包括：
膜固定夹具，该膜固定夹具保持将固体、液体、气体中的至少一种以上密封于基底膜与加压膜之间而形成的工具保护膜或由基底膜、加压膜和被粘贴于所述加压膜的屏蔽膜的三层膜结构构成的且将固体、液体、气体中的至少一种以上密封于所述基底膜与加压膜之间而形成的工具保护膜，并把将热固化性的底部填料树脂夹持于所述配线基板与所述半导体芯片之间而被定位设置的所述半导体芯片和其周围盖住；
加压加热工具，该加压加热工具形成有突部，该突部对所述半导体芯片加热且朝所述配线基板按压，并对所述膜固定夹具的内周部与所述半导体芯片的外周部分之间的所述工具保护膜进行按压而使其分离并朝所述热固化性的底部填料树脂的外周部分隆起。
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Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090289101A1 (en) * 2008-05-23 2009-11-26 Yong Du Method for ball grid array (bga) solder attach for surface mount
WO2010070806A1 (ja) * 2008-12-16 2010-06-24 パナソニック株式会社 半導体装置とフリップチップ実装方法およびフリップチップ実装装置
US8376012B2 (en) * 2009-12-07 2013-02-19 Panasonic Corporation Component press-bonding apparatus and component press-bonding method
CN102254837A (zh) * 2011-04-29 2011-11-23 永道无线射频标签(扬州)有限公司 电子标签倒贴片封装生产线封装工艺
JP5283242B2 (ja) * 2011-11-21 2013-09-04 株式会社名機製作所 積層方法および積層装置
TWI533421B (zh) * 2013-06-14 2016-05-11 日月光半導體製造股份有限公司 半導體封裝結構及半導體製程
US9177835B1 (en) 2014-04-17 2015-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Underfill dispensing with controlled fillet profile
CN106415826A (zh) * 2014-06-26 2017-02-15 索尼公司 半导体器件和制造半导体器件的方法
JP6314070B2 (ja) * 2014-10-07 2018-04-18 新光電気工業株式会社 指紋認識用半導体装置、指紋認識用半導体装置の製造方法及び半導体装置
JP6530242B2 (ja) * 2015-06-01 2019-06-12 日東電工株式会社 半導体裏面用フィルム及びその用途
KR20170011427A (ko) * 2015-07-23 2017-02-02 삼성전자주식회사 반도체 패키지의 범프 본딩 방법 및 이를 수행하기 위한 장치
JP6597056B2 (ja) * 2015-08-26 2019-10-30 富士通株式会社 半導体実装装置の加熱ヘッダ及び半導体の接合方法
JP6582975B2 (ja) * 2015-12-28 2019-10-02 富士通株式会社 半導体実装装置、半導体実装装置のヘッド及び積層チップの製造方法
JP6307729B1 (ja) * 2016-11-30 2018-04-11 株式会社新川 ボンディング装置及びボンディング方法
US11024595B2 (en) * 2017-06-16 2021-06-01 Micron Technology, Inc. Thermocompression bond tips and related apparatus and methods
JP2019021672A (ja) * 2017-07-12 2019-02-07 日立化成株式会社 半導体デバイスの製造に用いる積層体、及び半導体デバイスの製造方法
EP3428954B1 (en) * 2017-07-14 2021-05-19 Infineon Technologies AG Method for establishing a connection between two joining partners
KR102708431B1 (ko) * 2018-11-28 2024-09-25 삼성디스플레이 주식회사 본딩 장치 및 본딩 방법
FR3094561B1 (fr) 2019-03-25 2022-08-26 Commissariat Energie Atomique Procédé de fabrication d’une structure
US11410964B2 (en) * 2019-11-22 2022-08-09 Micron Technology, Inc. Contaminant control in thermocompression bonding of semiconductors and associated systems and methods
KR102459794B1 (ko) * 2020-05-25 2022-10-28 이주호 반도체 패키지의 전자파 차폐막 형성 방법
US11515171B2 (en) * 2020-06-08 2022-11-29 Micron Technology, Inc. Methods and apparatus for temperature modification and reduction of contamination in bonding stacked microelectronic devices
CN114207796B (zh) * 2020-07-16 2025-02-25 株式会社新川 安装装置
JP7569247B2 (ja) 2021-03-12 2024-10-17 キオクシア株式会社 半導体製造装置
WO2023062671A1 (ja) * 2021-10-11 2023-04-20 株式会社レゾナック 電子部品装置の製造方法、電子部品の実装方法及び緩衝シート
CN116631917B (zh) * 2023-07-19 2023-12-19 江苏快克芯装备科技有限公司 气压膜压接装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101151723A (zh) * 2005-03-28 2008-03-26 松下电器产业株式会社 倒装片安装体和倒装片安装方法及倒装片安装装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001226650A (ja) * 2000-02-16 2001-08-21 Nitto Denko Corp 放射線硬化型熱剥離性粘着シート、及びこれを用いた切断片の製造方法
JP4513235B2 (ja) 2001-05-31 2010-07-28 ソニー株式会社 フリップチップ実装装置
JP2002368026A (ja) * 2001-06-05 2002-12-20 Matsushita Electric Ind Co Ltd 半導体装置の製造方法および製造設備
JP4718734B2 (ja) * 2001-09-12 2011-07-06 日機装株式会社 回路素子の実装方法
CN1319140C (zh) * 2001-09-12 2007-05-30 日机装株式会社 电路元件安装方法
JP4121874B2 (ja) * 2002-03-13 2008-07-23 日世株式会社 生分解性成形物の製造方法およびそれに用いる成形型
JP3921459B2 (ja) 2003-07-11 2007-05-30 ソニーケミカル＆インフォメーションデバイス株式会社 電気部品の実装方法及び実装装置
JP4053483B2 (ja) * 2003-09-02 2008-02-27 新日鐵化学株式会社 半導体装置の製造方法
DE602005022414D1 (de) * 2004-03-11 2010-09-02 Nitto Denko Corp Warm abziehbare haftklebefolie und verfahren zur verarbeitung von haftgrund mit der warm abziehbaren haftklebefolie
JP4925669B2 (ja) * 2006-01-13 2012-05-09 ソニーケミカル＆インフォメーションデバイス株式会社 圧着装置及び実装方法
JP4925173B2 (ja) * 2006-06-02 2012-04-25 日東電工株式会社 ダイシング用粘着シート、及びそれを用いた被切断体の加工方法
JP4970863B2 (ja) * 2006-07-13 2012-07-11 日東電工株式会社 被加工物の加工方法
KR100831153B1 (ko) * 2006-10-26 2008-05-20 제일모직주식회사 반도체 조립용 접착 필름 조성물, 이에 의한 접착 필름 및이를 포함하는 다이싱 다이본드 필름
JP5122192B2 (ja) * 2007-07-04 2013-01-16 パナソニック株式会社 半導体素子実装装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101151723A (zh) * 2005-03-28 2008-03-26 松下电器产业株式会社 倒装片安装体和倒装片安装方法及倒装片安装装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开2003-86635A 2003.03.20

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