CN101937907B

CN101937907B - Chip stack package structure and manufacturing method thereof

Info

Publication number: CN101937907B
Application number: CN200910151818.2A
Authority: CN
Inventors: 刘君恺; 余致广; 戴明吉; 谢明哲
Original assignee: Industrial Technology Research Institute ITRI
Current assignee: Industrial Technology Research Institute ITRI
Priority date: 2009-06-29
Filing date: 2009-06-29
Publication date: 2012-09-05
Anticipated expiration: 2029-06-29
Also published as: CN101937907A

Abstract

The invention discloses a chip stacking and packaging structure which comprises a plurality of chip groups, a heat dissipation device, a substrate, a circuit board and a plurality of solder balls, wherein the chip groups are stacked together, and each chip group comprises a heat dissipation structure and a chip. The heat dissipation structure is provided with a chip placing groove, a plurality of through holes distributed in the chip placing groove and an extension part extending outwards from the chip placing groove. The chip is arranged in the chip placing groove, a plurality of convex blocks are arranged on the chip, and each convex block is correspondingly arranged in one of the through holes of the heat dissipation structure. The extension part of the heat dissipation structure of each chipset is in contact with the extension part of the heat dissipation structure of the adjacent chipset. The heat sink is located at the top of the chipset. The substrate is located at the bottom of the chip set. The circuit board is positioned below the substrate. The solder balls are positioned between the circuit board and the substrate. The invention also discloses a manufacturing method of the chip stacking and packaging structure.

Description

Chip stack package structure and preparation method thereof

Technical field

The present invention relates to a kind of chip stack package structure and preparation method thereof.

Background technology

In information society now, the user pursues high-speed, high-quality, polyfunctional electronic product.With regard to product appearance, the design of electronic product is to stride forward towards light, thin, short, little trend.In order to achieve the above object; Recently develop and a kind of multi-core encapsulation module; Just the chip with a plurality of difference in functionalitys or identical function is packaged on the same carrier (carrier) in the lump, and carrier for example is substrate or lead frame, and sees through carrier and external circuit electric connection.Therefore; Multi-core encapsulation module has transmission speed faster, shorter transmission path and better electrical characteristic; And further dwindle the size and the area of chip-packaging structure; Thereby make multicore sheet encapsulation technology be widely used among the various electronic products, and become following main product.

Chip stack package structure (stacked-chip packaging structure) promptly is to utilize multicore sheet encapsulation technology that a plurality of chips or passive component are disposed on the same carrier with the mode of piling up.Figure 1A illustrates known utilize perforation and projection and does the profile of the chip stack package structure of interconnection, and Figure 1B illustrates the surface temperature distribution figure of the chip stack package structure of Figure 1A.Please be simultaneously with reference to Figure 1A and Figure 1B; Known chip-stacked mode mainly is that a plurality of chips 110 are stacked; And these chips 110 are disposed on the substrate 120, these chips 110 can see through a plurality of perforation 140 and projections 130 that are disposed at therebetween and electrically connect each other.

Yet; When chip 110 in when running, if on the specific region of chip 110, produce when hot, the most of chip 110 that sees through of heat energy itself carries out heatsink transverse; Because the heat-sinking capability of air between chip 110 and the chip 110 and projection 130 is relatively poor, therefore form bigger thermal resistance in vertical direction.Just on chip 110, produce easily the higher focus (hot spot) of temperature, and focus is easy to generate problems of excessive heat and damage chip 110 and produce thermal stress at projection 130, so that influence the reliability of chip stack package structure 100.

Summary of the invention

The present invention provides a kind of chip stack package structure, and the radiator structure of its chipset can be used for the multiple heat dissipation path of vertical heat transfer and horizontal heat conduction.

The present invention proposes a kind of chip stack package structure and comprises a plurality of chipsets, heat abstractor, substrate, circuit board and a plurality of soldered ball, and wherein chipset is stacked each other, and each chipset comprises radiator structure and chip.Radiator structure has chip and puts groove, is distributed in the interior a plurality of perforations of chip storing groove and puts the outward extending extension of groove from chip.Chip is arranged at chip and puts in the groove, has a plurality of projections on the chip, and each projection correspondence is arranged in the wherein perforation of radiator structure.The extension of the radiator structure of each chipset contacts with the extension of the radiator structure of the chipset of adjacency.Heat abstractor is positioned at the top of chipset.Substrate is positioned at the bottom of chipset.Circuit board is positioned at the below of substrate.Soldered ball is between circuit board and substrate.

The present invention proposes a kind of chip stack package structure and comprises first chipset, at least one second chipset, heat abstractor, substrate, bottom radiator structure, circuit board and a plurality of soldered ball.First chipset comprises first radiator structure and first chip.First radiator structure has first chip and puts groove and put outward extending first extension of groove from first chip.First chip is arranged at first chip and puts in the groove.Second chipset is stacked in the below of first chipset; Wherein each second chipset comprises second radiator structure and at least one second chip, and second radiator structure has second chip and puts groove, is distributed in the interior a plurality of perforations of second chip storing groove and puts outward extending second extension of groove from second chip.Second chip is arranged at second chip and puts in the groove, has a plurality of projections at least one second chip, and each projection correspondence is arranged in the wherein perforation of second radiator structure.First extension of first radiator structure contacts with second extension of second radiator structure of at least one second chipset of adjacency.Heat abstractor is positioned at the top of first chipset.Substrate is positioned at the bottom of at least one second chipset.The bottom radiator structure is between substrate and at least one second chipset.Circuit board is positioned at the below of substrate.Soldered ball is between circuit board and substrate.

The manufacturing approach that the present invention proposes a kind of chip stack package structure is described below.At first, wafer is provided, has a plurality of chips, perforation and many interlaced precut roads on the wafer.Then, radiator structure is provided, it has main body, many interlaced strip projected parts portions and a plurality of groove, and the bottom of groove has a plurality of perforations.Then, on the chip of wafer, form a plurality of projections.Afterwards, radiator structure and wafer set are lumped together, wherein the strip projected parts portion of radiator structure is positioned at the precut road on the wafer, and the projection on the chip penetrates the perforation of radiator structure.Then, wafer is carried out polish process, so that the strip projected parts portion of radiator structure comes out.Then, precut certainly road carries out cutting process, to form a plurality of chipsets.Afterwards, chipset is stacked.Then, with the chipset configuration that is stacked on substrate.

Based on above-mentioned; Radiator structure of the present invention has conductive structure and the peripheral extension between each chip; Therefore, can be with each chip owing to the inhomogeneous focus that produces of heating spread, extension is horizontal to conduct heat and vertical heat transfer and the heat that entire chip produces also can see through.Thus, radiator structure can come the thermal diffusion that chip produced and conduct to the heat abstractor of chipset top and the substrate of chipset below effectively.

For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and conjunction with figs. elaborates as follows.

Description of drawings

Figure 1A illustrates the profile of known chip stack package structure, and Figure 1B illustrates the surface temperature distribution figure of the chip stack package structure of Figure 1A.

Fig. 2 A illustrates the profile of the chip stack package structure of the embodiment of the invention, and Fig. 2 B illustrates the vertical view of the radiator structure of Fig. 2 A.

Fig. 3 illustrates the surface temperature distribution figure of the chip stack package structure of Fig. 2 A.

Fig. 4 and Fig. 5 illustrate two kinds of variations of the chip stack package structure of Fig. 2 A respectively.

Fig. 6 illustrates the profile of the chip stack package structure of the embodiment of the invention.

Fig. 7 A～Fig. 7 E illustrates the process section of the chip stack package structure of the embodiment of the invention.

Description of reference numerals

110,214,712: chip

120,230,640,740: substrate

130,216,626, A: projection

140,212b, 622b, 712a, 726b: perforation

200,400,500,600: chip stack package structure

210,730: chipset

212,720: radiator structure

212a: chip is put groove

212c: extension

212d, 212e, 622d, 622e, 716: surface

212f: interlayer portion

214a: conductive channel

214b: through hole

214c: electric conducting material

220,630: heat abstractor

240,660: circuit board

242: ground mat

243: the wiring board perforation

244: copper foil layer

250,670: soldered ball

262,264,682,684,750: adhesion coating

270,690,760: padded coaming

410: the bottom radiator structure

412: substrate is put groove

414: opening

416: the outer edge

418a, 418b: a side

420: knitting layer

510: encapsulating structure

512,612: the first radiator structures

512a, 612a: first chip is put groove

512b: first perforation

512c, 612b: first extension

514,614: the first chips

516: the first substrates

610: the first chipsets

620: the second chipsets

622: the second radiator structures

622a: second chip is put groove

622c: second extension

624: the second chips

650: the bottom radiator structure

710: wafer

714: precut road

720a: radiator structure unit

722: main body

724: strip projected parts portion

726: groove

726a, B: bottom

G: gap

T: top

Embodiment

Fig. 2 A illustrates the profile of the chip stack package structure of the embodiment of the invention, and Fig. 2 B illustrates the vertical view of the radiator structure of Fig. 2 A.Fig. 3 illustrates the surface temperature distribution figure of the chip stack package structure of Fig. 2 A.

Please be simultaneously with reference to Fig. 2 A and Fig. 2 B, the chip stack package structure 200 of present embodiment comprises a plurality of chipset 210, heat abstractor 220, substrate 230, circuit board 240 and a plurality of soldered ball 250.Chipset 210 is stacked each other, and each chipset 210 comprises radiator structure 212 and chip 214.

Radiator structure 212 has chip and puts groove 212a, is distributed in the interior a plurality of perforation 212b of chip storing groove 212a and puts the outward extending extension 212c of groove 212a from chip.In the present embodiment, the material of radiator structure 212 for example is a ceramic material, like aluminium oxide, aluminium nitride and carborundum etc., or metal material such as copper, aluminium etc., or semi-conducting material such as silicon etc.Chip 214 is arranged at chip and puts in the groove 212a, has a plurality of projections 216 on the chip 214, and each projection 216 correspondence is arranged in the wherein perforation 212b of radiator structure 212.In detail; In the present embodiment; On the chip 214 have circuit and an element (not illustrating) design; And chip 214 optionally has a plurality of conductive channel 214a, and so-called conductive channel 214a is made up of the electric conducting material 214c that is formed on the through hole 214b in the chip 214 and fill in the through hole 214b.Projection 216 on the chip 214 can be electrically connected to conductive channel 214a, can see through projection 216 between the chipset 210 and electrically connect each other with conductive channel 214a.In the present embodiment; It is design upwards that chip is put groove 212a, therefore, and before above-mentioned each chip 214 not being stacked; Be earlier chip 214 to be placed in chip respectively to put within the groove 212a, just can directly the radiator structure that is equiped with chip 214 212 be stacked.

In the present embodiment; Relative two surperficial 212d of radiator structure 212,212e are last can respectively to dispose adhesion coating 262 and adhesion coating 264; To two adjacent chips 214, and then strengthen bond strength and the reliability of chip stack package structure 200 between the chipset 210 with jointing radiating structure 212.More detailed, adhesion coating 262,264 lays respectively at upper surface 212d and the lower surface 212e of the 212f of interlayer portion, and can also more be arranged at the surface of extension 212c.Adhesion coating 262,264 is preferably selected sticky material with high-termal conductivity matter.In addition, in the present embodiment, padded coaming 270 can be set in perforation 212b, it is filled in the inwall and the clearance G between the projection 216 of perforation 212b, and to reduce the stress of projection 216, the material of padded coaming 270 for example is a polymer.

The extension 212c of the radiator structure 212 of each chipset 210 contacts with the extension 212c of the radiator structure 212 of the chipset 210 of adjacency.Heat abstractor 220 is positioned at the top T of chipset 210, and heat abstractor 220 for example is the heat dissipation metal fin.Substrate 230 is positioned at the bottom B of chipset 210.Circuit board 240 is positioned at the below of substrate 230.Soldered ball 250 is between circuit board 240 and substrate 230, to electrically connect circuit board 240 and substrate 230.Circuit board 240 has ground mat (or power source pad) 242, perforation 243 and copper foil layer 244 or the like element, and it is the element on the general known circuit board.

It should be noted that; Radiator structure 212 is except having the 212f of interlayer portion between the chip 214; Also has the extension 212c that is positioned at each chip 214 periphery; Therefore, the heat that chip 214 produces can see through the horizontal heat conduction of the 212f of interlayer portion to this extension 212c, also can see through extension 212c vertical heat transfer.Thus, the heat abstractor 220 of heat conduction to chipset 210 tops that can be effectively chip 214 be produced of radiator structure 212 and the substrate 230 of chipset 210 belows.With reference to Fig. 3, can be known by Fig. 3 that please when chip 214 adstante febres, the Temperature Distribution of chip stack package structure 200 quite evenly and not produces focus, hence one can see that, and radiator structure 212 can reach the effect of the heat that even dispersed chip 214 produced really.

Fig. 4 and Fig. 5 illustrate two kinds of variations of the chip stack package structure of Fig. 2 A respectively.Please earlier with reference to Fig. 4; In the present embodiment; Chip stack package structure 400 is similar with the chip stack package structure 200 shown in Fig. 2 A; The difference part is that chip stack package structure 400 also comprises bottom radiator structure 410, and it has substrate and puts groove 412, is distributed in substrate and puts a plurality of openings 414 in the groove 412 and put groove 412 outward extending outer edges 416 from substrate.Similarly; Relative two surperficial 212d of radiator structure 212, last adhesion coating 262 and the adhesion coating 264 of also can respectively disposing of 212e; To two adjacent chips 214, and then strengthen bond strength and the reliability of chip stack package structure 400 between the chipset 210 with jointing radiating structure 212.

Substrate 230 is arranged at substrate and puts in the groove 412; Each soldered ball 250 correspondence is arranged in the wherein opening 414 of bottom radiator structure 410; And a side 418a of bottom radiator structure 410 contacts with the radiator structure 212 of the chipset 210 of adjacency, and opposite side 418b contacts with circuit board 240.

More detailed, the outer edge 416 of bottom radiator structure 410 contacts with the extension 212c of the radiator structure 212 of chipset 210.Thus, the heat that produced of chip 214 can see through radiator structure 212 and conduct to substrate 230 and circuit board 240 with bottom radiator structure 410.In the present embodiment, bottom radiator structure 410 can be connected with the ground mat (or power source pad) 242 of circuit board 240, or sees through wiring board perforation 243, connects copper foil layer 244, is beneficial to the heat that chip 214 is produced is conducted in the external environment through circuit board 240.In addition, in the present embodiment, can between bottom radiator structure 410 and circuit board 240, knitting layer 420 be set, on engage base radiator structure 410 to circuit board 240, the material of knitting layer 420 can be the material with high thermal conductivity coefficient.

According to another embodiment, please with reference to Fig. 5, the chip stack package structure 500 of Fig. 5 is similar with the chip stack package structure 400 of Fig. 4, and the difference part is that chip stack package structure 500 also comprises the encapsulating structure 510 between circuit board 240 and substrate 230.In the present embodiment, encapsulating structure 510 comprises first radiator structure 512, first chip 514 and first substrate 516.It should be noted that in other embodiments the quantity of first radiator structure 512 and first chip 514 also can be a plurality of.Similarly; Relative two surperficial 212d of radiator structure 212, last adhesion coating 262 and the adhesion coating 264 of also can respectively disposing of 212e; To two adjacent chips 214, and then strengthen bond strength and the reliability of chip stack package structure 200 between the chipset 210 with jointing radiating structure 212.This adhesion coating 264 all belongs to it for heat-conducting glue etc. and equivalent link thereof.

First radiator structure 512 has first chip and puts groove 512a, is distributed in the interior a plurality of first perforation 512b of the first placement chip groove 512a and puts the outward extending first extension 512c of groove 512a from first chip.First chip 514 is arranged at first and places in the chip groove 512a.First substrate 516 is positioned at the bottom of first chip 514.The first extension 512c of first radiator structure 512 contacts with the outer edge 416 of the bottom radiator structure 410 of adjacency.In other embodiments; If chip stack package structure does not have bottom radiator structure 410 (promptly similar with chip stack package structure 200), then the first extension 512c of first radiator structure 512 can contact with the extension 212c of the radiator structure 212 of the chipset 210 of adjacency.

In the chip stack package structure of above-mentioned Fig. 2 A, Fig. 4 and Fig. 5, chip putting groove 212a is design upwards, so the invention is not restricted to this.In other embodiment, the chip putting groove also can be downward design.

Fig. 6 illustrates the profile of the chip stack package structure of another embodiment of the present invention.Please with reference to Fig. 6, the chip stack package structure 600 of present embodiment comprises first chipset 610, a plurality of second chipset 620, heat abstractor 630, substrate 640, bottom radiator structure 650, circuit board 660 and a plurality of soldered ball 670.

First chipset 610 comprises first radiator structure 612 and first chip 614.First radiator structure 612 has first chip and puts groove 612a and put the outward extending first extension 612b of groove 612a from first chip.First chip 614 is arranged at first chip and puts in the groove 612a.

Second chipset 620 is stacked in the below of first chipset 610, and second chipset 620 comprises second radiator structure 622 and second chip 624.Second radiator structure 622 has second chip and puts groove 622a, is distributed in the interior a plurality of perforation 622b of second chip storing groove 622a and puts the outward extending second extension 622c of groove 622a from second chip.Second chip 624 is arranged at second chip and puts in the groove 622a, has a plurality of projections 626 on second chip 624, and each projection 626 correspondence is arranged in the wherein perforation 622b of second radiator structure 622.What is worth mentioning is that first chip puts groove 612a and second chip storing groove 622a is downward groove, in other words; In the present embodiment, before above-mentioned each chip 614,624 not being stacked, be earlier first chip 614 and second chip 624 to be placed in first and second chip storing groove 612a respectively; Among the 622a; Just will be equiped with first and second radiator structure 610,620 turnbacks of first and second chip 614,624 afterwards and be stacked.

The first extension 612b of first radiator structure 612 contacts with the second extension 622c of second radiator structure 622 of second chipset 620 of adjacency.In the present embodiment, in the present embodiment, the material of radiator structure 212 for example is a ceramic material, like aluminium oxide, aluminium nitride and carborundum etc., or metal material such as copper, aluminium etc., or semi-conducting material such as silicon etc.First and second radiator structure 612,622 can be same material or different materials.

In the present embodiment; Relative two surperficial 622d of second radiator structure 622,622e are last can respectively to dispose adhesion coating 682 and adhesion coating 684; Engaging second radiator structure 622 to 2 second adjacent chips 624 or on the first adjacent chip 614 and second chip 624, and then strengthen the reliability of first and second chipset 610, the bond strength between 620 and chip stack package structure 600.In addition, in the present embodiment, padded coaming 690 can be set in perforation 622b, it is filled in the inwall and the clearance G between the projection 626 of perforation 622b, and to reduce the stress of projection 626, the material of padded coaming 690 for example is a polymer.

Heat abstractor 630 is positioned at the top T of first chipset 610.In the present embodiment, first chip 614 heat of being produced in running can see through first radiator structure, 612 vertical conduction to the heat abstractor 630 that is positioned on first chipset 610.Substrate 640 is positioned at the bottom B of second chipset 620.Bottom radiator structure 650 is between the substrate 640 and second chipset 620.Circuit board 660 is positioned at the below of substrate 640.Circuit board 660 has ground mat (or power source pad) 242, perforation 243 and copper foil layer 244 or the like element, and it is the element on the general known circuit board.Soldered ball 670 is between circuit board 660 and substrate 640.

In other embodiments; Chip stack package structure also can comprise another encapsulating structure (not illustrating); Shown in the encapsulating structure of Fig. 5; It is between circuit board 660 and substrate 640, and chip stack package structure 600 is similar with the chip stack package structure 500 of Fig. 5 with the juncture of another encapsulating structure.

At first,, wafer 710 is provided, has a plurality of chips 712 and many interlaced precut roads 714 on the wafer 710 please with reference to Fig. 7 A.Particularly, these precut roads 714 mark off these chips 712.On chip, have a plurality of perforation 712a, in the present embodiment, also can on the surface 716 of wafer 710, form adhesion coating 750.

Then, please once more with reference to Fig. 7 A, radiator structure 720 is provided, it has main body 722, many interlaced strip projected parts portions 724 and a plurality of groove 726, and the bottom 726a of groove 726 has a plurality of perforation 726b.In detail, the Cutting Road 714 on the strip projected parts portion 724 corresponding wafers 710 of radiator structure 720, thereby the pattern of strip projected parts portion 724 is to design according to the position at Cutting Road 714 places with distributing.Chip 712 on the groove 726 corresponding wafers 710 of radiator structure 720, thereby groove 726 patterns are to design according to the position at chip 712 places.The perforation 726b of the bottom 726a of groove 726 designs according to the follow-up position that on chip 712, forms projection.

Then, please with reference to Fig. 7 B, on the chip 712 of wafer 710, form a plurality of projection A.Afterwards; Radiator structure 720 and wafer 710 are combined; So that the strip projected parts portion 724 of radiator structure 720 is disposed in the precut road 714 on the wafer 710; Each chip 712 correspondence is arranged in the wherein groove 726 of radiator structure 720, and the projection A on the chip 712 penetrates among the perforation 726b of radiator structure 720.Then, in the present embodiment, optionally in perforation 726b, insert padded coaming 760.

Then,, wafer 710 is carried out polish process, so that the strip projected parts portion 724 of radiator structure 720 comes out please with reference to Fig. 7 C.Particularly, polish process is that the surface 718 (back side) of wafer 710 is ground, and till exposing strip projected parts portion 724, wherein surface 718 is with respect to surface 716 with the thickness that reduces wafer 710.

Then, please with reference to Fig. 7 D-1, Fig. 7 D-2, precut certainly road 714 carries out cutting process, to form a plurality of chipsets 730.Particularly, when carrying out cutting process, be the strip projected parts portion 724 that cutting is arranged in precut road 714, to cut apart 720 one-tenth a plurality of radiator structures unit 720a of radiator structure, each chipset 730 all has radiator structure unit 720a.Afterwards,, chipset 730 is stacked, and the radiator structure unit 720a that adjacent chipset 730 is had contacts please with reference to Fig. 7 E.Then, the chipset that is stacked 730 is disposed on the substrate 740.Afterwards, can on the chipset 730 of the top, design heat abstractor (shown in Fig. 2 A), and soldered ball and circuit board (shown in Fig. 2 A) or the like element is set in the below of substrate 740.

In sum; Radiator structure of the present invention has conductive structure and the peripheral extension that is positioned at each chip chamber; So have a plurality of heat dissipation path; Therefore the heat of chip generation not only can be carried out horizontal heat conduction through the conductive structure between chip of radiator structure and the extension of chip periphery, and the conductive structure and the extension that also can see through between each chip carry out vertical heat transfer.Thus, radiator structure can be effectively with the heat abstractor of heat conduction to the chipset top that chip produced and the substrate of chipset below, even be transmitted to the circuit board of substrate below, thereby can effectively avoid producing on the chip focus.

Though the present invention discloses as above with embodiment; Right its is not in order to limit the present invention; Those of ordinary skill in the technical field under any; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking appended claim.

Claims

1. A chip stack package structure, comprising:

Multiple chipsets, stacked on top of each other, each chipset includes:

The heat dissipation structure has a chip placement groove, a plurality of through holes distributed in the chip placement groove, an interlayer portion between the plurality of through holes, and an extension extending outward from the chip placement groove department;

The chip is arranged in the chip placement groove, the chip has a plurality of bumps, and each bump is correspondingly arranged in one of the through holes of the heat dissipation structure,

Wherein, the extension of the heat dissipation structure of each chipset is in contact with the extension of the heat dissipation structure of the adjacent chipset;

heat sink, which sits on top of multiple chipsets;

a substrate located at the bottom of the plurality of chipsets;

a circuit board located beneath the substrate; and

A plurality of solder balls are located between the circuit board and the substrate.

2. The chip stack package structure according to claim 1, further comprising:

The bottom heat dissipation structure has a substrate placement groove, a plurality of openings distributed in the substrate placement groove, and an outer edge portion extending outward from the substrate placement groove,

Wherein, the substrate is disposed in the substrate placement groove, each solder ball is correspondingly disposed in one of the openings of the bottom heat dissipation structure, and the outer edge of the bottom heat dissipation structure is in contact with the heat dissipation structure of the adjacent chipset. The extension part contacts, and the other side contacts the circuit board.

3. The chip stack package structure as claimed in claim 2, further comprising a bonding layer located between the bottom heat dissipation structure and the circuit board to bond the bottom heat dissipation structure to the circuit board.

4. The chip stack package structure as claimed in claim 2, further comprising another package structure located between the circuit board and the substrate.

5. The chip stack package structure according to claim 4, wherein said another package structure comprises:

At least one first heat dissipation structure has a first chip placement groove, a plurality of first through holes distributed in the first chip placement groove, and a first through hole extending outward from the first chip placement groove an extension;

At least one first chip is correspondingly arranged in the first chip placement groove; and

a first substrate located at the bottom of the first chip,

Wherein, the first extension part of the first heat dissipation structure is in contact with the extension part of the heat dissipation structure of the adjacent chipset.

6 . The chip stack package structure as claimed in claim 1 , further comprising a buffer material, which is located in the plurality of through holes to fill up the gap between the inner walls of the plurality of through holes and the plurality of bumps. 7 .

7. The chip stack package structure as claimed in claim 6, wherein a material of the buffer material comprises a polymer.

8. The chip stack package structure according to claim 1, wherein the material of the heat dissipation structure includes ceramics, metals or semiconductors, wherein ceramics include aluminum oxide or aluminum nitride, metals include copper or aluminum, and semiconductors include silicon.

9. The chip stack package structure according to claim 1, wherein each chip group further comprises at least one adhesive layer, which is located at least among the upper surface and the lower surface of the interlayer portion of the heat dissipation structure and the surface of the extension portion one.

10. The chip stack package structure according to claim 1, wherein the chip has a plurality of through holes, and the plurality of through holes are filled with conductive material to form a plurality of conductive channels, and the plurality of conductive channels pass through the plurality of The bumps are electrically connected with adjacent chips.

11. A chip stack package structure, comprising:

A first chipset comprising:

The first heat dissipation structure has a first chip placement groove and a first extension extending outward from the first chip placement groove;

the first chip is arranged in the first chip placement groove;

At least one second chipset stacked below the first chipset, wherein the second chipset includes:

The second heat dissipation structure has a second chip placement groove, a plurality of through holes distributed in the second chip placement groove, an interlayer part between the plurality of through holes, and a placement from the second chip. the second extension part extending outward from the groove;

The second chip is arranged in the second chip placement groove, the second chip has a plurality of bumps, and each bump is correspondingly arranged in one of the through holes of the second heat dissipation structure,

Wherein, the first extension portion of the first heat dissipation structure is in contact with the second extension portion of the second heat dissipation structure of the adjacent second chipset;

a cooling device located on the top of the first chipset;

a substrate located at the bottom of the second chipset;

a bottom heat dissipation structure located between the substrate and the second chipset;

a circuit board located beneath the substrate; and

12 . The chip stack package structure as claimed in claim 11 , further comprising a bonding layer located between the bottom heat dissipation structure and the circuit board to bond the bottom heat dissipation structure to the circuit board. 13 .

13. The chip stack package structure as claimed in claim 11, further comprising another package structure located between the circuit board and the substrate.

14 . The stacked chip package structure as claimed in claim 11 , further comprising a buffer material located in the plurality of through-holes to fill up gaps between inner walls of the plurality of through-holes and the plurality of bumps.

15. The chip stack package structure as claimed in claim 14, wherein a material of the buffer material comprises a polymer.

16. The chip stack package structure according to claim 11, wherein the material of the heat dissipation structure includes ceramics, metals or semiconductors, wherein ceramics include aluminum oxide or aluminum nitride, metals include copper or aluminum, and semiconductors include silicon.

17. The chip stack package structure as claimed in claim 11, wherein each second chip group further comprises at least one adhesive layer located on at least one of the upper and lower surfaces of the interlayer portion and the surface of the extension portion.

18. The chip stack package structure as claimed in claim 11, wherein the second chip has a plurality of through holes, and the plurality of through holes are filled with conductive material to form a plurality of conductive channels, and the plurality of conductive channels pass through A plurality of bumps are electrically connected with adjacent chips.

19. A method for manufacturing a chip stack package structure, comprising:

A wafer is provided, the wafer has a plurality of chips, a plurality of through holes filled with conductive material in the plurality of through holes to form a plurality of conductive channels and a plurality of pre-cut lines interlaced with each other;

Provide a heat dissipation structure, which has a main body, a plurality of interlaced strip-shaped protrusions and a plurality of grooves, and the bottom of the grooves has a plurality of through holes;

forming a plurality of bumps on a plurality of conductive vias of a plurality of chips of the wafer;

Combining the heat dissipation structure with the wafer, wherein the plurality of strip-shaped protrusions of the heat dissipation structure are located in the plurality of pre-cut lines on the wafer, and the plurality of bumps on the plurality of chips penetrate the heat dissipation structure. Multiple through holes;

performing a grinding process on the wafer, so that the plurality of strip-shaped protrusions of the heat dissipation structure are exposed;

performing a dicing process from a plurality of pre-dicing lanes to form a plurality of chipsets;

Stack multiple chipsets together; and

A plurality of stacked chipsets are arranged on the substrate.

20 . The method of manufacturing the stacked chip package structure as claimed in claim 19 , further comprising filling the plurality of through holes with a buffer material after assembling the heat dissipation structure and the chip. 21 .

21 . The method for manufacturing a stacked chip package structure as claimed in claim 20 , further comprising forming an adhesive layer on at least one surface of the heat dissipation structure or the chip before combining the heat dissipation structure with the chip.