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CN101908564A - Bulk silicon based capacitor and manufacturing method thereof - Google Patents

Bulk silicon based capacitor and manufacturing method thereof Download PDF

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Publication number
CN101908564A
CN101908564A CN2010101984353A CN201010198435A CN101908564A CN 101908564 A CN101908564 A CN 101908564A CN 2010101984353 A CN2010101984353 A CN 2010101984353A CN 201010198435 A CN201010198435 A CN 201010198435A CN 101908564 A CN101908564 A CN 101908564A
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CN
China
Prior art keywords
electric capacity
electrode
forms
backing
extension electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2010101984353A
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Chinese (zh)
Inventor
许丹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN2010101984353A priority Critical patent/CN101908564A/en
Publication of CN101908564A publication Critical patent/CN101908564A/en
Pending legal-status Critical Current

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Abstract

The invention provides a bulk silicon based capacitor and a manufacturing method thereof. The capacitor is arranged on the bulk silicon and comprises a first electrode structure and a second electrode structure, wherein the first electrode structure is provided with a first electrode and a plurality of mutually-parallel first extending electrodes formed by extending the first electrode; the second electrode structure is provided with a second electrode and a plurality of parallel second extending electrodes formed by extending the second electrode; and the first extending electrodes and the second extending electrodes are sequentially interactively staggered. Since the capacitor uses the bulk silicon as the substrate, metal does not exist between the capacitor and a substrate and a back substrate which corresponds to the position of the capacitor is removed, thereby reducing the stray capacitance formed by coupling a conductive metal connection wire or metal layer with the capacitor.

Description

Electric capacity and manufacture method thereof based on body silicon
Technical field
The present invention relates to a kind of electric capacity and manufacture method thereof, specifically, relate to a kind of electric capacity and manufacture method thereof based on body silicon.
Background technology
The structure of electric capacity is made of two parallel metallic plates and two middle insulating material of metallic plate, the formula of electric capacity is C=ε S/4 π kd, capacity of parallel plate capacitor C follows DIELECTRIC CONSTANT, is directly proportional over against area S, with being inversely proportional between pole plate apart from d, k is the electrostatic force constant in the formula, and DIELECTRIC CONSTANT is by medium decision between the two-plate.
Be applied in the electric capacity in the integrated circuit, usually all electric capacity is formed on the surface that forms with certain medium, the metal connecting line or the metal level that under this surface, also have other conductions, and the metal connecting line of these conductions or metal level and capacitive coupling form stray capacitance, influence the integrated circuit signal transmission speed, restricted the performance of chip.
Summary of the invention
The technical problem to be solved in the present invention is: a kind of electric capacity and manufacture method thereof based on body silicon is provided, reduces the metal connecting line of conduction or the stray capacitance of metal level and capacitive coupling formation.
In order to realize the object of the invention, the invention provides a kind of electric capacity based on body silicon, described electric capacity places on the body silicon, and described electric capacity comprises:
First electrode structure, first extension electrode some parallel to each other that has first electrode and extend to form by described first electrode;
Second electrode structure, second extension electrode some parallel to each other that has second electrode and extend to form by described second electrode;
Described first extension electrode and described second extension electrode intert successively alternately.
Leave the gap between described first extension electrode and described second extension electrode.
The width in each gap that forms between described first extension electrode and described second extension electrode equates.
The material of described first electrode structure and described second electrode structure is aluminium or copper.
Described body silicon comprises:
At the bottom of the backing;
The insulating barrier that on the surface at the bottom of the described backing, forms;
On described insulating barrier, form trench oxide;
The polysilicon layer that on described trench oxide, forms;
The dielectric layer that above described polysilicon, forms.
At the bottom of the described backing silicon.
Described insulating barrier is an oxide layer.
Described oxide layer is preferably silicon dioxide.
Described polysilicon layer is CoSi.
The present invention also provide a kind of as described in the above-mentioned claim based on the manufacture method of the electric capacity of body silicon, comprise step:
At the bottom of forming backing on the wafer;
On the surface at the bottom of the described backing, form insulating barrier;
On described insulating barrier, form groove;
Deposition forms trench oxide in described groove;
On described trench oxide surface, form polysilicon;
Above described polysilicon, form dielectric layer;
Depositing metal layers on described dielectric layer;
The etched portions metal level makes the remainder metal level form described electric capacity;
Compared with prior art, electric capacity of the present invention is substrate with body silicon, make the metal that no longer contains conduction between described electric capacity and the substrate, and remove at the bottom of the backing of corresponding described electric capacity position, thereby reduce the stray capacitance of the metal connecting line of conduction or metal level and capacitive coupling formation.
Description of drawings
Fig. 1 is the structural representation that the present invention is based on the electric capacity of body silicon;
Fig. 2 is the interface schematic diagram of the electric capacity based on body silicon shown in Figure 1 along the A-A cross section.
Embodiment
For clearer understanding technology contents of the present invention, especially exemplified by specific embodiment and cooperate appended graphic being described as follows.
See also Fig. 1, Fig. 1 is the structural representation that the present invention is based on the electric capacity of body silicon.
The electric capacity 1 of present embodiment comprises: first electrode structure 10 and second electrode structure 11, the material of described first electrode structure 10 and second electrode structure 11 is aluminium or copper.
First extension electrode 100 some parallel to each other that described first electrode structure 10 has first electrode 101 and extended to form by described first electrode.
Second extension electrode 110 some parallel to each other that described second electrode structure 11 has second electrode 111 and extended to form by described second electrode;
Described first extension electrode 100 interts successively alternately with described second extension electrode 111.
See also Fig. 2, Fig. 2 is the interface schematic diagram of the electric capacity based on body silicon shown in Figure 1 along the A-A cross section.The described electric capacity 1 of present embodiment places on the substrate, and described substrate is body silicon substrate (Bulk CMOSSubstrate), and described body silicon substrate comprises: at the bottom of the backing 5; The insulating barrier 4 that on 5 surface at the bottom of the described backing, forms; The trench oxide 3 that in described insulating barrier 4, forms; The polysilicon layer 2 that forms on described trench oxide 3, described polysilicon layer 2 is CoSi.The dielectric layer 6 that forms above described polysilicon layer 2, described dielectric layer 6 can be the formation such as nitride of the oxide or the silicon of silicon.
5 is silicon at the bottom of the described backing, and described insulating barrier 4 is an oxide layer, is preferably silicon dioxide.
Described first extends between extension electrode 100 and described second extension electrode 110 and leaves gap 12, and the width in each gap 12 of formation equates between described first extension electrode 100 and described second extension electrode 110.
The step of making described electric capacity is as follows:
At the bottom of forming backing on the wafer 5;
On 5 surface at the bottom of the described backing, form insulating barrier 4;
Groove on described insulating barrier 4;
Deposition forms trench oxide 3 on described groove;
On described trench oxide 3 surfaces, form polysilicon 2;
Form dielectric layer 6 above described polysilicon 2, this dielectric layer 6 is an insulating material;
Depositing metal layers on described dielectric layer 6;
The etched portions metal level makes the remainder metal level form described electric capacity 1.
The electric capacity 1 of present embodiment is substrate with body silicon, make the metal that no longer contains conduction between described electric capacity 1 and the substrate, and remove at the bottom of the backing of corresponding described electric capacity 1 position, thereby reduce the metal connecting line of conduction or the stray capacitance of metal level and capacitive coupling formation.
More than show and described basic principle of the present invention, principal character and advantage of the present invention.The technical staff of the industry should understand; the present invention is not restricted to the described embodiments; that describes in the foregoing description and the specification just illustrates principle of the present invention; the present invention also has various changes and modifications without departing from the spirit and scope of the present invention, and these changes and improvements all fall in the claimed scope of the invention.The claimed scope of the present invention is defined by appending claims and equivalent thereof.

Claims (10)

1. electric capacity based on body silicon, it is characterized in that: described electric capacity places on the body silicon, and described electric capacity comprises:
First electrode structure, first extension electrode some parallel to each other that has first electrode and extend to form by described first electrode;
Second electrode structure, second extension electrode some parallel to each other that has second electrode and extend to form by described second electrode;
Described first extension electrode and described second extension electrode intert successively alternately.
2. electric capacity as claimed in claim 1 is characterized in that: leave the gap between described first extension electrode and described second extension electrode.
3. electric capacity as claimed in claim 2 is characterized in that: the width in each gap that forms between described first extension electrode and described second extension electrode equates.
4. electric capacity as claimed in claim 1 is characterized in that: the material of described first electrode structure and described second electrode structure is aluminium or copper.
5. electric capacity as claimed in claim 1 is characterized in that: described body silicon comprises:
At the bottom of the backing;
The insulating barrier that on the surface at the bottom of the described backing, forms;
The trench oxide that on described insulating barrier, forms;
The polysilicon layer that on described trench oxide, forms;
The dielectric layer that above described polysilicon, forms.
6. electric capacity as claimed in claim 5 is characterized in that: be silicon at the bottom of the described backing.
7. electric capacity as claimed in claim 5 is characterized in that: described insulating barrier is an oxide layer.
8. electric capacity as claimed in claim 7 is characterized in that: described oxide layer is a silicon dioxide.
9. electric capacity as claimed in claim 5 is characterized in that: described polysilicon layer is CoSi.
10. one kind according to claim 1 based on the manufacture method of the electric capacity of body silicon, it is characterized in that, comprises step:
At the bottom of forming backing on the wafer;
On the surface at the bottom of the described backing, form insulating barrier;
On described insulating barrier, form groove;
Deposition forms trench oxide in described groove;
On described trench oxide surface, form polysilicon;
Above described polysilicon, form dielectric layer;
Depositing metal layers on described dielectric layer;
The etched portions metal level makes the remainder metal level form described electric capacity.
CN2010101984353A 2010-06-11 2010-06-11 Bulk silicon based capacitor and manufacturing method thereof Pending CN101908564A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2010101984353A CN101908564A (en) 2010-06-11 2010-06-11 Bulk silicon based capacitor and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2010101984353A CN101908564A (en) 2010-06-11 2010-06-11 Bulk silicon based capacitor and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN101908564A true CN101908564A (en) 2010-12-08

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010101984353A Pending CN101908564A (en) 2010-06-11 2010-06-11 Bulk silicon based capacitor and manufacturing method thereof

Country Status (1)

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CN (1) CN101908564A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5631186A (en) * 1992-12-30 1997-05-20 Samsung Electronics Co., Ltd. Method for making a dynamic random access memory using silicon-on-insulator techniques
US20030148578A1 (en) * 2002-02-07 2003-08-07 Ku Joseph W. Method and apparatus for building up large scale on chip de-coupling capacitor on standard CMOS/SOI technology
CN101692455A (en) * 2009-10-13 2010-04-07 上海宏力半导体制造有限公司 SOI-based capacitor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5631186A (en) * 1992-12-30 1997-05-20 Samsung Electronics Co., Ltd. Method for making a dynamic random access memory using silicon-on-insulator techniques
US20030148578A1 (en) * 2002-02-07 2003-08-07 Ku Joseph W. Method and apparatus for building up large scale on chip de-coupling capacitor on standard CMOS/SOI technology
CN101692455A (en) * 2009-10-13 2010-04-07 上海宏力半导体制造有限公司 SOI-based capacitor

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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING

Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI

Effective date: 20140514

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Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399

Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Address before: 201203 Shanghai Guo Shou Jing Road, Zhangjiang hi tech Park No. 818

Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai

C12 Rejection of a patent application after its publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20101208