CN101902626B - Bit stream buffer controller and its control method - Google Patents

Abstract

The present invention provides a bit stream buffer controller for a video decoder, which includes a first first-in-first-out buffer, a second first-in-first-out buffer and an interrupt controller. The first first-in-first-out buffer is used to store an input bit stream, and the second first-in-first-out buffer is used to store a valid load, wherein the valid load is taken from the input bit stream, and the interrupt controller generates an interrupt signal according to the full status of the first first-in-first-out buffer and the second first-in-first-out buffer, so that each time the valid load is loaded, the video decoder can switch to load the valid load without checking the full status.

Description

Bit stream buffer controller and its control method

technical field

The present invention relates to a video decoder, in particular to a bit stream buffer controller for H.264/AVC decoder and its control method.

Background technique

First-in-first-out buffers are usually used in bitstream controllers of video decoders for temporary storage and flow control, and are often used as circular queues for reading and writing pointers. The previous read and write pointers are all at the same memory location, and the FIFO queue is empty. As usual, the video decoder must first ask the FIFO empty status to ensure the correctness of the stored data each time the data is read, so Reduce the efficiency of the video decoder.

Therefore, there is a current need to provide a bitstream buffer controller that can reduce unnecessary queues of FIFO states in video decoders.

Contents of the invention

The present invention provides an efficient bitstream buffer controller with a variable bitstream empty state checking module.

A bit stream buffer controller for a video decoder, comprising a first FIFO buffer, a second FIFO buffer and an interrupt controller, the first FIFO buffer is used to store an input bit stream, A second FIFO buffer is used to store a payload, wherein the payload is obtained from the input bitstream, and the interrupt controller is based on the full status of the first FIFO buffer and the second FIFO buffer (fullness status) to generate an interrupt signal so that each time the payload is loaded, the video decoder can switch without checking the fullness status to load the payload.

A bit stream buffer control method for a video decoder, comprising: receiving and storing an input bit stream of a first FIFO buffer, obtaining and storing a payload, the payload being taken from a second FIFO buffer The input bit stream in, and according to the full status of the first FIFO buffer and the second FIFO buffer, an interrupt signal is generated, so that the video decoder switches between checked mode and unchecked mode to load The payload, so that the frequency of checking the full state can be reduced.

By generating appropriate interrupt signals and maintaining SW function pointers, the present invention helps to allow the processor to check the status of the pointers whenever an interrupt is triggered, that is, the bitstream can be accessed without confirming the status of the FIFO buffers , to achieve the effect of improving the efficiency of the process.

The foregoing paragraphs have briefly described the features and technical advantages of the present invention. In order to understand the details of the present invention more clearly, other features and advantages of the present invention are disclosed in the following specification

Description of drawings

The following provides a brief description of the accompanying drawings and accompanying drawings, thereby more completely disclosing the details and advantages of the present invention:

FIG. 1 is a block diagram showing the configuration of a bit stream buffer controller related to one embodiment of the present invention.

FIG. 2 is a block diagram showing details of control signals and data streams for the bitstream buffer controller of FIG. 1 .

FIG. 3 is a flowchart showing the operation of the bitstream buffer controller of FIG. 1 .

[Description of main component symbols]

100 bit stream buffer controller

101 video codec

102 external memory

103 memory interface

104 bit stream FIFO buffer

105 process manager

107 Packetized basic bitstream parser

108 Parser for Network Abstraction Layer Units to Raw Byte Sequence Payloads

109 Raw Byte Sequence Load FIFO Buffer

110 interrupt controller

112 Bitstream Manager

201 bit stream buffer controller

202 multiplexer

301, 302, 303, 304, 305 steps

Detailed ways

The following related descriptions of the embodiments of the present invention relate to the accompanying drawings of the present invention.

FIG. 1 is a block diagram showing the configuration of a bitstream buffer controller 100 according to an embodiment of the present invention. The bitstream buffer controller 100 can avoid unnecessary checking of the empty state of the first-in first-out buffer, such as applied in H.264 /AVC decoder.

The bitstream buffer controller 100 includes a memory interface 103, a bitstream first-in-first-out buffer (BSB FIFO; Bit-stream Buffer First-in First-Out) 104, a process manager 105, a packetized elementary bitstream parser (PES parser; Packetized Elementary Stream Parser) 107, network abstraction layer unit to raw byte sequence load (NALU2RBSP; Network AbstractLayer Unit to Raw Byte Sequence Payload) parser 108, raw byte sequence load first-in-first-out buffer (RBSP FIFO; Raw Byte Sequence Packet First-in First-Out) 109, interrupt controller 110 and bit stream manager 112. The bit stream buffer controller 100 is used for receiving the bit stream, and the bit stream is either a packetized basic bit stream form or a basic bit stream form, such as an external memory 102, and the bit stream buffer controller 100 is also used for outputting an interrupt signal, This enables the video decoder 101 to take the bitstream in checked mode or unchecked mode and store it in the RBSP FIFO 109. In check mode, every time video decoder 101 loads the raw byte sequence payload stored in RBSPFIFO 109, video decoder 101 checks the fullness of RBSP FIFO 109; conversely, in unchecked mode, every time When the video decoder 101 loads the raw byte sequence payload stored in the RBSP FIFO 109, the video decoder 101 does not check the fullness of the RBSP FIFO 109.

Assuming that the external memory 102 provides a bit stream, the memory interface 103 is connected to the external memory 102 with the BSB FIFO 104, and the process manager 105 controls the BSB FIFO 104 to load the bit stream, and the bit stream is either an elementary bit stream form or a packetized elementary bit stream form, wherein the bitstream is loaded from the external memory 102 via the memory interface 103 . In addition, the external memory 102 is preferably a double data rate synchronous dynamic random access memory (DDR SDRAM; Double Data RateSynchronous Dynamic Random Access Memory), and the external memory 102 is controlled by a double data rate synchronous dynamic random access memory controller (DDR controller) controlled (not shown). In one embodiment, the BSB FIFO 104 can generate a first indicator that can indicate five different states of the BSB FIFO 104, that is, empty, almost empty, half full, almost full, and full, etc., in a In alternative embodiments, the first indicator may indicate more or fewer kinds of states of the BSB FIFO 104.

The packetized elementary bit stream parser 107 is used for: if the bit stream stored in the BSB FIFO 104 is a packetized elementary bit stream form, then the packetized elementary bit stream parser 107 is stored in the BSB FIFO 104 The bitstream takes an elementary bitstream form payload; in alternative embodiments, the packetized elementary bitstream parser 107 can also bypass this if the bitstream stored in the BSB FIFO 104 is in the form of a packetized elementary bitstream The input bitstream goes to the next stage, which is the parser 108 of NALU2RBSP. In this embodiment, the packetized elementary bit stream parser 107 can also obtain the information of the presentation time stamp (PTS; Presentation Time Stamp) in the bit stream of the packetized elementary bit stream form for subsequent video decoding process.

After the packetized elementary bitstream parser 107, the parser 108 of NALU2RBSP is used to remove the emulation prevention three bytes (0*00_00_03) of the payload in the elementary bitstream form, where the elementary bitstream form The emulation prevention 3 bytes of the payload is obtained by the packetized elementary bit stream parser 107, or the parser 108 of NALU2RBSP is used to remove the emulation prevention 3 bytes of the elementary bit stream form bit stream stored in the BSB FIFO 104 section to get the raw byte sequence payload.

The RBSP FIFO 109 is used to load the original byte sequence load obtained by the parser 108 of NALU2RBSP. In this embodiment, the RBSP FIFO 109 can generate a second index, which can indicate five different states of the RBSP FIFO 109, That is, empty, almost empty, half full, almost full, and full states, etc. In alternative embodiments, this first indicator may indicate more or fewer kinds of states of the RBSP FIFO 109.

In addition, the bitstream manager 112 is used to untransform the original byte sequence payload stored in the RBSP FIFO 109 for the video decoder 101 according to the syntax specification.

The interrupt controller 110 is used to reduce the unnecessary check FIFO process of the video decoder 101. In this embodiment, the interrupt controller 110 is used to generate an interrupt signal so that the video decoder 101 is in the check mode or not checked. mode to load the raw byte sequence load stored in the RBSP FIFO 109. Like this example, the interrupt signal can be a [empty] interrupt signal to switch the video decoder 101 to the inspection mode to load the original byte sequence load stored in the RBSP FIFO 109; or the interrupt signal can be a [full] The interrupt signal is used to switch the video decoder 101 to unchecked mode to load the raw byte sequence payload stored in the RBSP FIFO 109.

In the example of the [empty] interrupt signal, the interrupt controller 110 is used to detect whether the state indicators of the BSB FIFO 104 and the RBSP FIFO 109 reach the preset empty configuration (empty configuration), as in this example, the preset empty group The state can be designed as the first indicator of the almost empty BSB FIFO 1045, and the second indicator of the almost empty RBSP FIFO 109, only when the interrupt controller 110 receives the status indicators of the BSBFIFO 104 and RBSP FIFO 109, and confirms that the preset is satisfied When the empty configuration of RBSP FIFO 109 is stored, the video decoder 101 can switch to the inspection mode to load the raw byte sequence payload. In another alternative embodiment about the [full] interrupt signal, the interrupt controller 110 is used to detect whether the state indicators of the BSB FIFO 104 and the RBSP FIFO 109 reach a preset full configuration (full configuration), as in this example, the The preset full configuration can be designed as the first indicator of the almost full BSBFIFO 1045, and the second indicator of the almost full RBSP FIFO 109, only when the interrupt controller 110 receives the status indicators of the BSB FIFO 104 and RBSP FIFO 109, And when it is confirmed that the preset full configuration is met, the video decoder 101 can switch to an unchecked mode to load the original byte sequence payload stored in the RBSP FIFO 109 . In addition, anyone skilled in the technical field of this invention can understand that: in order to generate interrupt signals and make the BSB FIFO 104 and RBSPFIFO 109 achieve better utilization, the preset interrupt configurations can be designed separately.

By appropriately switching the video decoder 101 to unchecked mode to load the raw byte sequence load stored in the RBSPFIFO 109, thus reducing the frequency of querying the FIFO status, with the help of the interrupt controller 101 and the BSB FIFO 104 and The utilization rate of the RBSP FIFO 109, so the performance of the video decoder 101 can be greatly improved.

FIG. 2 is a block diagram showing details of control signals and data streams for the bit stream buffer controller 100 of FIG. 1. In addition, for example, the process manager 105 of FIG. The detailed features of the multiplexer 202 are disclosed as follows.

The bit stream buffer controller 201 adjusts the access rate so that the BSB FIFO 104 is a full state, the bit stream buffer controller 201 generates a control protocol for the memory interface 103, and then loads the bit stream from the external memory 102 to the BSB FIFO 104, and the bit stream buffer controller 201 The bitstream is either in the form of a packetized elementary bitstream or in the form of an elementary bitstream. If the status indicator of BSB FIFO 104 becomes full or almost full, bitstream buffer controller 201 will stop loading bitstream from external memory 102 to BSB FIFO 104 based on the control protocol, and if the status indicator of BSB FIFO 104 becomes half Full, almost empty or empty, the bitstream buffer controller 201 will request to load the bitstream from the external memory 102 to the BSB FIFO 104 based on the control protocol.

The multiplexer 202 is connected to the BSB FIFO 104 or the packetized basic bit stream parser 107 with the parser 108 of NALU2RBSP. As mentioned above, when the input bit stream is a packetized basic bit stream form, the multiplexer 202 will have a packetized The basic bit stream form bit stream of the packetized basic bit stream form is stored in the BSB FIFO 104 to flow through the packetized basic bit stream parser 107, and then obtains the basic bit stream form payload, and then enters the NALU2RBSP Parser 108 to obtain raw byte sequence payload. In an alternative embodiment, when the input bitstream is in elementary bitstream form, multiplexer 202 will have elementary bitstream form bitstream stored in BSB FIF 104 and streamed directly into NALU2RBSP's Parser 108 to obtain raw byte sequence payload. Furthermore, the packetized elementary bitstream parser 107 is used to obtain the elementary bitstream form payload from the bitstream stored in the BSB FIFO 104, and the parser 108 of NALU2RBSP is used to remove the emulation prevention of the elementary bitstream form payload 3 bytes, wherein the emulation prevention 3 bytes of the elementary bit stream form payload is obtained by the packetized elementary bit stream parser 107, or directly stored in the BSB FIFO 104 to obtain the original byte sequence payload, the above The technical features are similar to those disclosed in FIG. 1 . The multiplexer 202 is used for: if the status indicator of the second FIFO buffer 109 becomes almost full or full, the multiplexer 202 will abort the loading of the basic bit stream payload to the parser 108 of the NALU2RBSP to obtain the second FIFO The raw byte sequence payload for storage in the output buffer 109, and if the status indicator of the second FIFO buffer 109 becomes half full, almost empty or empty, the multiplexer 202 requires the basic bit stream payload to be loaded into The parser 108 of NALU2RBSP obtains the raw byte sequence payload for storage in the second FIFO buffer 109 .

The bitstream manager 112 reads the raw byte sequence payload stored in the RBSP FIFO 109, and untransforms the raw byte sequence payload stored in the RBSP FIFO 109 for the video decoder 101 according to the syntax specification.

In addition to storing the packetized elementary bit stream/bit stream in the form of elementary bit stream and the original byte sequence load, the BSB FIFO 104 and RBSP FIFO 109 here are used to mark the bit stream according to different purposes, and generate their respective Possesses a status indicator (eg empty, almost empty, half full, almost full or full status) to indicate its full status. The status indicators of the BSB FIFO 104 and the RBSP FIFO 109 can be transmitted and received by the interrupt controller 110, and are used to generate an interrupt signal based on a preset interrupt configuration, such as an [empty] interrupt signal or a [full] interrupt signal, Wherein the preset interrupt configuration can be a preset empty configuration or a preset full configuration, so that the video decoder 101 can switch between checked mode or unchecked mode to load the original bytes stored in the RBSP FIFO 109 sequence load. In a similar embodiment, any person skilled in the technical field of this invention can understand that: in order to generate the interrupt signal and make the BSB FIFO 104 and the RBSP FIFO 109 can achieve better utilization, the preset interrupt configuration can be respectively Don't design.

By appropriately switching the video decoder 101 to unchecked mode to load the raw byte sequence load stored in the RBSPFIFO 109, thus reducing the frequency of querying the FIFO status, with the help of the interrupt controller 101 and the BSB FIFO 104 and The utilization rate of the RBSP FIFO 109, so the performance of the video decoder 101 can be greatly improved.

FIG. 3 is a flowchart showing the operation of the bitstream buffer controller 100 of FIG. 1 .

Regarding step 301, the bitstream buffer controller 100 is in an initial state, where the input bitstream is stored in the BSB FIFO 104, the raw byte sequence load from the input bitstream is stored in the RBSP FIFO 109, and the video decoder 101 is to load the original byte sequence load stored in the RBSPFIFO 109 in the check mode, that is to say, when the video decoder 101 loads the original byte sequence load stored in the RBSP FIFO 109, the video decoder 101 must be loaded every To check the full status indicator of the RBSP FIFO 109, for example, the bitstream can be loaded through the memory interface. In addition, the process of loading the input bit stream into the BSB FIFO 104 can be suspended or requested according to the full state of the BSB FIFO 104, and the process of loading the extracted raw byte sequence load into the RBSP FIFO 109 can also be based on the full state of the RBSP FIFO 109 be suspended or required. Additionally, if the input bitstream is in the form of a packetized elementary bitstream, the input bitstream stored in the BSB FIFO 104 can be parsed to obtain the elementary bitstream form payload, the input elementary bitstream form bitstream or the retrieved elementary bitstream The bitstream form payload can be parsed to obtain the raw byte sequence payload for storage in the RBSPFIFO 109.

Regarding step 302, the interrupt controller 110 of the bitstream buffer controller 100 detects the full status of the BSB FIFO 104 and the RBSP FIFO 109.

Regarding step 303, the interrupt controller 110 detects whether the full state of the BSB FIFO 104 and the RBSP FIFO 109 meets a preset interrupt configuration, such as a preset [empty] interrupt configuration or a preset [full] interrupt configuration.

Next, the video decoder 101 switches between unchecked mode and checked mode to load the raw byte sequence payload stored in the RBSP FIFO 109, thereby reducing the frequency of querying the FIFO status. For example, at step 304, when the interrupt controller 110 detects that the full state of the BSB FIFO 104 and the BSP FIFO 109 satisfies the preset interrupt configuration, the video decoder 101 loads the stored in the RBSP FIFO 109 in an unchecked mode. Raw byte sequence load; Conversely, at step 305, when interrupt controller 110 detects that the full state of BSB FIFO 104 and BSP FIFO 109 does not meet the default interrupt configuration, video decoder 101 loads and stores in check mode Raw byte sequence payload in RBSP FIFO 109. The foregoing preset interrupt configuration can be a preset [empty] interrupt configuration, a preset [full] interrupt configuration, or be separately designed to generate interrupt signals, so that the BSB FIFO 104 and the RBSP FIFO 109 can achieve better utilization.

Then get back to step 302 and step 303, where the interrupt controller 110 of the bit stream buffer controller 100 detects the full state of the BSB FIFO 104 and the RBSP FIFO 109 again, and detects whether the state indicators of the BSBFIFO 104 and the RBSP FIFO 109 meet the predetermined condition Set interrupt configuration.

Properly switching between unchecked mode and checked mode by the video decoder 101 to load the raw byte sequence load stored in the RBSP FIFO 109, thus reducing the frequency of querying the FIFO status and having the interrupt controller 101 Helping and utilization of BSB FIFO 104 and RBSP FIFO 109, so the performance of video decoder 101 can be greatly improved.

Finally, those skilled in the technical field of this invention will understand that the above descriptions and embodiments are only preferred embodiments and implementation details for demonstration and disclosure of the present invention, and are not intended to limit the scope of the present invention. Those skilled in the art should understand that some changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined in the appended claims.

Claims (14)

1. A bitstream buffer controller for a video decoder, comprising: a first-in-first-out buffer for storing the input bit stream; a second FIFO buffer for storing payloads, wherein the payloads are obtained from the input bitstream; and The interrupt controller is used to track the first state index of the first FIFO buffer and the second state index of the second FIFO buffer, and when according to the first FIFO buffer and the second An interrupt signal is generated when the first and second state indicators of the FIFO buffer meet a preset condition, so that the video decoder operates in the first operation mode and the second operation mode for the payload from the second FIFO buffer. Loading in one of, wherein, whenever the video decoder loads a payload from a second FIFO buffer in the first mode of operation, the video decoder checks the second status indicator, whenever the video decodes When the payload from the second FIFO buffer is loaded with the second mode of operation, the video decoder does not check the second status indicator, and the video decoder responds to the interrupt signal in the first mode of operation and the second mode of operation Switch between operating modes. 2. The bit stream buffer controller as claimed in claim 1, wherein the video decoder is an H.264/AVC decoder, the first FIFO buffer is a bit stream FIFO buffer, and the second FIFO buffer is a FIFO buffer for raw byte sequence loads. 3. The bit stream buffer controller as claimed in claim 2, further comprising: a packetized elementary bit stream parser, if the input bit stream is a packetized elementary bit stream form, the packetized elementary bit stream parses a parser to obtain primitive bitstream form payloads from the input bitstream stored in the bitstream FIFO buffer; and a parser of network abstraction layer units to raw byte sequence payloads, if the input bitstream is packetized elementary bitstream form, then the NAL unit to raw byte sequence payload parser obtains the raw byte sequence payload from the elementary bitstream form payload output by the packetized elementary bitstream parser, if the input bitstream is In elementary bitstream form, the NAL-to-raw byte-sequence payload parser obtains the raw byte-sequence payload from the bitstream in elementary bitstream form stored in the bitstream FIFO buffer. 4. The bit stream buffer controller as claimed in claim 2, further comprising a process manager, to control the loading of the input bit stream into the bit stream FIFO buffer and the original byte sequence load FIFO buffer process. 5. The bit stream buffer controller as claimed in claim 4, wherein the process manager comprises a bit stream buffer controller and a multiplexer, and the bit stream buffer controller can be based on the first bit stream first-in-first-out buffer status indicator for aborting and requesting the input bitstream to load the bitstream FIFO, and the multiplexer for aborting and requesting The raw byte sequence load is loaded into the raw byte sequence load first-in-first-out buffer. 6. The bitstream buffer controller of claim 2, further comprising a memory interface connected to the input bitstream stored in the bitstream FIFO buffer. 7. The bitstream buffer controller of claim 2, further comprising a bitstream manager for untransforming the original byte sequence payload according to the syntax specification. 8. The bit stream buffer controller as claimed in claim 2, wherein when the first state index of the bit stream FIFO buffer and the second state index of the original byte sequence load FIFO buffer meet the preset When the interrupt is configured, the interrupt controller is used to generate an interrupt signal to switch the video decoder to the first operation mode. 9. A bitstream buffering control method for a video decoder, comprising: receiving and storing an input bitstream of a first FIFO buffer; obtaining and storing in a second FIFO buffer the payload obtained from the input bitstream in the first FIFO buffer; and When the first state index of the first FIFO buffer and the second state index of the second FIFO buffer meet a preset condition, an interrupt signal is generated so that the video decoder switches from the first operating state to the second operating state Two operating states, wherein the video decoder checks the second status indicator whenever the video decoder loads a payload from the second FIFO buffer in the first mode of operation, whenever the video decoder loads the second FIFO buffer The video decoder does not check the second status indicator when loading payloads from the second FIFO buffer in the second mode of operation. 10. The bit stream buffering control method as claimed in claim 9, wherein the video decoder is an H.264/AVC decoder, the first FIFO buffer is a bit stream FIFO buffer, and the second FIFO buffer is a FIFO buffer for raw byte sequence loads. 11. The bit stream buffering control method as claimed in claim 10, further comprising: if the input bit stream is a packetized elementary bit stream form, from the input bit stream stored in the bit stream first-in-first-out buffer obtaining a payload in elementary bitstream form; and obtaining a raw byte sequence payload from the obtained payload in elementary bitstream form or an input bitstream in elementary bitstream form. 12. The bitstream buffering control method as claimed in claim 10, further comprising: suspending and requiring the input bitstream to load the bitstream FIFO buffer according to the first state indicator of the bitstream FIFO; And aborting and requesting the original byte sequence load to load the original byte sequence load FIFO buffer according to the second state indicator of the original byte sequence load FIFO buffer. 13. The bitstream buffer control method as claimed in claim 10, further comprising a step of receiving the input bitstream through a memory interface. 14. The bitstream buffering control method as claimed in claim 10, further comprising a step of outputting the obtained original byte sequence payload according to the syntax specification of the video decoder.

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