A kind of code check method of adjustment of multimedia code stream
Technical field
The present invention relates to digital video technology, particularly a kind of code check method of adjustment of multimedia code stream.
Background technology
Motion picture expert group (Motion Picture Experts Group:MPEG-2) is the international standard that Digital Television adopts, this standard code the compress mode of analog video, audio signal, and defined and be used for the multiplexing data structure of video compression data, audio compression data, control data and private data, comprising: program stream PS (Programme Stream) and transport stream TS (Transport Stream).Wherein transport stream is the long data structure of a kind of fixed packet, is mainly used in the transmission of compressed bit stream.Be generally 188 bytes or 204 bytes, wherein the 1st byte is that the bag sync byte is 0x47H; Low 13 of ensuing the 2nd, 3 bytes is bag sign PID (Packet Identifier), and in order to identify the information category that carries in this packet, such as video data, voice data etc., its basic pack arrangement as shown in Figure 1.
Prior art is made a start at MPEG-2 and is sent the transport stream of cbr (constant bit rate), because the difference of transmission medium or the requirement difference to code check of receiving terminal, thereby the transport stream bad adaptability of cbr (constant bit rate).If the program code check is lower in the transmission code stream, then waste transmission bandwidth, if the transmission code stream code check is too high, surpass the receiving terminal ability to bear, then cause packet loss, can't wait mistake synchronously.
Summary of the invention
The object of the present invention is to provide a kind of code check method of adjustment of multimedia code stream, to solve the problem of the transport stream bad adaptability of cbr (constant bit rate) in the prior art.
For addressing the above problem, the invention provides following proposal:
A kind of code check method of adjustment of multimedia code stream comprises the steps:
Adopt the bag sign of packet in field programmable gate array or other programmable logic chip detected transmission code streams;
After this packet carried out buffer memory by second buffer memory in described field programmable gate array or other programmable logic chips, judge according to described bag sign whether corresponding packet is empty bag, if not the sky bag, then this packet is write the first outer buffer memory of described field programmable gate array or other programmable logic chips, otherwise forbid this sky bag is write described first buffer memory;
When the bit rate output clock is effective, judge the packet that whether has a whole bag in described first buffer memory, if then synchronously read a packet and output from described first buffer memory, otherwise the empty bag storage area of the inside from described field programmable gate array or other programmable logic chips is synchronously exported an empty bag.
When the described first cache writing data bag, be that unit writes, promptly from first byte of this packet with the bag.
Described first buffer memory adopts fifo queue.
The described first buffer memory degree of depth is at least the byte number of two packets.
Whether judge effectively according to the half-full interrupt signal of described first buffer memory whether described first buffer memory has the packet of a whole bag.
It is the hardware configuration processing transmission code stream of core that the present invention adopts with FPGA, have fixing and the fast characteristics of processing speed of postponing in processing such as data write, bag sign PID detection, interrupt responses, treatment effeciency and reliability have been improved, effectively solve the variety of issue that code check does not match and causes, utilized transmission bandwidth fully.
Description of drawings
Fig. 1 is a mpeg 2 transport stream pack arrangement schematic diagram;
Fig. 2 adjusts theory diagram for code check of the present invention;
Fig. 3 is a flow chart of the present invention;
Fig. 4 adjusts functional block diagram for code check.
Embodiment
The present invention adjusts the transmission code stream code check of output by sky bag (promptly bag sign PID is the packet of the 0x1ffH) number of adjusting in the transport stream.The prerequisite of adjusting is that bit rate output must be greater than the effective code check in the input bit rate, and promptly the effective code stream behind the sky bag in removing input code flow must be less than the bit rate output of setting.
Consult shown in Figure 2ly, the present invention adopts First Input First Output (FIFO) to realize the buffer memory of transport stream, i.e. first buffer memory among the figure, and determine to add empty opportunity of wrapping by the state of FIFO, the degree of depth of first buffer memory is at least 2 data packet byte length.PID detects, FIFO control etc. can adopt on-site programmable gate array FPGA (Field Programable Gate Array) or other programmable logic chip to finish, and adopts FPGA in the present embodiment.
Consult Fig. 3 and Fig. 4, specific implementation step of the present invention is as follows:
Step 10: input MPEG-2 transmission code stream.
Step 20: the bag that is detected packet in the input code flow by FPGA identifies PID, is 0x1ffH if wrap sign PID, and then the specified data bag is empty bag, forbids that the write signal of FIFO wraps to abandon sky, otherwise carry out step 30.
Forbid that write signal is in order there not to be the empty bag of transport stream in the data that guarantee to write FIFO.
Because bag sign PID field is the 2nd, 3 bytes in transport stream data packet, for first buffer memory that writes that guarantees that packet can be complete after detection PID field is finished, at inner second buffer memory of realizing minimum 3 bytes of FPGA.
Step 30: write the data packet first buffer memory.
For guarantee with the bag be unit from first buffer memory (FIFO) sense data bag, be that to restart in initial condition or after resetting all must be that sync byte begins to write first buffer memory from first byte of transport stream data packet.
Step 40: when the bit rate output clock is effective, check the state of FIFO, promptly check the packet among the FIFO.
In the present embodiment, whether effectively check by the half-full interrupt signal of judging FIFO and the state of FIFO also can adopt other modes.
Step 50: judge whether half-full interrupt signal is effective, if effectively then represent that FIFO inside has had above half data (promptly having a packet at least) of the FIFO degree of depth, carry out step 60, otherwise it is half-full to show among the FIFO that data also do not arrive, and then carry out step 70.
Step 60: read a packet synchronously from FIFO.
Step 70: from being preset in the synchronous empty bag of output of the inner empty bag storage area of FPGA.
Step 80: output code flow.
The bit rate output clock needs to preestablish according to different situations and demand.
The inventive method is when concrete the application, export the empty bag of interpolation again owing to remove empty bag in input, the packet spacing of the input code flow that can change like this, influence a fundamental clock characteristic (ProgramClock Reference of transport stream, PCR), therefore need adjust PCR, guarantee the correctness of PCR information.