CN101864586B - Electroplating method of lead frame of integrated circuit chip - Google Patents
Electroplating method of lead frame of integrated circuit chip Download PDFInfo
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- CN101864586B CN101864586B CN2010102096937A CN201010209693A CN101864586B CN 101864586 B CN101864586 B CN 101864586B CN 2010102096937 A CN2010102096937 A CN 2010102096937A CN 201010209693 A CN201010209693 A CN 201010209693A CN 101864586 B CN101864586 B CN 101864586B
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Abstract
The invention relates to a processing method of an integrated circuit chip, in particular to an electroplating method of a lead frame of an integrated circuit chip, which comprises the following steps: dividing all unit windows of lead frame makeups arranged in arrays into two staggered groups, and respectively electroplating with a silver layer; shading the second group of unit windows before the first group of staggered unit windows are electroplated; and shading the first group of electroplated unit windows before the second group of staggered unit windows are electroplated. The invention realizes that the unit windows of the positive full-page lead frame makeups are more and the intensity thereof is higher, and thereby, the efficiency of manufacturing operations is improved.
Description
Technical field
The present invention relates to the working method of IC chip; Relate in particular to a process step in a kind of processing and manufacturing of mini-IC chip; It is electric plating method about lead frame; The mini-IC chip relates in particular to four sides does not have the IC of pin flat package (IC chip); This encapsulating structure is QFN (quad flat non-leaded package) by the title of EIAJ's regulation, also can be referred to as LCC encapsulation, PCLC encapsulation, P-LCC encapsulation etc.
Background technology
A kind of encapsulating structure of mini-IC chip, for example QFN (quad flat non-leaded package) encapsulation, promptly four sides do not have the pin flat package, are one of surface attaching type encapsulation.Encapsulate four sides and dispose electrode contacts, because no pin, it is littler than the QFP encapsulation to mount occupied area, and aspect ratio QFP encapsulates low.But, when producing stress between printed base plate and the encapsulation, just can not be eased in the electrode contact position.Therefore electrode contacts is difficult to accomplish that the pin that kind of QFP encapsulation is many, generally about from 14 to 100.Material has pottery and two kinds in plastics.All be ceramic QFN basically when the LCC mark.Electrode contacts width between centers 1.27mm.
And lead frame is as the chip carrier of unicircuit; Be a kind of being electrically connected by means of bonding gold wire realization chip internal circuit leading-out end and outer lead; Form the key structure spare of electric loop; It has played the function served as bridge that is connected with outer lead, all need use lead frame in the semi-conductor integrated package of the overwhelming majority, is base mateiral important in the electronics and information industry.Mainly produce with die stamping method and chemical etching method.
The same with other IC encapsulating structures, the steps necessary of the lead frame of QFP encapsulation before carrying out spun gold welding and encapsulation is exactly to electroplate layer of metal silver on the Copper Foil top layer of lead frame, to increase its electrically conductive rate.In the prior art, because the QFP encapsulation is small, electrode contacts is very approaching, therefore in the design of whole layout, must cell window be strengthened at interval, so the cell window of justifying is few, and is big at interval, all is that symmetry distributes, and production efficient is low.
Summary of the invention
Therefore, the present invention is directed to the deficiency of prior art, propose a kind of utilization and jump the plating principle; In twice electroplating technology, accomplish; Not only avoided repeatedly in crossing liquid, producing unnecessary chemical replacement reaction etc., there is extremely accurate requirement its plating area, reaches in the positive and negative 0.025mm error amount.And solved few, the big at interval deficiency of the cell window of justifying in the prior art, realized that the window of galvanograph is many, intensity is high, improves and makes efficient.
Technical scheme of the present invention is:
The electro-plating method of the lead frame of IC chip of the present invention is: with all cell windows of the lead frame layout of arrayed be divided into staggered 2 groups, electroplate silver layer respectively.Be similar to the chessboard of chess, all cell windows of the lead frame layout of arrayed are divided into 2 groups of black and white grid, after earlier the cell window of black lattice being electroplated, again the cell window of white grid is electroplated.
Further, described staggered the 1st group of cell window carry out electroplating processes before, the 2nd group of cell window blocked; Described staggered the 2nd group of cell window carry out electroplating processes before, with the 1st group the electricity clad cell window block.Before promptly electroplating the cell window of black lattice, must the cell window of white grid be blocked; Simultaneously, electroplate the cell window of white grid before, must will be the cell window of electric clad white grid block.
Further, described lead frame layout connects electroplating cathode, and electroplate liquid connects galvanic anode.
Further, described electroplate liquid constantly impacts the cell window that the lead frame layout is not blocked with certain pressure, and electroplates.
Technical scheme of the present invention be adopt staggered plating method with all cell windows of the lead frame layout of arrayed be divided into staggered 2 groups, electroplate silver layer respectively.Like this, the cell window of lead frame layout just can be arranged by array closely, and does not worry having influence on the electrosilvering operation of cell window at interval.Thereby the cell window of having realized the layout of positive justifying lead frame is more, and intensity is higher, improves manufacturing operation efficient.
Description of drawings
Fig. 1 is a schematic flow sheet of the present invention.
Embodiment
Combine accompanying drawing and embodiment that the present invention is further specified at present.
Consult shown in Figure 1ly, the electro-plating method of the lead frame of IC chip of the present invention comprises the steps:
Step 101: the copper coin that blocks the 2nd group of staggered lead frame layout of cell window; The cell window arrayed of lead frame copper coin forms the layout of an integral body.Each cell window arrayed on the lead frame copper coin has the black and white grid of arrayed with regard to the chessboard that is similar to chess; All cell windows of the lead frame layout of arrayed are divided into 2 groups of black and white grid; The cell window of supposing white grid is the 1st group, and black lattice is the 2nd group.All black lattices on the chessboard of chess are blocked, soak into to prevent electroplate liquid.
Step 102: the 1st group of lead frame copper coin that does not block cell window carried out the electrosilvering processing.That is the 1st group of white of all of, not blocking on the chessboard with chess grid carries out the electrosilvering operation to be handled.Preferred electrosilvering handles that can to adopt energising to carry out chemical method silver-plated.
Step 103: the cell window that blocks the 1st group of silver-plated processing.That is, all the 1st group of silver-plated processing on the chessboard of chess white grid blocked, stay the 2nd group of black lattice.
Step 104: the 2nd group of not silver plated cell window in the lead frame copper coin carried out electrosilvering handle.That is, all the 2nd group of black lattices on the chessboard of chess being carried out the electrosilvering operation handles.Be that to adopt energising to carry out chemical method silver-plated equally.
Although specifically show and introduced the present invention in conjunction with preferred embodiment; But the those skilled in the art should be understood that; In the spirit and scope of the present invention that do not break away from appended claims and limited; Can make various variations to the present invention in form with on the details, be protection scope of the present invention.
Claims (3)
1. the electro-plating method of the lead frame of an IC chip is characterized in that: all cell windows of the lead frame layout of arrayed are divided into staggered 2 groups, electroplate silver layer respectively; Specifically: described staggered the 1st group of cell window carry out electroplating processes before, the 2nd group of cell window blocked; Described staggered the 2nd group of cell window carry out electroplating processes before, with the 1st group the electricity clad cell window block.
2. the electro-plating method of the lead frame of IC chip according to claim 1 is characterized in that: described lead frame layout connection electroplating cathode, electroplate liquid connection galvanic anode.
3. the electro-plating method of the lead frame of IC chip according to claim 2, it is characterized in that: described electroplate liquid constantly impacts the cell window that the lead frame layout is not blocked with certain pressure, and electroplates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102096937A CN101864586B (en) | 2010-06-25 | 2010-06-25 | Electroplating method of lead frame of integrated circuit chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102096937A CN101864586B (en) | 2010-06-25 | 2010-06-25 | Electroplating method of lead frame of integrated circuit chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101864586A CN101864586A (en) | 2010-10-20 |
| CN101864586B true CN101864586B (en) | 2012-09-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010102096937A Expired - Fee Related CN101864586B (en) | 2010-06-25 | 2010-06-25 | Electroplating method of lead frame of integrated circuit chip |
Country Status (1)
| Country | Link |
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| CN (1) | CN101864586B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111850643A (en) * | 2020-08-04 | 2020-10-30 | 天水华洋电子科技股份有限公司 | Electroplating method of lead frame |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1381260A1 (en) * | 2002-07-11 | 2004-01-14 | Ultratera Corporation | Method of plating connecting layers on a conductor pattern of a printed circuit board (PCB) |
| CN1529545A (en) * | 2003-09-29 | 2004-09-15 | 威盛电子股份有限公司 | Selective electroplating method |
| CN201439545U (en) * | 2009-05-22 | 2010-04-21 | 上海新阳半导体材料股份有限公司 | Parcel plating device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11293489A (en) * | 1998-04-10 | 1999-10-26 | Hitachi Cable Ltd | Equipment for continuous plating of both sides of lead frame |
-
2010
- 2010-06-25 CN CN2010102096937A patent/CN101864586B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1381260A1 (en) * | 2002-07-11 | 2004-01-14 | Ultratera Corporation | Method of plating connecting layers on a conductor pattern of a printed circuit board (PCB) |
| CN1529545A (en) * | 2003-09-29 | 2004-09-15 | 威盛电子股份有限公司 | Selective electroplating method |
| CN201439545U (en) * | 2009-05-22 | 2010-04-21 | 上海新阳半导体材料股份有限公司 | Parcel plating device |
Non-Patent Citations (1)
| Title |
|---|
| JP特开平11-293489A 1999.10.26 |
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| Publication number | Publication date |
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| CN101864586A (en) | 2010-10-20 |
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