CN101846858B - Array substrate and manufacturing method thereof - Google Patents
Array substrate and manufacturing method thereof Download PDFInfo
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- CN101846858B CN101846858B CN 200910081011 CN200910081011A CN101846858B CN 101846858 B CN101846858 B CN 101846858B CN 200910081011 CN200910081011 CN 200910081011 CN 200910081011 A CN200910081011 A CN 200910081011A CN 101846858 B CN101846858 B CN 101846858B
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- base palte
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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Abstract
The invention relates to the technology of liquid crystal display, in particular to an array substrate and a manufacturing method thereof. The array substrate comprises an effective area of a display frame and a soldering-pan area for providing pixel signals for the effective area, wherein the soldering-pan area comprises a test signal wire and a connector wire for testing; the connector wire for the testing comprises a first part of which one end is electrically connected with the test signal wire and a second part of which one end is electrically connected with a first signal wire or a second signal wire of the effective area; the other end of the first part and the other end of the second part are separated at intervals; and the connector wire for the testing also comprises a connection part for connecting the other end of the first part with the other end of the second part electrically. The invention also provides a method for manufacturing the array substrate. Compared with the prior art, the manufacturing method has no pollution problems of metal particles generated when metal wires are cut by lasers, and thus the yield and production efficiency are improved.
Description
Technical field
The present invention relates to lcd technology, particularly a kind of array base palte and manufacturing approach thereof.
Background technology
Liquid crystal indicator (Liquid Crystal Display; Be called for short: be to show various pictures LCD) through the light transmission rate that is controlled at the liquid crystal pixel of arrayed on the liquid crystal panel.The chip for driving of generally using the driving liquid crystal panel is crimped on thin-film transistor LCD device (Thin Film TransistorLiquid Crystal Display; Be called for short: TFT LCD) method on the panel has three kinds: lead-in wire bonding (Wire Bonding; Be called for short: WB) mode, strip-like carrier crimping (Tape Automated Bonding; Be called for short: TAB) mode and chip vertical compression (Chip On Glass; Be called for short: mode COG).In the manufacturing process of liquid crystal panel,, flow to follow-up technology, carry out array base palte test (Array Test) to prevent bad panel in order before processing liquid crystal nuclear, to detect bad panel earlier.When being suitable for the manufacturing process of COG mode, adopt usually and carry out earlier signal wire all being coupled together through connecting line before the array base palte test, wait after the array base palte EOT method of breaking off signal wire with the method for cut again.But in the time of with cut gate line or data line metal, can produce metallic particles, form pollute, and such process influence of cut operating speed, reduced production efficiency.
In order to reduce the operation of cut, the whole bag of tricks has been proposed.For example: in Korean Patent KR2005-0110745, propose a kind of on gate line or data line additional design thin film transistor (TFT) (ThinFilm Transistor; Hereinafter to be referred as: TFT) switch, the grid of TFT all connect together and control its on off state with a switching signal.Like this, only need add the unlatching signal in the time of the array base palte test and open switch, also not need particular processing after the test.But grid/data line connects through TFT side by side, even sometimes actual signal has broken off also and can cause distorted signals because of bottom generation leakage current backlight, and when making large-scale panel, has the problem that is suitable for difficulty because need to design big TFT.
Other a kind of method is disclosed in Korean Patent KR2005-0003511.At the outermost design connecting line of panel, all gate lines or data line all vertically are connected on the connecting line, in polishing (Grinding) technology, eliminate connecting line at last, so just need not increase extra technology.But this method is being crimped on chip for driving in the process of panel, and owing to suppressing of crimping chip, COG crimping pad has problem of short-circuit with being connected with cabling of cabling below it.
Summary of the invention
The object of the present invention is to provide a kind of array base palte and method thereof, can solve the pollution problem that the available technology adopting laser cutting parameter produces, thereby improve productive rate and production efficiency.
Array base palte of the present invention, effective coverage that comprises display frame and the welding disking area that is used for providing picture element signal to the effective coverage; Said effective coverage comprises: with first metal first signal wire, the on-off element that is electrically connected with the second metal secondary signal line, with said first signal wire and said secondary signal line and the pixel electrode that is driven by said on-off element; Said welding disking area also comprises: the test signal line; Connecting line is used in test, is electrically connected with the signal wire of effective coverage; Said test comprises with connecting line: the second portion that first that an end and test signal line are electrically connected and first signal wire of an end and said effective coverage or secondary signal line are electrically connected; The other end of said first and the second portion segment distance of being separated by is oppositely arranged; Said test also comprises the connecting portion that the other end of the other end that makes said first and said second portion is electrically connected with connecting line.
Array base palte of the present invention is compared with prior art realized the array base palte test operation of shutoff signal line afterwards through array base palte technology; Saved the operation of cut signal wire; Thereby the metallic particles pollution problem that has produced when having avoided the laser cut metal line has improved productive rate and production efficiency.This array base palte need not design the TFT structure, does not have the problem of distorted signals, also the cabling problem of short-circuit can not occur in the time of the chip for driving crimping.
The present invention provides a kind of manufacturing approach of array base palte, and said array base palte comprises effective coverage that display frame is used and the welding disking area of providing signal to use for said effective coverage, comprising:
The opaque conductive layer of deposition on glass substrate;
Utilize composition technology to form the pattern of opaque conductive layer; The pattern of said opaque conductive layer comprises to said effective coverage provides first signal wire of signal and the test signal line in the said welding disking area to use connecting line with test; Said test comprises the second portion that first signal wire of first that an end and test signal line are electrically connected and an end and effective coverage is electrically connected with connecting line, and the other end of said first and the other end of the second portion segment distance of being separated by is oppositely arranged;
Depositing insulating layer on the glass substrate of the pattern of accomplishing said opaque conductive layer;
The via hole that the test that utilizes composition technology to form to make said welding disking area is exposed with the other end of the other end of the first of connecting line and second portion;
Deposit transparent conductive layer on the glass substrate of accomplishing the via hole on the said insulation course;
Utilize composition technology etching transparency conducting layer, form the pattern of the connecting portion that the pixel electrode in the said effective coverage is connected with the other end that on the via hole of said welding disking area, makes said test with the other end of the first of connecting line and second portion.
The array base palte that manufacturing approach through array base palte of the present invention is made is after the array base palte test, and the test of below composition technology etching transparency conducting layer and via hole, exposing comes the cut-off signal line with connecting line.This method has been saved the operation of cut signal wire, thereby the metallic particles pollution problem that produces when having avoided the laser cut metal line has improved productive rate and production efficiency.And this method need not design the TFT structure, does not have the problem of distorted signals, also the cabling problem of short-circuit can not occur in the time of the chip for driving crimping.
Description of drawings
Fig. 1 is the synoptic diagram of the array base palte first embodiment welding disking area of the present invention;
Fig. 2 be among Fig. 1 A-A ' to sectional view;
Fig. 3 is the synoptic diagram of the array base palte second embodiment welding disking area of the present invention;
Fig. 4 be among Fig. 3 B-B ' to sectional view;
Fig. 5 is the process flow diagram of manufacturing approach first embodiment of array base palte of the present invention;
Fig. 6 is the process flow diagram of manufacturing approach second embodiment of array base palte of the present invention.
Reference numeral:
Connecting line is used in 1-first signal wire or secondary signal line 2-test signal line 3-test
4-insulation course 5-via hole 6-transparency conducting layer
The 7-connecting portion 31-32-of first second portion
Embodiment
Through accompanying drawing and embodiment, technical scheme of the present invention is done further detailed description below.
Array base palte first embodiment
Array base palte comprises the effective coverage and the welding disking area that is used for providing picture element signal to the effective coverage of display frame.The effective coverage comprises with first metal first signal wire, the on-off element that is electrically connected with the second metal secondary signal line, with said first signal wire and said secondary signal line and the pixel electrode that is driven by said on-off element.Fig. 1 is the synoptic diagram of the array base palte first embodiment welding disking area of the present invention, Fig. 2 be among Fig. 1 A-A ' to sectional view.Like Fig. 1, shown in Figure 2, welding disking area comprises: test signal line 2 is used to provide test signal; Test is electrically connected with the signal wire (first signal wire or secondary signal line 1) of effective coverage with connecting line 3, is used to judge the state that is electrically connected of pixel electrode; Via hole 5 is located on the insulation course 4 of test with the connecting line top; Transparency conducting layer 6 is located at the top of via hole, is used to protect test exposed below the via hole with connecting line 3.
Above-mentioned test is made up of material identical with first signal wire of said effective coverage or the material identical with the secondary signal line with connecting line.
Present embodiment is provided with via hole on insulation course, test connects together through via hole 5 and transparency conducting layer 6 with connecting line.Like this; The array base palte of present embodiment can exposed test break off first signal wire or the secondary signal line that originally connected together through test signal line 2 with the method for connecting line 3 below composition technology etching transparency conducting layer 6 and via hole 5 after the array base palte test; Need not do laser cutting parameter; Therefore, the metallic particles pollution problem of having avoided cut to cause has improved productive rate and production efficiency.
Array base palte second embodiment
Array base palte comprises the effective coverage and the welding disking area that is used for providing picture element signal to the effective coverage of display frame.The effective coverage comprises with first metal first signal wire, the on-off element that is electrically connected with the second metal secondary signal line, with said first signal wire and said secondary signal line and the pixel electrode that is driven by said on-off element.Fig. 3 is the synoptic diagram of the array base palte second embodiment welding disking area of the present invention, Fig. 4 be among Fig. 3 B-B ' to sectional view.Like Fig. 3, shown in Figure 4, welding disking area comprises: test signal line 2 is used to provide test signal; Test is electrically connected with the signal wire (first signal wire or secondary signal line 1) of effective coverage with connecting line 3, is used to judge the state that is electrically connected of pixel electrode; Said test comprises first 31 and first signal wire of an end and said effective coverage or the second portion 32 that the secondary signal line is electrically connected that an end and test signal line 2 are electrically connected with connecting line 3; The other end of said first 31 and second portion 32 segment distance of being separated by is oppositely arranged; Said test also comprises the connecting portion 7 that the other end of the other end that makes said first 31 and said second portion 32 is electrically connected with connecting line 3.
Above-mentioned test is made up of the material identical with first signal wire of said effective coverage or also can constitutes by the material identical with the secondary signal line with second portion with the first of connecting line.Above-mentioned test with the connecting portion of connecting line by constituting with the same material of the pixel electrode of effective coverage.
Present embodiment is provided with via hole on insulation course, test is broken off at the via hole place with connecting line, and connects together through connecting portion.Like this, the array base palte of present embodiment can pass through the etching transparency conducting layer after the array base palte test, makes the signal wire that originally connected together through the test signal line break off, and need not do cut.Therefore, the metallic particles pollution problem of having avoided cut to cause has improved productive rate and production efficiency, and compares because of only needing the etching transparency conducting layer can save one procedure with array base palte first embodiment.
Manufacturing approach first embodiment of array base palte
Fig. 5 is the process flow diagram of manufacturing approach first embodiment of array base palte of the present invention.As shown in Figure 5, the manufacturing approach of present embodiment array base palte comprises:
The pattern of opaque conductive layer comprises to the effective coverage provides first signal wire of signal and test signal line and the test in the welding disking area to use connecting line.First signal wire of effective coverage can be whether control provide the gate line of picture element signal to pixel electrode or the data line of picture element signal is provided to pixel electrode.
Technology such as the alleged composition technology of the present invention comprises photoresist coating, mask, exposure, etching, peel off.
The array base palte of the method manufacturing through present embodiment only needs in array base palte test back just can make the signal wire disconnection that originally linked together, the metallic particles pollution problem that need not carry out laser cutting parameter so can avoid the laser cut metal line to cause with transparency conducting layer above the composition technology etching via hole and the test below the via hole with connecting line.Array base palte with the method manufacturing of present embodiment need not design the TFT structure, therefore on large-scale panel, does not have the excessive inapplicable problem of area occupied yet, and does not have the cabling problem of short-circuit chip for driving crimping time yet.
The etching liquid of etching transparency conducting layer is different with the etching liquid of etching signal line, so need carry out twice etching.In order to reduce operation the present invention another kind of preferred version is provided further.
Manufacturing approach second embodiment of array base palte
Fig. 6 is the process flow diagram of manufacturing approach second embodiment of array base palte of the present invention.As shown in Figure 6, the manufacturing approach of the array base palte of present embodiment comprises:
The pattern of opaque conductive layer comprises to the effective coverage provides first signal wire of signal and the test signal line in the welding disking area to use connecting line with test; Said test comprises the second portion that first signal wire of first that an end and test signal line are electrically connected and an end and effective coverage is electrically connected with connecting line, and the other end of said first and the other end of the second portion segment distance of being separated by is oppositely arranged.First signal wire of effective coverage can be whether control provide the gate line of picture element signal to pixel electrode or the data line of picture element signal is provided to pixel electrode.
The via hole that step 604, the test that utilizes composition technology to form to make said welding disking area are exposed with the other end of the other end of the first of connecting line and second portion.
The array base palte of the method manufacturing through present embodiment only needs just can make the signal wire that originally linked together break off the metallic particles pollution problem that need not carry out laser cutting parameter so can avoid the laser cut metal line to cause with the transparency conducting layer above the composition technology etching via hole in array base palte test back.The array base palte of the method manufacturing through present embodiment need not design the TFT structure yet, therefore on large-scale panel, does not have the excessive inapplicable problem of area occupied yet, and does not have the cabling problem of short-circuit chip for driving crimping time yet.The array base palte of comparing with the array base palte of the method manufacturing of manufacturing approach first embodiment of array base palte with the method manufacturing of present embodiment only needs the etching transparency conducting layer just can break off the signal wire that originally linked together in array base palte test back; Can economize operation, improve productive rate.
It should be noted last that; Above embodiment is only unrestricted in order to technical scheme of the present invention to be described; Although the present invention is specified with reference to preferred embodiment; Those of ordinary skill in the art should be appreciated that and can make amendment or be equal to replacement technical scheme of the present invention, and do not break away from the spirit and the scope of technical scheme of the present invention.
Claims (3)
1. the manufacturing approach of an array base palte, said array base palte comprise effective coverage that display frame is used and the welding disking area of providing signal to use for said effective coverage, it is characterized in that, comprising:
The opaque conductive layer of deposition on glass substrate;
Utilize composition technology to form the pattern of opaque conductive layer; The pattern of said opaque conductive layer comprises to said effective coverage provides first signal wire of signal and the test signal line in the said welding disking area to use connecting line with test; Said test comprises the second portion that first signal wire of first that an end and test signal line are electrically connected and an end and effective coverage is electrically connected with connecting line, and the other end of said first and the other end of the second portion segment distance of being separated by is oppositely arranged;
Depositing insulating layer on the glass substrate of the pattern of accomplishing said opaque conductive layer;
The via hole that the test that utilizes composition technology to form to make said welding disking area is exposed with the other end of the other end of the first of connecting line and second portion;
Deposit transparent conductive layer on the glass substrate of accomplishing the via hole on the said insulation course;
Utilize composition technology etching transparency conducting layer, form the pattern of the connecting portion that the pixel electrode in the said effective coverage is connected with the other end that on the via hole of said welding disking area, makes said test with the other end of the first of connecting line and second portion.
2. the manufacturing approach of array base palte according to claim 1 is characterized in that: whether first signal wire of said effective coverage provides the gate line of picture element signal to pixel electrode for control.
3. the manufacturing approach of array base palte according to claim 1 is characterized in that: first signal wire of said effective coverage is for providing the data line of picture element signal to pixel electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910081011 CN101846858B (en) | 2009-03-27 | 2009-03-27 | Array substrate and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910081011 CN101846858B (en) | 2009-03-27 | 2009-03-27 | Array substrate and manufacturing method thereof |
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| CN101846858A CN101846858A (en) | 2010-09-29 |
| CN101846858B true CN101846858B (en) | 2012-05-30 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3336885A4 (en) * | 2015-08-13 | 2019-04-03 | Boe Technology Group Co. Ltd. | NETWORK SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY PANEL, AND DISPLAY APPARATUS |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103383925B (en) | 2013-07-02 | 2015-06-03 | 京东方科技集团股份有限公司 | Display device, signal substrate of naked eye 3D function panel and manufacturing method of signal substrate |
| CN104701327B (en) | 2015-03-20 | 2018-03-02 | 京东方科技集团股份有限公司 | The manufacture method and display device of array base palte, array base palte |
| CN106057782A (en) * | 2016-08-04 | 2016-10-26 | 上海奕瑞光电子科技有限公司 | Antistatic protection structure and reliability improving method of semiconductor panel |
| CN109872983B (en) * | 2019-03-04 | 2020-10-16 | 武汉华星光电技术有限公司 | Test pad |
| CN110208978B (en) * | 2019-07-04 | 2022-10-25 | 京东方科技集团股份有限公司 | Cutting method of display panel intermediate product and display panel |
| CN112018086B (en) * | 2020-07-27 | 2022-03-22 | 惠科股份有限公司 | Shorting bar, manufacturing method thereof, array substrate and display device |
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2009
- 2009-03-27 CN CN 200910081011 patent/CN101846858B/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3336885A4 (en) * | 2015-08-13 | 2019-04-03 | Boe Technology Group Co. Ltd. | NETWORK SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY PANEL, AND DISPLAY APPARATUS |
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| CN101846858A (en) | 2010-09-29 |
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Owner name: JINGDONGFANG SCIENCE AND TECHNOLOGY GROUP CO., LTD Free format text: FORMER OWNER: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY CO., LTD. Effective date: 20150623 Owner name: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY Effective date: 20150623 |
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Effective date of registration: 20150623 Address after: 100015 Jiuxianqiao Road, Beijing, No. 10, No. Patentee after: BOE Technology Group Co., Ltd. Patentee after: Beijing BOE Photoelectricity Science & Technology Co., Ltd. Address before: 100176 Beijing economic and Technological Development Zone, West Central Road, No. 8 Patentee before: Beijing BOE Photoelectricity Science & Technology Co., Ltd. |