CN101320148A - Display substrate, manufacturing method thereof, and display having same - Google Patents

Abstract

The display substrate includes a base substrate having a display area and a peripheral area surrounding the display area, a pixel electrode formed in the display area, a pad portion formed in the peripheral area, a pad portion formed in the peripheral area and having a plurality of The bonding portion of the plurality of holes in the area of the pad portion, and a conductive bonding member formed on the pad portion and the bonding portion to electrically contact the pad portion and the integrated circuit terminal.

Description

Display substrate, manufacturing method thereof, and display having same

technical field

The present invention relates to a display substrate, a method for manufacturing the display substrate and a display device with the display substrate. In particular, the present invention relates to a display substrate having strong reliability, a method of manufacturing the display substrate, and a display device having the display substrate.

Background technique

In general, a display includes a display panel and a driving circuit for driving the display panel. The display panel includes an array substrate. The array substrate includes a plurality of gate lines, a plurality of data lines and a plurality of pixel portions defined by the gate lines and data lines. The drive circuit includes a gate drive circuit for supplying gate signals to the multiple gate lines and a source drive circuit for supplying data signals to the multiple data lines.

The gate driving circuit and the source driving circuit can be mounted on the array substrate in one chip. In current general practice, the gate driving circuit is directly formed on the array substrate to manufacture a display with required features such as thinness. Further, in order to prevent corrosion of the gate driving circuit, a relatively thick organic layer is formed on the gate driving circuit of the array substrate.

In order to mount a source driving circuit on the array substrate, a plurality of pads are formed on the array substrate. Individual pads of the plurality of pads are electrically connected to the lower metal layer through contact holes formed in the organic layer.

During the panel drop test process of the display panel including the array substrate, due to the weak adhesion between the organic layer and the protective layer on the lower metal layer, the protective layer is peeled off from the array substrate. In addition, the source driver circuit is peeled off along the protective layer. As a result, contact defects are formed between the source driving circuit and the pad, thereby reducing driving reliability of the source driving circuit.

Contents of the invention

The present invention provides a display substrate with strong reliability, a method of manufacturing the display substrate, and a display having the display substrate.

In an exemplary embodiment of the present invention, a display substrate includes a base substrate having a display area and a peripheral area surrounding the display area; a pixel electrode formed on the display area; a pad portion formed on the peripheral area; and has a plurality of holes formed on the peripheral region adjacent to the area of the pad portion, and a conductive bond formed on the pad portion and the bonding portion for electrically contacting the pad portion and IC terminal.

The display substrate further includes an organic layer formed under the pixel electrode, a first insulating layer formed on the base substrate, and an organic layer formed on the first insulating layer.

Each of the plurality of holes is formed through a portion of the organic layer in the peripheral region, and a conductive adhesive is bonded to the first insulating layer exposed through the respective hole.

A second insulating layer is formed on the base substrate.

In addition, each of the plurality of holes may be formed through portions of the first insulating layer and the organic layer formed in the peripheral region, and the conductive adhesive may be bonded to the second insulating layer exposed through the respective holes.

Alternatively, each of the plurality of holes may be formed by simultaneous patterning of the first insulating layer and the organic layer formed in the peripheral region, and the display substrate further includes a dummy pattern exposed through each hole.

The display substrate further includes a switching element including a channel layer electrically connected to the pixel electrode formed of the first metal layer, and a source electrode and a drain electrode formed of the second metal layer.

The dummy patterning is formed by patterning the channel layer, or in an alternative exemplary embodiment, by patterning the second metal layer.

Further, the dummy patterning may be a multi-layer structure formed by patterning the channel layer and patterning the second metal layer.

The display substrate further includes a step compensation pattern formed on the base substrate, wherein the step compensation pattern is formed by the patterning of the first metal layer.

Each of the plurality of holes is formed by simultaneous patterning of part of the organic layer, the first insulating layer, and the second insulating layer formed in the peripheral region, and a conductive adhesive is bonded to the second insulating layer exposed through the respective holes.

The pixel electrode includes a transparent electrode and a reflective electrode, and an organic layer may be formed on the reflective electrode.

In an alternative embodiment, the organic layer has a concave pattern and a convex pattern formed thereon.

Further, a first part of the organic layer having a first thickness may be formed in the peripheral region having the pad part, a second part of the organic layer having the second thickness may be formed in the display region on which the pixel electrode is formed, and The second thickness of the second portion of the organic layer may be greater than the first thickness of the first portion of the organic layer.

The display substrate further includes a gate circuit part formed on the peripheral area, and a part of the organic layer formed on the peripheral area may cover the gate circuit part.

In another exemplary embodiment of the present invention, a display substrate includes a base substrate having a display area and a peripheral area surrounding the display area, a pixel electrode formed in the display area, a pad portion formed in the peripheral area, and a peripheral area formed in the peripheral area. And a circuit portion having a plurality of holes formed in a region of the peripheral region adjacent to the pad portion. The circuit section has an integrated circuit ("IC") mounted on the circuit section.

The display substrate further includes a first insulating layer formed on the base substrate, an organic layer formed on the first insulating layer, and a first insulating layer formed between the organic layer and the base substrate.

Each of the plurality of holes is formed through a portion of the organic layer in the peripheral region.

A second insulating layer is formed on the base substrate.

Each of the plurality of holes is formed by portions of the first insulating layer and the organic layer formed in the peripheral region.

A virtual composition can be exposed through each aperture.

The display substrate further includes a switching element including a channel layer electrically connected to the pixel electrode formed of the first metal layer, and a source electrode and a drain electrode formed of the second metal layer.

The dummy patterning is formed by patterning the channel layer or patterning the second metal layer.

The virtual patterning can be a multi-layer structure, and can be formed by patterning the channel layer and patterning the second metal layer.

The display substrate further includes a step compensation pattern formed on the base substrate by patterning the first metal layer.

Each of the plurality of holes is formed by simultaneous patterning of the organic layer, the first insulating layer, and the second insulating layer formed in the peripheral region.

The pixel electrode includes a transparent electrode and a reflective electrode, and an organic layer is formed on the reflective electrode.

The organic layer has a concave pattern and a convex pattern formed thereon.

A first part of the organic layer having a first thickness is formed in a peripheral region having a pad part, a second part of an organic layer having a second thickness is formed in a display region on which a pixel electrode is formed, and a second part of the organic layer The second thickness of the portion is greater than the first thickness of the first portion of the organic layer.

A gate circuit portion may be formed in the peripheral region. A portion of the organic layer formed in the peripheral region covers the gate circuit portion.

In still another exemplary embodiment of the present invention, in a method of manufacturing a display substrate, a base substrate is formed, a switching element is formed in a display area of the base substrate and a pad pattern is formed in a peripheral area surrounding the display area. Then, an organic layer is formed on the base substrate and patterned to form a bonding portion in a region adjacent to the pad pattern. The bonding portion has a plurality of holes formed therein. Then, the pixel electrode is formed and electrically connected to the switching element and the pad electrode is electrically connected to the pad pattern. Then, a conductive adhesive is formed on the pad electrode and the adhesive portion. The conductive adhesive electrically contacts the pad electrodes and the IC terminals.

A first insulating layer may be formed on the base substrate.

A conductive adhesive is bonded to the first insulating layer revealed through each of the plurality of holes.

A second insulating layer is formed on the base substrate.

The forming of the bonding part includes simultaneously patterning the first insulating layer and the organic layer.

A conductive adhesive is bonded to the second insulating layer exposed through the hole.

A gate circuit portion may be formed in the peripheral area.

The organic layer forming step forms a part of the organic layer to cover the gate circuit part.

In another exemplary embodiment of the present invention, a display includes a display panel. The display panel includes: a base substrate; a display substrate formed on the base substrate and having a display area and a peripheral area; an opposite substrate facing the display substrate; a pixel electrode formed in the display area; a pad part formed in the peripheral area; A junction portion is formed in the peripheral region and has a plurality of holes formed in a region of the peripheral region adjacent to the pad portion.

The display further includes a conductive member formed on the pad portion and the bonding portion, and an integrated circuit electrically connected to the pad portion through the conductive member.

The display substrate further includes a first insulating layer formed on the base substrate and a first portion of an organic layer formed under the pixel electrode on the first insulating layer.

Each of the plurality of holes is formed in the peripheral region through a portion of the first portion of the organic layer, and a conductive adhesive is bonded to the first insulating layer exposed through the respective hole.

A second insulating layer is formed on the base substrate.

Each of the plurality of holes is formed through a portion of the first portion of the organic layer and a portion of the first insulating layer in the peripheral region, and a conductive adhesive is bonded to the second insulating layer exposed through the respective hole.

The holes may be formed by simultaneous patterning of the first insulating layer and the organic layer formed in the peripheral region, and the display substrate may further include a dummy pattern exposed by each of the respective holes.

The display optionally includes a switching element including a channel layer electrically connected to the pixel electrode formed of the first metal layer, and source and drain electrodes formed of the second metal layer.

The dummy pattern is formed by patterning the channel layer or by patterning the second metal layer.

The virtual patterning can be a multi-layer structure formed by patterning the channel layer and the second metal layer.

A step compensation pattern may be formed on the base substrate.

The step compensation pattern may be formed by patterning the first metal layer.

Each of the respective holes is simultaneously patterned by the organic layer formed in the peripheral region, the first insulating layer, and the second insulating layer, and a conductive adhesive is bonded to the second insulating layer exposed through the respective holes.

The pixel electrodes include transparent electrodes and reflective electrodes. A first portion of the organic layer may be formed on the reflective electrode.

A convex pattern and a concave pattern may be formed on the first portion of the organic layer.

A light-transmitting hole may be formed in the color filter layer, wherein the light-transmitting hole is formed on the reflective electrode.

The opposite electrode further includes a second organic layer formed on the reflective electrode of the pixel electrode on the display area of the display substrate.

A first portion of the first portion of the organic layer having a first thickness is formed in the peripheral region having the pad portion, a second portion of the organic layer having a second thickness is formed in the display region on which the pixel electrode is formed, and the organic layer The second thickness of the first portion of the second portion is greater than the first thickness of the first portion of the first portion of the organic layer.

In the display substrate, the method of manufacturing the display substrate, and the display having the display substrate according to an exemplary embodiment of the present invention, the bonding portion is formed adjacent to the pad portion, so that the gap between the pad portion and the IC terminal mounted on the pad portion can be reinforced. the bonding force between them.

Description of drawings

The above and other aspects, features and advantages of the present invention will be more apparent by further describing exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

1 is a plan view of a display substrate according to a first exemplary embodiment of the present invention;

2 is a partial cross-sectional view of the display substrate in FIG. 1 according to a first exemplary embodiment of the present invention;

3A, 3B and 3C are partial cross-sectional views illustrating a manufacturing method of the substrate shown in FIG. 2 according to a first exemplary embodiment of the present invention;

4 is a partial cross-sectional view of a display substrate according to a second exemplary embodiment of the present invention;

5A and 5B are partial cross-sectional views illustrating a method of manufacturing a display substrate in FIG. 4 according to a second exemplary embodiment of the present invention;

6 is a partial sectional view of a display according to a third exemplary embodiment of the present invention;

7 is a partial sectional view of a display according to a fourth exemplary embodiment of the present invention;

8 is a partial sectional view of a display according to a fifth exemplary embodiment of the present invention;

9 is a partial sectional view of a display according to a sixth exemplary embodiment of the present invention;

10 is a partial cross-sectional view of a display substrate according to a seventh exemplary embodiment of the present invention;

11 is a partial cross-sectional view of a display substrate according to an eighth exemplary embodiment of the present invention;

12 is a partial cross-sectional view of a display substrate according to a ninth exemplary embodiment of the present invention;

13 is a partial sectional view of a display substrate according to a tenth exemplary embodiment of the present invention; and

14 is a partial cross-sectional view of a display substrate according to an eleventh exemplary embodiment of the present invention.

Detailed ways

The present invention will now be described more fully with reference to the accompanying drawings showing exemplary embodiments of the invention. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals designate like elements throughout.

It will be understood that when an element is said to be on another element, it can be directly on the other element or intervening elements may be present therebetween. Accordingly, when one element is said to be directly on another element, there are no intervening elements present. As used herein, the term "and/or" includes any and all combinations of one or more of the listed items.

It will be understood that although the terms "first", "second", "third" etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

The terminology used herein is for describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms "a", "an" and "the" also include plural forms unless the context clearly dictates otherwise. It can be understood that when the terms "comprising" and/or "comprising" are used in the description, it indicates that there are specified features, regions, components, integers, steps, operations, elements and/or components, but does not exclude one or The presence or addition of multiple other features, regions, integers, steps, operations, elements, components and/or combinations thereof.

Also, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe an element's relationship to other elements as shown in the figures. It will be understood that other orientations of the device than those shown in the figures are encompassed by terms relative to the orientation. For example, if the device in one of the figures is turned over, elements described as "below" other elements would then be oriented "above" the elements. Therefore, the typical term "lower part" includes both "lower part" and "upper part" according to the particular orientation in the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "lower" can thus encompass both an orientation of above and below.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the meaning commonly understood by one of ordinary skill in the art to which this invention belongs. It can further be understood that these terms, such as those defined in general dictionaries, should be interpreted as meanings consistent with the relevant technologies and the context of the present disclosure, and should not be interpreted as idealized or overly formal meanings, unless explicitly stated herein so defined.

Exemplary embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. Likewise, various deviations from the shapes of the figures, eg, due to manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as planar, typically has rough and/or non-linear features. Furthermore, sharp angles described can be rounded. Thus, the regions depicted in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the invention.

Hereinafter, typical embodiments of the present invention will be described in further detail with reference to the corresponding drawings.

FIG. 1 is a plan view of a display substrate according to a first exemplary embodiment of the present invention.

According to FIG. 1 , the display substrate includes a display area DA and a peripheral area PA surrounding the display area DA. A plurality of gate lines GL and a plurality of data lines DL are formed in the display area DA. The gate lines GL cross the data lines DL to define a substantially rectangular pattern. In one exemplary embodiment, the gate lines GL and the data lines DL define a plurality of pixel portions P on the display substrate; however, the plurality of pixel portions P may be defined differently in alternative exemplary embodiments.

Each pixel P of the plurality of pixel portions P includes a switching element TFT electrically connected to each of the plurality of gate lines GL and each of the plurality of data lines DL, and a switching element TFT electrically connected to the plurality of data lines DL. The pixel electrode PE.

The peripheral area PA includes a first circuit area CA1 disposed at an end of the data line DL and a second circuit area CA2 disposed at an end of the gate line GL.

The pad part 210 and the bonding part 220 are disposed on the surface of the first circuit area CA1. The pad part 210 includes a plurality of pads 211 . Further, the pad portion 210 includes an input pad 210a electrically connected to an input terminal of a source integrated circuit (“IC”) (not shown), and an output pad 210b electrically connected to an output terminal (not shown). The output pad part 210b is electrically connected to the data line DL to apply a data signal to the data line DL.

The bonding portion 220 includes a plurality of holes formed adjacent to the pad portion 210 . The bonding part 220 strengthens the bonding force between the pad part 210 and the source IC (not shown) and strengthens the bonding force between the source IC and the display substrate.

The gate circuit part 230 may be directly formed on the display substrate in the second circuit area CA2. The gate circuit part 230 may include a shift register, have a plurality of switching elements electrically connected to each other, and apply a gate signal to the gate line GL.

FIG. 2 is a partial cross-sectional view of the substrate shown in FIG. 1 according to a first exemplary embodiment of the present invention.

According to FIGS. 1 and 2 , a display substrate 100 a according to a first exemplary embodiment of the present invention includes a base substrate 101 . The display substrate 100a further includes a display area DA and a peripheral area PA surrounding the display area DA, as described above. Likewise, the peripheral area PA includes a first circuit area CA1 and a second circuit area CA2.

A first metal pattern (not fully shown) is formed on the base substrate 100a. The first metal pattern includes a plurality of gate lines GL formed in the display area DA, a gate electrode GE of the switching element TFT, and a gate metal pattern 231 formed in the gate circuit part 230 of the second circuit area CA2.

A gate insulating layer 110 is formed on the base substrate 101 on which a first metal pattern is formed, and a channel portion CH is formed on the gate insulating layer 110 of the gate electrode GE. The channel portion CH includes an active layer having amorphous silicon ("a-Si"), and an ohmic contact layer having n+ amorphous silicon ("n+a-Si") obtained by implanting n+ impurities at a higher concentration a-Si formation. The first hole H1 is formed in the gate insulating layer 110 on the gate metal pattern 231 .

A second metal pattern (not fully shown) is formed on the base substrate 101 on which the channel portion CH is formed. The second metal pattern (not fully shown) includes a plurality of data lines DL formed in the display area DA, the source electrode SE of the switching element TFT, the drain electrode DE of the switching element TFT, and a liner formed in the first circuit area CA1. pad pattern 211a, and a source metal pattern 232 formed in the gate circuit part 230 in the second circuit area CA2. The source metal pattern 232 electrically contacts the gate metal pattern 231 through the first hole H1.

A protective insulating layer 120 and an organic layer 130 are formed on the base substrate 101 on which the second metal pattern is formed. The organic layer 130 is formed on the gate circuit part 230 to prevent corrosion of the gate circuit part 230 , thereby enhancing driving reliability of the gate circuit part 230 .

The second hole H2 exposing part of the drain electrode DE is formed on the protective insulating layer 120 and the organic layer 130, the third hole H3 forming the bonding portion 220 and the fourth hole H4 exposing the pad pattern 211a are formed on the first circuit area CA1 . The third hole H3 of the bonding part 220 may expose the gate insulating layer 110 through the patterning of the organic layer 130 and the protective insulating layer 120 . In an alternative embodiment, the third hole H3 may expose the protective insulating layer 120 by patterning only the organic layer 130 . Further, the first portion of the organic layer 130 corresponding to the first circuit area CA1 may have a first thickness, which is thinner than a second thickness of the second portion 130 of the organic layer corresponding to the display area DA, so as to minimize the third holes H3 and The stepped part of the fourth hole H4.

A pixel electrode PE electrically connected to the drain electrode DE through the second hole H2 is formed in the display area DA, and a pad electrode 211b electrically connected to the pad pattern 211a through the fourth hole H4 is formed in the first circuit area CA1. A pad 211 including a pad pattern 211a and a pad electrode 211b is formed in the first circuit area CA1.

The conductive adhesive 150 is formed in the first circuit area CA1 on which the source IC (not shown) is mounted and is electrically connected to the source IC and the pad part 210 . The conductive adhesive 150 may include, for example, an anisotropic conductive film ("ACF"), but is not limited thereto. The conductive adhesive 150 is inserted into the plurality of third holes H3 of the adhesive part 220 to directly contact the gate insulating layer 110 or the protective insulating layer 120 .

Accordingly, since the conductive adhesive 150 is in direct contact with the base substrate 101 through the plurality of third holes H3 of the bonding portion 220, the adhesive force between the conductive adhesive 150 and the base substrate 101 is strengthened. Thus, the conductive adhesive 150 is prevented from coming off from the base substrate 101 . As a result, the adhesive force between the source IC mounted on the first circuit area CA1 and the pad portion 210 is strengthened, thereby improving driving reliability.

3A, 3B and 3C are partial cross-sectional views illustrating a method of manufacturing the substrate shown in FIG. 2 according to a first exemplary embodiment of the present invention.

1, 2 and 3A, the first metal pattern (not fully shown) of the gate metal pattern 231 including the gate line GL, the gate electrode GE and the gate circuit part 230 adopts the first metal pattern formed on the base substrate 101. A metal layer is formed on the base substrate 101 . Then, a gate insulating layer 110 is formed on the base substrate 101 having the first metal pattern formed thereon.

A channel layer having an active layer and an ohmic contact layer is formed on the base substrate 101 having a gate insulating layer 110 formed thereon. The active layer may include a-Si. The ohmic contact layer may include n+a-Si formed by implanting n+ impurities into a-Si at a high concentration. Next, the channel layer is patterned to form a channel portion CH covering the gate electrode GE on the gate insulating layer 110, as shown in FIG. 3A.

The first hole H1 is formed in the gate metal pattern 231 by patterning the gate insulating layer 110 .

Now according to FIGS. 1, 2 and 3B, a second metal pattern comprising the data line DL, the source electrode SE, the drain electrode DE, the pad pattern 211a and the source metal pattern 232 of the gate circuit portion 230 is formed on the base substrate 101, It has a first hole H1 formed on the base substrate 101 using a second metal layer.

The source metal pattern 232 of the gate circuit part 230 is electrically connected to the gate metal pattern 231 through the first hole H1.

A protective insulating layer 120 and an organic layer 130 are sequentially formed on the base substrate 101 on which the second metal pattern is formed. Then, the protective layer 120 and the organic layer 130 are patterned using the mask 250 .

The mask 250 includes an exposed portion 251 , a half-exposed portion 252 and a light blocking portion 253 . The exposed portion 251 is disposed on the second hole H2 formed on the display area DA, and the third and fourth holes H3 and H4 are formed in the first circuit area CA1. The half-exposed portion 252 is disposed on the first circuit area CA1, and the light blocking portion 253 is disposed on the organic layer 130 area, as shown in FIG. 3B.

Accordingly, during the patterning process of the protective layer 120 and the organic layer 130 using the mask 250, the exposed portion 251 removes the organic layer 130 and the protective insulating layer 120 to form the second, third and fourth holes H2, H3 and H4, respectively. Subsequently, the half-exposed portion 252 forms the organic layer 130 on the first circuit area CA1, which is thicker than the organic layer 130 formed on the display area DA and the second circuit area CA2, as described above.

Still according to FIGS. 1 , 2 and 3B , the organic layer 130 and the protective insulating layer 120 are removed, and the gate insulating layer 110 is exposed to form holes for the bonding portion 220 . In an alternative embodiment of the present invention, the organic layer 130 , the insulating layer 120 and the gate insulating layer 110 may be removed simultaneously, and then the base substrate 101 is exposed to form the hole of the bonding portion 220 . Alternatively, the organic layer 130 may be removed and then the protective insulating layer 120 exposed to form the second, third and fourth holes H2, H3 and H4 of the bonding part 220, respectively.

According to FIGS. 1, 2 and 3C, a transparent conductive layer (not fully shown) is formed on the base substrate 101 on which the second to fourth holes H2, H3 to H4 are respectively formed. The transparent conductive layer is patterned to form a pixel electrode PE electrically connected to the drain electrode DE in the display area DA through the second hole H2, and to form a pad electrode electrically connected to the pad pattern 211a in the first circuit area CA1 through the fourth hole H4. 211b. Thus, a pad 211 including a pad pattern 211a and a pad electrode 211b is formed.

The conductive adhesive 150 is formed on the first circuit area CA1 on which the pad electrode 211b is formed. In an exemplary embodiment, the conductive adhesive 150 is electrically connected to the source IC and the pad electrode 211b mounted to the first circuit area CA1. Further, the conductive adhesive 150 is inserted into the third hole H3 of the adhesive part 220 to contact the gate insulating layer 110 .

Correspondingly, the adhesive force between the base substrate 101 and the conductive adhesive 150 , such as a coupling force, prevents, for example, the protective insulating layer 120 and the organic layer 130 from being separated by external effects, but is not limited thereto.

4 is a partial cross-sectional view of a display substrate according to a second exemplary embodiment of the present invention. Hereinafter, the same reference numerals are used to designate the same components as those described with reference to the display substrate 100a according to the first exemplary embodiment of the present invention, and repeated descriptions are omitted here.

According to FIGS. 1 and 4, the display substrate 100b according to the second exemplary embodiment has a reflective-transmissive structure. For example, the display area DA may include a transmissive area TA and a reflective area RA. The organic layer 130a is formed in the reflective area RA. The pixel electrode PE formed in the display area DA includes a transparent electrode TE formed in the transmissive area TA and a reflective electrode RE formed in the reflective area RA.

A bonding portion 220 including a plurality of holes and a pad portion 210 including a plurality of pads 211 are formed in the first circuit area CA1. The bonding part 220 and the pad part 210 are formed by patterning the organic layer 130a. The part of the organic layer 130a in the reflective area RA is thicker than the part of the organic layer 130a in the first circuit area CA1, as shown in FIG. 4 .

The bonding part 220 includes a plurality of third holes H3. A plurality of third holes H3 are formed by patterning the organic layer 130 a and the protective insulating layer 120 . In an alternative embodiment, the plurality of third holes H3 may be formed by patterning only the organic layer 130a.

The conductive adhesive layer 150 is formed in the first circuit area CA1, and is electrically connected to a source IC (not shown) terminal mounted to the pad 211 in the first circuit area CA1. The conductive adhesive 150 is inserted into the plurality of third holes H3 of the adhesive part 220 to contact the gate insulating layer 110 .

Accordingly, the adhesive force between the base substrate 101 and the conductive adhesive layer 150 through the adhesive portion 220 strengthens the adhesive force between the protective insulating layer 120 and the organic layer 130a.

The gate circuit part 230 is formed in the second circuit area CA2. The gate circuit part 230 includes a gate metal pattern 231 and a source metal pattern 232 formed on the gate metal pattern 231 . The gate metal pattern 231 and the source metal pattern 232 are electrically connected to each other through the first hole H1 formed on the gate insulating layer 110 . The organic layer 130 a is formed on the gate circuit part 230 to prevent corrosion of the gate circuit part 230 .

5A and 5B are partial cross-sectional views illustrating a method of manufacturing the display substrate in FIG. 4 according to a second exemplary embodiment of the present invention.

According to FIGS. 1 , 4 , 5A and 5B, a first metal pattern and a second metal pattern are formed on a base substrate 101 . The gate lines GL, data lines DL and switching elements TFT are formed in the display area DA, the pad pattern 211a is formed in the first circuit area CA1, and the gate circuit part 230 is formed in the second circuit area CA2.

The protective insulating layer 120 and the organic layer 130 a are sequentially formed on the base substrate 101 having the first and second metal patterns formed thereon, and then the protective insulating layer 120 and the organic layer 130 a are patterned using the mask 260 .

The mask 260 includes an exposed portion 261 , a half-exposed portion 262 and a light blocking portion 263 . The exposed portion 261 is disposed on the second hole H2 in the display area DA, the transmissive area TA of the display area DA, the third hole H3 and the fourth hole H4 in the first circuit area DA.

The half-exposed portion 262 is disposed on the organic layer 130a in the first circuit area CA1, as shown in FIG. 5A. The light blocking part 253 is disposed on the remaining area of the organic layer 130a, for example, the remaining area of the organic layer 130a is within the second circuit area CA2, but is not limited thereto.

Therefore, during the patterning process of the protective layer 120 and the organic layer 130a using the mask 260, the organic layer 130a and the protective insulating layer 120 are removed to form the second to fourth holes H2, H3 and H4, respectively, and the gate is exposed in the transmission area TA. Pole insulating layer 120.

Due to the half-exposed portion 252, the thickness of the organic layer 130a corresponding to the first circuit area CA1 is thinner than that of the organic layer 130a corresponding to the display area DA and the second circuit area CA2.

According to FIGS. 1, 4 and 5B, a reflective metal layer is formed on a base substrate 101 having second to fourth holes H2, H3 and H4 formed thereon, respectively. The reflective metal layer is patterned to form the reflective electrode RE of the pixel electrode PE on the organic layer 130a of the reflective area RA. The reflective electrode RE is electrically connected to the drain electrode DE through the second hole H2, as shown in FIG. 5B.

The transparent electrode layer is formed on the base substrate 101 having the reflective electrode RE formed thereon, and then the transparent electrode layer is patterned to form the transmissive electrode TE of the pixel electrode PE, and the pad electrically connected to the pad pattern 211a through the fourth hole H4. Electrode 211B. Accordingly, a pad 211 including a pad pattern 211a and a pad electrode 211b is formed.

The conductive adhesive 150 (FIG. 4) is formed on the first circuit area CA1 having the pad electrode 211b formed thereon. The conductive adhesive 150 is inserted into the third hole H3 of the adhesive part 220 to contact the gate insulating layer 110 . Accordingly, the bonding force between the base substrate 101 and the conductive bonding member 150 through the bonding portion 220 strengthens the bonding force between the protective insulating layer 120 and the organic layer 130a.

6 is a partial sectional view of a display according to a third exemplary embodiment of the present invention.

According to FIGS. 1 and 6 , the display according to the third exemplary embodiment includes a display panel and a source IC 600 .

The display panel includes a display substrate 100a, an opposite substrate 400a facing the display substrate 100a, and a liquid crystal layer 500a interposed between the display substrate 100a and the opposite substrate 400a. The display substrate 100a is basically the same as the display substrate in FIG. 2 . Therefore, the same reference numerals may be used to denote the same components as those described in FIG. 2 , and any repetitive explanation related to the same components will be omitted below.

The opposite substrate 400a faces the display substrate 100a. The opposite substrate 400a and the display substrate 100a are combined by the sealing member 330 to accommodate the liquid crystal layer 500a.

The opposite substrate 400 a includes a light blocking layer 410 , a color filter layer 420 and a common electrode layer 440 . The light blocking layer 410 may include a light blocking material. Further, the light blocking layer 410 may be formed in an area corresponding to the data line DL and the gate line GL of the display area DA to block light leakage, and may be formed in a peripheral area PA adjacent to the display area DA to enhance visibility of the display area DA.

The color filter layer 420 is formed in a pixel area of the display area DA defined by a portion of the display area DA and not covered by the light blocking layer 410 to filter transmitted light into light having a color determined by the color filter.

The common electrode layer 440 is an electrode facing the pixel electrode PE of the display substrate 100a to form an electric field in the liquid crystal layer 500a.

The source IC 600 includes a driving chip (not shown) and a flexible printed circuit board (“FPCB”) (not shown) for mounting the driving chip. Source IC 600 includes a plurality of terminals 610 .

The source IC 600 is mounted on the first circuit area CA1 of the display substrate 100a. The conductive adhesive 150 formed in the first circuit area CA1 is electrically connected to the terminal 610 and the pad 211 . The conductive adhesive 150 may be bonded to the third hole H3 of the bonding part 220 to strengthen the bonding force between the source IC 600 and the pad 211 .

The adhesive force between the adhesive part 220 and the conductive adhesive 150 prevents, for example, the protective insulating layer 120 and the organic layer 130 from being separated by external effects. Therefore, electrical contact defects between the source IC 600 and the pad 211 can be effectively prevented or reduced.

7 is a partial sectional view of a display according to a fourth exemplary embodiment of the present invention. Hereinafter, the same components according to the third exemplary embodiment described in FIG. 6 are denoted by the same reference numerals, and any repeated description will be omitted.

According to FIGS. 1 and 7 , the display according to the fourth exemplary embodiment includes a display panel and a source IC 600 .

The display panel includes a display substrate 100b, an opposite substrate 400b facing the display substrate 100b, and a liquid crystal layer 500b interposed between the display substrate 100b and the opposite substrate 400b. The display substrate 100b is substantially the same as that in FIG. 4 according to the second exemplary embodiment, and thus any repeated explanation will be omitted. The opposite substrate 400b is disposed to face the display substrate 100b, and is combined with the display substrate 100b through the sealing member 330 to accommodate the liquid crystal layer 500b.

The opposite substrate 400b includes a color filter layer 420a on which a light-transmitting hole 421 is formed to enhance the color reproducibility of the reflective area PA.

The liquid crystal layer 500b has a first cell gap d1 corresponding to the reflective area RA of the display substrate 100b, and a second cell gap d2 corresponding to the transmissive area TA of the display substrate 100b.

In the reflective area RA, when the first light is incident to the liquid crystal layer 500b of the first cell gap d1 through the opposite substrate 400b, the first light has a double transmission path. More specifically, the first light transmitted through the liquid crystal layer 500b of the first cell gap d1 is reflected by the reflective electrode RE, and then the first light is transmitted again through the liquid crystal layer 500b of the first cell gap d1.

Alternatively, in the transmission area TA, when the second light passes through the display substrate 100b and is transmitted into the liquid crystal layer 500b of the second cell gap d2, the second light has a single transmission path.

The length of the second cell gap d2 is approximately twice the length of the first cell gap d1.

The source IC 600 is disposed on the first circuit area CA1 of the display substrate 100b. The conductive adhesive 150 is electrically connected to the terminal 610 of the source IC 600 and the pad 211 , and may be bonded to the third hole H3 of the bonding part 220 to strengthen the adhesive force between the source IC 600 and the pad 211 .

8 is a partial sectional view of a display according to a fifth exemplary embodiment of the present invention.

According to FIGS. 1 and 8 , the display according to the fifth exemplary embodiment includes a display panel and a source IC 600 .

The display panel includes a display substrate 100c, an opposite substrate 400c, and a liquid crystal layer 500b interposed between the display substrate 100c and the opposite substrate 400c.

The display substrate 100c includes a first portion 130a of organic layers and a second organic layer 130b. The second organic layer 130b has an alternating meniscus pattern (hereinafter collectively referred to as a relief pattern) formed in the reflective area RA and a planar pattern formed in the transmissive area TA, as shown in FIG. 8 . In alternative exemplary embodiments, the second organic layer 130 b may be omitted from the transmission area TA to expose the protective insulating layer 120 or the gate insulating layer 110 .

The reflective electrode RE is formed of a reflective metal layer in the reflective area RA. The transmissive electrode TE is formed of a transparent electrode layer within the transmissive area TA. For example, the transparent electrode layer may be electrically connected to the switching element TFT, and then the reflective electrode RE is formed on the transparent electrode layer corresponding to the reflective area RA, but is not limited thereto.

A relief pattern is formed in the second organic layer 130b under the reflective electrode RE. Further, a relief pattern is formed on the reflective electrode RE to enhance the reflectivity of the reflective electrode RE.

The opposite substrate 400c includes a color filter layer 420a having a plurality of light transmission holes 421 formed therein and a third organic layer 430 . The third organic layer 430 is formed on the reflective area RA such that the liquid crystal layer 500b has a first cell gap d1 corresponding to the reflective area RA and a second cell gap d2 corresponding to the transmissive area TA.

The source IC 600 is installed in the first circuit area CA1 of the display substrate 100c. The conductive adhesive layer 150 electrically connects the terminal 610 of the source IC 600 to the pad 211 , and may be bonded to the third hole H3 of the adhesive part 220 to strengthen the adhesive force between the source IC 600 and the pad 211 .

9 is a partial sectional view of a display according to a sixth exemplary embodiment of the present invention.

According to FIGS. 1 and 9 , the display includes a display panel and a source IC 600 . The display panel includes a display substrate 100 d , an opposite substrate 400 and a liquid crystal layer 500 .

The display substrate 100d includes a base substrate 101 . The first metal pattern is formed by a first metal layer on the base substrate 101 . The first metal pattern includes a plurality of gate lines GL formed in the display area DA and gate electrodes GE of the switching elements TFT.

A gate insulating layer 110 is formed on the base substrate 101 having the first metal pattern formed thereon, and a channel layer is formed on the gate insulating layer 110, on the gate electrode GE. The channel layer includes an active layer and an ohmic contact layer. The active layer includes a-Si. The ohmic contact layer includes n+a-Si, for example, a-Si doped with a high concentration of n-type dopants. The channel layer is patterned to form a channel portion CH of the switching element TFT on the gate electrode GE and a dummy pattern DP on the first channel area CA1.

A second metal pattern formed of a second metal layer is formed on the base substrate 101 on which the channel part CH and the dummy pattern DP are formed. The second metal pattern includes a plurality of data lines DL, the source electrode SE and the drain electrode DE of the switching element TFT formed on the display area DA, and includes a pad pattern 211a formed on the first circuit area CA1 and a pad pattern formed on the second circuit area CA1. The source metal pattern 232 of the gate circuit portion 230 on the area CA2. The source metal pattern 232 is electrically connected to the gate metal pattern 231 through the first hole H1.

A protective insulating layer 120 and an organic layer 130 are formed on the base substrate 101 having the second metal pattern formed thereon. The organic layer 130 covers the gate circuit part 230 to prevent corrosion of the gate circuit part 230, thereby enhancing driving reliability.

The second hole H2 is formed in the protective insulating layer 120 and the organic layer 130 to expose a portion of the drain electrode DE. The pixel electrode PE is formed in the display area DA through the second hole H2, which is electrically connected to the drain electrode DE.

The third hole H3 of the bonding part 220 and the fourth hole H4 exposing the pad pattern 211a are formed in the first circuit area CA1. The third hole H3 of the bonding part 220 is patterned through the organic layer 130 and the protective insulating layer 120 to expose the dummy pattern DP.

栅极绝缘层110通过蚀刻处理清除。因此，虚拟构图DP相应于其上形成有第三孔H3的区域形成，以防止在保护绝缘层120蚀刻期间栅极绝缘层的过蚀刻。虚拟构图DP的厚度厚于过蚀刻的厚度。例如，虚拟构图DP1的厚度可大约为700

到15,000

，但并不限制于此。During the etching process of the protective insulating layer 120 before the formation of the dummy pattern DP, the gate insulating layer 110 is over-etched to form the third hole H3 of the bonding part 220 . More specifically, about 700

The gate insulating layer 110 is removed by an etching process. Accordingly, the dummy pattern DP is formed corresponding to the region on which the third hole H3 is formed to prevent over-etching of the gate insulating layer during etching of the protective insulating layer 120 . The thickness of the virtual patterning DP is thicker than that of the overetching. For example, the thickness of the virtual composition DP1 may be about 700

to 15,000

, but not limited to this.

The dummy patterning DP prevents etching of the gate insulating layer 110 and etching of the protective insulating layer 120 such that the conductive adhesive 150 contacts the dummy patterning DP1 at the third hole H3 to be bonded to the protective insulating layer 120 and the organic layer 130 . Therefore, the adhesive force between the display substrate 100d and the conductive adhesive member 150 is strengthened. As a result, the adhesive force between the source IC 600 mounted in the first circuit area CA1 and the pad 211 is strengthened, thereby improving driving reliability.

The pad electrode 211b is formed through the fourth hole H4, and is electrically connected to the pad pattern 211a. Accordingly, the pad 211 including the pad pattern 211a and the pad electrode 211b is formed on the first circuit area CA1.

The thickness of the organic layer 130 corresponding to the first circuit area CA1 may be thinner than that of the organic layer 130 formed in the display area DA, as shown in FIG. 9, so that the height steps between the third and fourth holes H3 and H4 may be minimize.

The opposite substrate 400 includes a light blocking layer 410 , a color filter layer 420 and a common electrode layer 440 .

The light blocking layer 410 may include a light blocking material. Also, the light blocking layer 410 may be formed in an area corresponding to the data line DL and the gate line GL of the display area DA to block light leakage, and at the same time be formed in the peripheral area PA adjacent to the display area DA to enhance the reliability of the display area DA. visibility.

The color filter layer 420 is formed in a pixel area of the display area DA defined by a portion of the display area DA and not covered by the light blocking layer 410 to filter transmitted light into light having a color determined by the color filter. The common electrode layer 440 is an electrode facing the pixel electrode PE of the display substrate 100 d to form an electric field in the liquid crystal layer 500 .

The source IC 600 includes a driver chip (not shown) and an FPCB (not shown) for mounting the driver chip. Source IC 600 includes a plurality of terminals 610 .

The source IC 600 is mounted on the first circuit area CA1 of the display substrate 100d. The conductive adhesive layer 150 formed at the first circuit area CA1 is electrically connected to the terminal 610 and the pad 211 . The conductive adhesive 150 is bonded to the third hole H3 of the bonding part 220 to strengthen the bonding force between the source IC 600 and the pad 211 as described above.

Therefore, the adhesive force between the bonding part 220 and the conductive bonding member 150 prevents, for example, the protective insulating layer 120 and the organic layer 130 from being separated by external effects. Therefore, electrical contact defects between the source IC 600 and the pad 211 can be effectively prevented or reduced.

10 is a partial sectional view of a display according to a seventh exemplary embodiment of the present invention.

According to FIGS. 9 and 10, the display substrate 100e may further include a step compensation pattern SP formed under the dummy pattern DP1. The step compensation pattern SP is formed of the first metal layer and the step compensation pattern SP is included in the first metal pattern. The step compensation patterning SP reduces the step height of the organic layer 130 formed on the third hole H3.

The step height of the organic layer 130 is compensated by the step compensation pattern SP, so that the adhesive force between the dummy pattern DP1 and the conductive adhesive member 150 through the third hole H3 may be strengthened.

11 is a partial sectional view of a display according to an eighth exemplary embodiment of the present invention.

According to FIGS. 1 and 11, the bonding part 220 including the third hole H3 is formed at the first circuit area CA1 of the display substrate 100f. The third hole H3 of the bonding part 220 is formed by patterning the protective insulating layer 120 and the organic layer 130 to expose the dummy pattern DP2. The dummy pattern DP2 is formed through the second metal layer, so that the second metal pattern includes the dummy pattern DP2.

The conductive adhesive layer 150 is bonded to the dummy pattern DP2 through the third hole H3 of the bonding part 220 , protecting the insulating layer 120 and the organic layer 130 to strengthen the adhesive force between the conductive adhesive layer 150 and the base substrate 101 . Further, the adhesive force between the dummy pattern DP2 formed by the second metal layer and the conductive adhesive member 150 can be very large, because the adhesive force characteristic between the metal material and the organic material is very good. Correspondingly, the adhesion between the organic layer 130 and the protective insulating layer 120 is strengthened.

As a result, an adhesive force between a source IC (not shown) mounted on the first circuit area CA1 and the pad 211 is strengthened, thereby improving driving reliability.

12 is a partial sectional view of a display according to a ninth exemplary embodiment of the present invention.

According to FIGS. 11 and 12, the display substrate 100g further includes a step compensation pattern SP formed under the dummy pattern DP2.

The step compensation pattern SP is included in the first metal pattern formed by the first metal layer. The step compensation patterning SP reduces the step height of the organic layer 130 formed in the third hole H3. The step height of the organic layer 130 is compensated by the step compensation pattern SP, so that the adhesive force between the dummy pattern DP2 and the conductive adhesive layer 150 through the third hole H3 is further strengthened.

13 is a partial sectional view of a display according to a tenth exemplary embodiment of the present invention.

According to FIGS. 1 and 13, the bonding part 220 including the third hole H3 is formed in the first circuit area CA1 of the display substrate 100h. The third hole H3 of the bonding part 220 is formed by patterning the protective insulating layer 120 and the organic layer 130 to expose the dummy pattern DP3. The virtual composition DP3 has a multi-layer structure including a first virtual composition DP1 and a second virtual composition DP2 formed on the first virtual composition DP1. The first dummy pattern DP1 is formed of a channel layer. The second dummy pattern DP2 is formed of the second metal layer. The dummy pattern DP3 is formed by simultaneous patterning using masks of the channel layer and the second metal layer.

Accordingly, the conductive adhesive layer 150 is bonded to the second dummy pattern DP2 of the dummy pattern DP3 , and then bonded to the protective insulating layer 120 and the organic layer 130 . Further, as mentioned above, due to the better characteristics of the bonding force between the metal material and the organic material, the bonding force between the second virtual pattern DP2 formed by the second metal layer and the conductive bonding member 150 is relatively large. . Correspondingly, the adhesion between the organic layer 130 and the protective insulating layer 120 is strengthened.

As a result, an adhesive force between a source IC (not shown) mounted on the first circuit area CA1 and the pad 211 is strengthened, thereby improving driving reliability.

The data line DL, the source electrode DI and the drain electrode DE of the switching element TFT formed in the display area DA of the display substrate 100h are formed by patterning the channel layer and the second metal layer using a mask. Therefore, the data line DL, the source electrode SE, and the drain electrode DE have a multilayer structure including a channel layer and a second metal layer formed on the channel layer.

14 is a partial sectional view of a display according to an eleventh exemplary embodiment of the present invention.

According to FIGS. 13 and 14, the display substrate 100i may further include a step compensation pattern SP formed under the dummy pattern DP3. The step compensation pattern SP is included in the first metal pattern formed of the first metal layer. The step compensation patterning SP reduces the step height of the organic layer 130 formed in the third hole H3. The step height of the organic layer 130 is compensated by the step compensation pattern SP, so that the adhesive force between the dummy pattern DP3 and the conductive adhesive layer 150 through the third hole H3 is further strengthened.

Finally, as shown in FIGS. 9 to 14 , virtual composition and step compensation composition can be used in displays according to second to fifth exemplary embodiments of the present invention, as described above with reference to FIGS. 4 to 8 .

According to the exemplary embodiments of the present invention described herein, the bonding portion including the plurality of holes is formed adjacent to the pad portion, so that the adhesive force of the ICs electrically connected by the pad portion and the bonding member is enhanced.

The invention should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that these disclosures will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

For example, a lower insulating layer of the display substrate, such as a gate insulating layer or a protective insulating layer, may contact the conductive adhesive layer through the bonding portion, thereby strengthening the adhesive force between the organic layer and the protective insulating layer. Therefore, electrical contact defects between the IC and the pad portion caused by separation of the organic layer from the protective insulating layer can be effectively reduced or prevented.

While the invention has been particularly shown and described in terms of exemplary embodiments, it will be understood by those skilled in the art that changes may be made in form and detail without departing from the spirit and scope of the invention as defined in the following claims. Various changes and modifications.

Claims (65)

1, a kind of display base plate comprises:

Base substrate has the viewing area and around the outer peripheral areas of viewing area;

Be formed on the pixel electrode of viewing area;

Be formed on the liner part of outer peripheral areas;

Adhesive segment is formed on outer peripheral areas and has the formation of a plurality of holes and is close in the zone of liner part on outer peripheral areas; With

The conduction bonding piece is formed on liner part and the adhesive segment, to electrically contact liner part and ic terminal.

2,, wherein, further comprise as the display base plate in the claim 1:

Be formed on first insulation course on the base substrate; With

Be formed on the organic layer on first insulation course.

3, as the display base plate in the claim 2, each hole in wherein said a plurality of holes by the part organic layer outer peripheral areas form and

The conduction bonding piece is bonded to first insulation course that exposes to the open air by each hole.

4,, wherein, further comprise second insulation course that is formed on the base substrate as the display base plate in the claim 2.

5, as the display base plate in the claim 4, each hole in wherein said a plurality of holes by being formed on outer peripheral areas first insulation course and the part of organic layer forms and

The conduction bonding piece is bonded to second insulation course that exposes to the open air by each hole.

6, as the display base plate in the claim 4, each hole in wherein said a plurality of holes by being formed on outer peripheral areas first insulation course and the synchronous composition of organic layer forms and

Display base plate further comprises the virtual composition that is exposed to the open air by each hole.

7, as the display base plate in the claim 6, wherein, further comprise on-off element, it comprises the channel layer of the pixel electrode that is electrically connected to the first metal layer formation and source electrode and the drain electrode that second metal level forms.

8, as the display base plate in the claim 7, wherein virtual composition forms by the channel layer composition.

9, as the display base plate in the claim 7, wherein virtual composition forms by the second metal level composition.

10, as the display base plate in the claim 7, wherein virtual composition is a sandwich construction, forms by the channel layer composition and the second metal level composition.

11,, wherein, further comprise the ladder compensation composition that is formed on the base substrate as the display base plate in the claim 7.

12, as the display base plate in the claim 11, wherein ladder compensation composition forms by the first metal layer composition.

13, as the display base plate in the claim 4, each hole in wherein said a plurality of holes form by the synchronous composition of the part organic layer, first insulation course and second insulation course that are formed on outer peripheral areas and

The conduction bonding piece is bonded to second insulation course that exposes to the open air by each hole.

14, as the display base plate in the claim 2, wherein pixel electrode comprises transparency electrode and reflecting electrode.

15, as the display base plate in the claim 14, wherein organic layer is formed on the reflecting electrode.

16, as the display base plate in the claim 15, wherein organic layer has formation recessed composition and protruding composition thereon.

17, as the display base plate in the claim 2, wherein:

First's organic layer with first thickness is formed on the outer peripheral areas with liner part,

Second portion with organic layer of second thickness be formed on have pixel electrode form thereon the viewing area and

Second thickness of the second portion of organic layer is greater than first thickness of first's organic layer.

18,, wherein, further comprise the grid circuit part that is formed on outer peripheral areas as the display base plate in the claim 2.

19,, wherein be formed on the part organic layer cover gate circuit part of outer peripheral areas as the display base plate in the claim 18.

20, a kind of display base plate comprises:

Base substrate has the viewing area and around the outer peripheral areas of viewing area;

Be formed on the pixel electrode on the viewing area;

Be formed on the liner part on the outer peripheral areas;

Circuit part is formed on outer peripheral areas and has the formation of a plurality of holes in the zone of the contiguous liner part of outer peripheral areas; With

Be installed in the integrated circuit on the circuit part.

21,, wherein, further comprise as the display base plate in the claim 20:

Be formed on first insulation course on the base substrate; With

Be formed on the organic layer on first insulation course.

22, as the display base plate in the claim 21, each hole in wherein said a plurality of holes forms in outer peripheral areas by the part organic layer.

23,, wherein, further comprise second insulation course that is formed on the base substrate as the display base plate in the claim 21.

24, as the display base plate in the claim 23, each hole in wherein said a plurality of holes by being formed on outer peripheral areas first insulation course and the part of organic layer form.

25,, wherein, further comprise the virtual composition that exposes to the open air by each hole as the display base plate in the claim 24.

26, as the display base plate in the claim 25, wherein, further comprise on-off element, this on-off element comprises the channel layer of the pixel electrode that is electrically connected to the first metal layer formation and source electrode and the drain electrode that second metal level forms.

27, as the display base plate in the claim 26, wherein virtual composition is formed by the channel layer composition.

28, as the display base plate in the claim 26, wherein virtual composition is formed by the second metal level composition.

29, as the display base plate in the claim 26, wherein virtual composition has sandwich construction, and is formed by the channel layer composition and the second metal level composition.

30,, wherein, further comprise the ladder compensation composition that is formed on the base substrate as the display base plate in the claim 26.

31, as the display base plate in the claim 30, wherein ladder compensation composition is formed by the first metal layer composition.

32, as the display base plate in the claim 23, each hole in wherein said a plurality of holes forms by the synchronous composition of the organic layer, first insulation course and second insulation course that are formed on outer peripheral areas.

33, as the display base plate in the claim 21, wherein pixel electrode comprises transparency electrode and reflecting electrode.

34, as the display base plate in the claim 33, wherein organic layer is formed on the reflecting electrode.

35, as the display base plate in the claim 34, wherein organic layer has formation recessed composition and protruding composition thereon.

36, as the display base plate in the claim 21, wherein:

First's organic layer with first thickness is formed on the outer peripheral areas with liner part,

Second portion with organic layer of second thickness form the viewing area be formed with pixel electrode thereon and

Second thickness of the second portion of organic layer is greater than first thickness of first's organic layer.

37,, wherein, further comprise the grid circuit part that is formed on the outer peripheral areas as the display base plate in the claim 21.

38,, wherein be formed on the part organic layer cover gate circuit part of outer peripheral areas as the display base plate in the claim 37.

39, the manufacture method of display base plate, this method comprises:

Form base substrate;

In the viewing area of base substrate, form on-off element;

In the outer peripheral areas of the viewing area that centers on base substrate, form the liner composition;

On base substrate, form organic layer;

The composition organic layer is to form adhesive segment on the part outer peripheral areas of contiguous liner composition, this adhesive segment has a plurality of holes and forms within it;

On base substrate, form pixel electrode;

Pixel electrode is electrically connected to on-off element and the pad electrode that is electrically connected to the liner composition; With

Form the conduction bonding piece on pad electrode and adhesive segment, this conduction bonding piece is electrically connected to pad electrode and ic terminal.

40,, wherein, further be included in and form first insulation course on the base substrate as the method in the claim 39.

41, as the method in the claim 40, the bonding piece of wherein conducting electricity is bonded to first insulation course that exposes to the open air by each hole in described a plurality of holes.

42,, wherein, further be included in and form second insulation course on the base substrate as the method in the claim 40.

43, as the method in the claim 42, wherein the formation of adhesive segment comprises synchronous composition first insulation course and organic layer.

44, as the method in the claim 43, the bonding piece of wherein conducting electricity is bonded to second insulation course that exposes to the open air by the hole.

45,, wherein, further be included in outer peripheral areas and form the grid circuit part as the method in the claim 40.

46, as the method in the claim 45, wherein the formation of organic layer has formed the organic layer of part cover gate circuit part.

47, a kind of display comprises:

Display panel comprises:

Base substrate;

Be formed on the base substrate and have the viewing area and the display base plate of outer peripheral areas;

Relative substrate towards display base plate;

Be formed on the pixel electrode on the viewing area;

Be formed on the liner part of outer peripheral areas; With

Adhesive segment is formed on the outer peripheral areas and has a plurality of holes in the zone of the contiguous liner part of the outer peripheral areas of being formed on;

Be formed on the conducting element of liner part and adhesive segment; With

Be electrically connected to the integrated circuit of liner part by conducting element.

48, as the display in the claim 47, wherein display base plate further comprises:

Be formed on first insulation course on the base substrate; With

Be formed on the first of the organic layer on first insulation course.

49, as the display in the claim 48, each hole in wherein said a plurality of holes forms by the first of the part organic layer of outer peripheral areas, and the conduction bonding piece is bonded to first insulation course that exposes to the open air by each hole.

50,, wherein, further comprise second insulation course that is formed on the base substrate as the display in the claim 48.

51, as the display in the claim 50, each hole in wherein said a plurality of holes forms by the first and part first insulation course of the part organic layer of outer peripheral areas, and

The conduction bonding piece is bonded to second insulation course that exposes to the open air by each hole.

52, as the display in the claim 50, its mesopore constitutes by first insulation course and the synchronous composition of organic layer that is formed on outer peripheral areas, and

Display base plate further comprises the virtual composition that exposes to the open air by each hole.

53, as the display in the claim 52, wherein, further comprise on-off element, it comprises the channel layer of the pixel electrode that is electrically connected to the first metal layer formation and source electrode and the drain electrode that second metal level forms.

54, as the display in the claim 53, wherein virtual composition forms by the channel layer composition.

55, as the display in the claim 53, wherein virtual composition forms by the second metal level composition.

56, as the display in the claim 53, wherein virtual composition is a sandwich construction, and forms by the channel layer and the second metal level composition.

57,, wherein, further comprise the ladder compensation composition that is formed on the base substrate as the display in the claim 53.

58, as the display in the claim 57, wherein ladder compensation composition forms by the first metal layer composition.

59, as the display in the claim 50, each hole in wherein said a plurality of holes by be formed on the synchronous composition of organic layer, first insulation course and second insulation course in the outer peripheral areas and form and

The conduction bonding piece is bonded to second insulation course that exposes to the open air by each hole.

60, as the display in the claim 48, wherein pixel electrode comprises transparency electrode and reflecting electrode.

61, as the display in the claim 60, wherein the first of organic layer is formed on the reflecting electrode.

62,, wherein be formed with recessed composition and protruding composition in the first of organic layer as the display in the claim 61.

63, as the display in the claim 60, wherein be formed with light hole in the colour filter, wherein light hole is formed on the reflecting electrode.

64, as the display in the claim 63, wherein, relatively substrate further comprises second organic layer, is formed on the reflecting electrode of the pixel electrode on the viewing area of display base plate.

65, as the display in the claim 48, wherein:

First with first's organic layer of first thickness is formed on the outer peripheral areas with liner part,

Second portion with organic layer of second thickness be formed on have that pixel electrode forms in thereon the viewing area and

Second thickness of the first of the second portion of organic layer is greater than first thickness of the first of first's organic layer.

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