CN101840240A - Adjustable multi-value output reference voltage source - Google Patents

Abstract

The invention discloses an adjustable multi-valued output reference voltage source, which comprises a reference generation circuit and a reference voltage output circuit, and a starting circuit and a mirror current source negative feedback loop are connected between the reference generation circuit and the reference voltage output circuit. One end of the start-up circuit is connected to the reference generating circuit, the other end is connected to the mirror current source negative feedback loop, and the other end of the mirror current source negative feedback loop is connected to the reference voltage output circuit. The adjustable multi-valued output reference voltage source of the invention has the advantages of low circuit power consumption, small temperature drift and strong power supply suppression capability. The reference voltage source of the adjustable multi-valued output of the present invention uses a mirror current source negative feedback loop instead of a high voltage gain operational amplifier to make the circuit structure simpler, and the source follower connected to the output terminal of the mirror current source negative feedback loop provides dual A bandgap reference voltage is generated simultaneously with the polar transistor bias voltage, and an output voltage value with a small temperature coefficient can be obtained at the same time.

Description

A Reference Voltage Source with Adjustable Multi-valued Output

technical field

The invention relates to a reference voltage source used in an integrated circuit, in particular to a bandgap reference voltage source.

Background technique

A reference voltage source usually refers to a highly stable voltage source used as a reference in a circuit. With the rapid development of integrated circuits, the system structure is further complicated, and higher requirements are put forward for the basic modules of analog circuits, such as A/D, D/A converters, voltage detection and comparison circuits, etc., high precision, high stability, Low power consumption is the mainstream of the design. For these modules, the voltage reference is a very important module, and the stability of the reference voltage source is directly related to the working state and performance of the circuit. A good voltage reference requires a small temperature coefficient and strong power supply rejection.

选择适当的倍数，使得两个电压的温漂系数相互抵消，从而得到在某一温度下的零温度系数的电压基准，典型值为1.25V。The working principle of the bandgap reference is based on the fact that the bandgap voltage of the silicon material is independent of the power supply voltage and temperature, and uses the positive temperature coefficient of V _BE to offset the negative temperature coefficient of V _BE of the bipolar transistor to achieve low temperature drift and high precision. the reference voltage. Bipolar transistors provide emitter bias voltage V _BE , V _T is generated by V _BE between the two transistors, V _T is amplified several times through a resistor network, and the two voltages are summed as

Select an appropriate multiple so that the temperature drift coefficients of the two voltages cancel each other out, thereby obtaining a voltage reference with zero temperature coefficient at a certain temperature, with a typical value of 1.25V.

In the BUCK type LED drive circuit, the voltage fed back by the current detection resistor is an extremely low voltage value, and we determine the switching state of the POWERMOS of the drive circuit by comparing the voltage value fed back by the current detection resistor. The stability of the reference voltage used for comparison is important. The general bandgap reference voltage source cannot directly meet this requirement, and other voltage conversion circuits need to be designed to reduce the output reference voltage value, which also greatly increases the difficulty of design.

The Chinese invention patent with publication number CN101470458A and application number 200710303891.8 discloses a bandgap reference voltage reference circuit, which includes: a VBE voltage generator, which includes a self-bias for generating two-branch reference circuits A current source, and a bias generator coupled to the self-bias current source for generating two VBE voltages; a reference voltage regulator, the reference voltage regulator includes an operational transconductance amplifier and a reference voltage adjustment unit for generate a constant reference voltage. The above solution needs to use an operational transconductance amplifier, which makes the circuit more complicated and the cost is higher.

这个正温度系数的电压，从而得到流过R1的PTAT电流，经电路镜像在电阻R2上得到正温度系数的电压V_R2，而负温度系数电压是双极性晶体管P3、P4的V_be相加构成，从附图可以看出，其带隙基准电压为

其中，

M为双极性晶体管P2、P1的基区面积比。Authorized announcement number is CN100459197C, patent number is ZL200510120849.3 Chinese invention patent discloses a low temperature coefficient bandgap reference voltage source, which includes the following circuit: PTAT current generation circuit, used to generate PTAT current IPTAT; reference voltage start The circuit is connected with the PTAT current generating circuit, and is used to overcome the zero current operating point of the PTAT current generating circuit, so as to ensure that the PTAT current IPTAT can be generated; the reference voltage synthesis circuit is connected with the output terminal of the PTAT current generating circuit, and is used to generate A reference voltage; a base current offset circuit, connected to the reference voltage synthesis circuit, used to offset the extra base current generated by the transistor in the reference voltage synthesis circuit, to ensure the correct generation of the reference voltage; a first current mirror circuit, used to The PTAT current mirror copy generated by the PTAT current generation circuit is output to the PTAT current generation circuit, the reference voltage starting circuit, the reference voltage synthesis circuit and the base current offset circuit respectively. The low temperature coefficient bandgap reference voltage source It also includes a second-order temperature compensation current generation circuit, connected to the first current mirror circuit and the reference voltage synthesis circuit, inputting the IPTAT current and the bandgap reference voltage, and utilizing the square relationship between the drain-source current of the MOS tube and the gate-source voltage difference, The second-order compensation current is generated and output to the reference voltage synthesis circuit to generate the second-order compensation voltage, and the second-order temperature coefficient of the reference voltage is compensated to generate a reference voltage with an extremely low temperature coefficient. On the one hand, the above scheme cannot realize the multi-value output mode; on the other hand, the way to generate the bandgap reference voltage is relatively complicated, and the power consumption, temperature drift and power supply suppression ability are not ideal. It is composed of MN1, MN2, MP1, and MP2. The current mirror makes the current flowing through MN1 and MN2 the same so that the source voltages of MN1 and MN2 are the same, and then the two ends of R1 are obtained

This positive temperature coefficient voltage, thus obtaining the PTAT current flowing through R1, is mirrored in the circuit to obtain the positive temperature coefficient voltage V _R2 on the resistor R2, and the negative temperature coefficient voltage is the sum of the V _be of the bipolar transistors P3 and P4 Composition, as can be seen from the attached figure, its bandgap reference voltage is

in,

M is the base area ratio of the bipolar transistors P2 and P1.

Contents of the invention

The problem to be solved by the present invention is to provide an adjustable multi-value output reference voltage source with low circuit power consumption, small temperature drift and strong power supply suppression capability.

In order to achieve the above object, the present invention designs a reference voltage source of adjustable multi-valued output. The reference voltage source of adjustable multi-valued output includes a reference generating circuit and a reference voltage output circuit. In the reference generating circuit and the reference voltage output circuit A start-up circuit and a mirror current source negative feedback loop are connected between them, one end of the start-up circuit is connected to the reference generating circuit, the other end is connected to the mirror current source negative feedback loop, and the other end of the mirror current source negative feedback loop is connected to the Reference voltage output circuit connection.

The mirror image current source negative feedback loop includes PMOS transistors MP5, MP6, NMOS transistors MN1, MN2, the gate of PMOS transistor MP5 is connected to the reference generation circuit, the source of MP5 is connected to VDD, and the drain of MP5 is connected to NMOS transistor The drain of MN2, the source of NMOS transistor MN2 are grounded, the gate of NMOS transistor MN2 is connected to the gate of NMOS transistor MN1, the drain of NMOS transistor MN1 is connected to the drain of PMOS transistor MP6, and the gate of PMOS transistor MP6 is connected to the reference. Circuit connection, the source of the PMOS transistor MP6 is connected to VDD, and the drain of the PMOS transistor MP6 is connected to the reference voltage output circuit.

The start-up circuit includes PMOS transistors MP3, MP4 and bipolar transistors Q3, Q4, the source terminal of the PMOS transistor MP3 is connected to VDD, the drain terminal is connected to the source terminal of the PMOS transistor MP4, and the gates of the PMOS transistors MP3 and MP4 are connected to each other. After being connected to ground, the drain of PMOS transistor MP4 is connected to the collector of bipolar transistor Q4, the emitter of bipolar transistor Q4 is grounded, its collector and base are short-circuited and simultaneously connected to the base of bipolar transistor Q3, The emitter and collector of the bipolar transistor Q3 are respectively connected to the reference generating circuit.

The reference voltage output circuit is a multi-valued reference voltage output circuit, which includes a source follower Q5, voltage dividing resistors R4, R5, R6, the base of the source follower Q5 and the mirror current source negative feedback loop The drain of the PMOS transistor MP6 is connected, the collector of Q5 is connected to VDD, the emitter is connected to the resistor R6 and leads to the output terminal of the reference voltage V2, the other end of the resistor R6 is connected to the resistor R5 and the reference generating circuit, and is between the resistors R6 and R5 The output end of the bandgap reference voltage VREF is drawn out, the other end of the resistor R5 is connected to the resistor R4, and the output end of the reference voltage V1 is drawn between the resistors R5 and R4, and the other end of the resistor R4 is grounded.

The reference generation circuit includes PMOS transistors MP1, MP2, bipolar transistors Q1, Q2, resistors R1, R2, R3, the sources of the PMOS transistors MP1 and MP2 are connected to VDD, the gates of the PMOS transistors MP1 and MP2 are short-circuited, The drain of the PMOS transistor MP1 is connected to the collector of the bipolar transistor Q1 and the gate of the PMOS transistor MP5 in the negative feedback loop of the mirror current source, and the drain of the PMOS transistor MP2 is connected to the collector of the bipolar transistor Q2 and the mirror image The gate of the PMOS transistor MP6 in the negative feedback loop of the current source is connected, one end of the resistor R3 is connected to the base of the bipolar transistor Q2, and the other end is connected to the base of the bipolar transistor Q1 and the resistor R6 in the reference voltage output circuit The resistor R2 is connected to the emitter of the bipolar transistor Q2, and the resistor R1 is connected between the common point of the emitters of the bipolar transistors Q1 and Q2 and the ground.

The reference voltage source of the adjustable multi-valued output of the present invention uses a mirror current source negative feedback loop instead of a high voltage gain operational amplifier to make the circuit structure simpler, and the source follower connected to the output terminal of the mirror current source negative feedback loop provides dual The polar transistor bias voltage is simultaneously generated with a bandgap reference voltage, and the connection of the circuit is optimized, so that an output voltage value with a small temperature coefficient can be obtained during operation. At the same time, according to the needs of the system, multiple reference voltage outputs can be obtained at the same time. The adjustable multi-value output reference voltage source of the present invention has the characteristics of low circuit power consumption, small temperature drift and strong power supply suppression capability.

Description of drawings:

Fig. 1 is the principle block diagram of the reference voltage source of adjustable multi-valued output of the present invention;

Fig. 2 is a circuit diagram of the reference voltage source of the adjustable multi-valued output of the present invention.

Detailed ways

In order to facilitate the understanding of those skilled in the art, the structural principle of the present invention will be further described in detail below in conjunction with specific embodiments and accompanying drawings:

As shown in Figure 1, a reference voltage source for adjustable multi-value output, a reference voltage source for adjustable multi-value output, a reference voltage source for adjustable multi-value output, including a reference generation circuit and a reference voltage output circuit, in the reference A start-up circuit and a mirror current source negative feedback loop are connected between the generating circuit and the reference voltage output circuit. One end of the start-up circuit is connected to the reference generating circuit, and the other end is connected to the mirror current source negative feedback loop. The other end of the feedback loop is connected with the reference voltage output circuit.

As shown in Figure 2, the negative feedback loop of the mirror image current source includes PMOS transistors MP5, MP6, NMOS transistors MN1, MN2, the gate of PMOS transistor MP5 is connected with the reference generation circuit, the source of MP5 is connected to VDD, and the gate of MP5 is connected to VDD. The drain is connected to the drain of the NMOS transistor MN2, the source of the NMOS transistor MN2 is grounded, the gate of the NMOS transistor MN2 is connected to the gate of the NMOS transistor MN1, the drain of the NMOS transistor MN1 is connected to the drain of the PMOS transistor MP6, and the PMOS transistor MP6 The grid of the PMOS transistor MP6 is connected to the reference generating circuit, the source of the PMOS transistor MP6 is connected to VDD, and the drain of the PMOS transistor MP6 is connected to the reference voltage output circuit.

The start-up circuit includes PMOS transistors MP3, MP4 and bipolar transistors Q3, Q4, the source terminal of the PMOS transistor MP3 is connected to VDD, the drain terminal is connected to the source terminal of the PMOS transistor MP4, and the gates of the PMOS transistors MP3 and MP4 are connected to each other. After being connected to ground, the drain of PMOS transistor MP4 is connected to the collector of bipolar transistor Q4, the emitter of bipolar transistor Q4 is grounded, its collector and base are short-circuited and simultaneously connected to the base of bipolar transistor Q3, The emitter and collector of the bipolar transistor Q3 are respectively connected to the reference generating circuit.

The reference voltage output circuit is a multi-valued reference voltage output circuit, which includes a source follower Q5, voltage dividing resistors R4, R5, R6, the base of the source follower Q5 and the mirror current source negative feedback loop The drain of the PMOS transistor MP6 is connected, the collector of Q5 is connected to VDD, the emitter is connected to the resistor R6 and leads to the output terminal of the reference voltage V2, the other end of the resistor R6 is connected to the resistor R5 and the reference generating circuit, and is between the resistors R6 and R5 The output end of the bandgap reference voltage VREF is drawn out, the other end of the resistor R5 is connected to the resistor R4, and the output end of the reference voltage V1 is drawn between the resistors R5 and R4, and the other end of the resistor R4 is grounded.

The reference generating circuit includes PMOS transistors MP1, MP2, bipolar transistors Q1, Q2, resistors R1, R2, R3, the sources of the PMOS transistors MP1 and MP2 are connected to VDD, the gates of the PMOS transistors MP1 and MP2 are short-circuited, The drain of the PMOS transistor MP1 is connected to the collector of the bipolar transistor Q1 and the gate of the PMOS transistor MP5 in the negative feedback loop of the mirror current source, and the drain of the PMOS transistor MP2 is connected to the collector of the bipolar transistor Q2 and the mirror image The gate of the PMOS transistor MP6 in the current source negative feedback loop is connected, one end of the resistor R3 is connected to the base of the bipolar transistor Q2, and the other end is connected to the base of the bipolar transistor Q1 and the resistor R6 in the reference voltage output circuit The resistor R2 is connected to the emitter of the bipolar transistor Q2, and the resistor R1 is connected between the common point of the emitters of the bipolar transistors Q1 and Q2 and the ground.

The present invention connects the output terminal of the mirror current source negative feedback loop with the reference voltage output circuit, the reference voltage output circuit is a multi-valued reference voltage output circuit, and the source follower included in the reference voltage output circuit provides bipolar type The transistor provides base bias, and on the one hand outputs multiple reference voltages through voltage dividing resistors.

PMOS管MP2的源极接VDD，栅极和PMOS管MP1短接，漏极接到PMOS管MP5的栅极，PMOS管MP5的源极接到VDD，漏极接到NMOS管MN2的漏极，NMOS管MN2的源极接地，栅极接NMOS管MN1的栅极，NMOS管MN1的漏极接PMOS管MP6的漏极。PMOS管MP1的源端接VDD，其栅漏短接接入PMOS管MP6的栅极，PMOS管MP6源极接VDD。源极跟随器双极型晶体管Q5作为源极跟随器，其集电极接VDD，其基极接PMOS管MP6的漏端，其发射极接电阻R6的电流输入端并在此输出基准电压V2。电阻R6的电流输出端接电阻R5的电流输入端并为双极型晶体管Q1、Q2提供基极偏置，产生带隙基准电压VREF。电阻R5的电流输出端接电阻R4的电流输入端并产生基准电压V1。电阻R4的电流输出端接地。The present invention uses mirror image current source negative feedback loop to replace high voltage gain operational amplifier, so that the circuit structure is simpler. The details are shown in Figure 2. In Figure 2, all NMOS transistors have the same width-to-length ratio, and all PMOS transistors have the same width-to-length ratio. Through the mirroring of MP1, MP5, MN2 and MN1, the currents on MP1 and Q1 branches are mirrored to the MN1 and MP6 branches. At the same time, through the mirror pair of MP1 and MP2, the saturation current flowing on MP2 is equal to the saturation current flowing on MP1. When outputting the bandgap reference voltage, MP1, MP2, MP6 and MN1 are all working in the saturation region, and the currents flowing through MP1, MP2 and MP6 are equal, VGSMP1=VGSMP6, that is, VDSMP1=VDSMP2, which eliminates the mirror image caused by the secondary effect of the MOSFET lost horses, ensured

The source of the PMOS transistor MP2 is connected to VDD, the gate is short-circuited to the PMOS transistor MP1, the drain is connected to the gate of the PMOS transistor MP5, the source of the PMOS transistor MP5 is connected to VDD, and the drain is connected to the drain of the NMOS transistor MN2. The source of the NMOS transistor MN2 is grounded, the gate is connected to the gate of the NMOS transistor MN1, and the drain of the NMOS transistor MN1 is connected to the drain of the PMOS transistor MP6. The source terminal of the PMOS transistor MP1 is connected to VDD, the gate and drain thereof are short-circuited to the gate of the PMOS transistor MP6, and the source of the PMOS transistor MP6 is connected to VDD. Source follower bipolar transistor Q5 is used as a source follower, its collector is connected to VDD, its base is connected to the drain of PMOS transistor MP6, its emitter is connected to the current input terminal of resistor R6 and the reference voltage V2 is output here. The current output terminal of the resistor R6 is connected to the current input terminal of the resistor R5 and provides base bias for the bipolar transistors Q1 and Q2 to generate a bandgap reference voltage VREF. The current output terminal of the resistor R5 is connected to the current input terminal of the resistor R4 to generate a reference voltage V1. The current output terminal of resistor R4 is grounded.

In the circuit of the present invention, the PMOS transistors MP3 and MP4 and the bipolar transistors Q3 and Q4 constitute a starting circuit. The source end of the PMOS transistor MP3 is connected to VDD, the drain end is connected to the source end of the PMOS transistor MP4, and the PMOS transistors MP3 and MP4 are connected to the ground. The drain terminal of the PMOS transistor MP4 is connected to the collector of the bipolar transistor Q4. The emitter of the bipolar transistor Q4 is grounded, its collector and base are short-circuited and simultaneously connected to the base of the bipolar transistor Q3. The emitter of the bipolar transistor Q3 is connected to the current input terminal of the resistor R1, and its collector is connected to the drain terminal of MP2. When the circuit is powered on, the base-emitter voltage difference of the bipolar transistors Q3 and Q4 generates a current in the resistor R1 to start the circuit.

产生。双极型晶体管Q1的集电极接PMOS管MP1的漏端，基极接电阻R6的电流输出端，发射极接电阻R1电流输入端。双极型晶体管Q2的集电极接PMOS管MP2的漏端，基极接电阻R3的电流输出端，电阻R3的电流输入端接电阻R6的电流输出端，发射极接电阻R2电流输入端，电阻R2电流输出端接电阻R1电流输入端，电阻R1电流输出端接地。In the present invention, the positive temperature coefficient is determined by the bipolar transistors Q1, Q2

produce. The collector of the bipolar transistor Q1 is connected to the drain of the PMOS transistor MP1, the base is connected to the current output terminal of the resistor R6, and the emitter is connected to the current input terminal of the resistor R1. The collector of the bipolar transistor Q2 is connected to the drain of the PMOS transistor MP2, the base is connected to the current output terminal of the resistor R3, the current input terminal of the resistor R3 is connected to the current output terminal of the resistor R6, the emitter is connected to the current input terminal of the resistor R2, and the resistor The current output terminal of R2 is connected to the current input terminal of the resistor R1, and the current output terminal of the resistor R1 is grounded.

It can be seen from the formula that the resistor R3 can correct the positive temperature coefficient voltage, and the resistor R3 can be converted into R2. The temperature coefficient of the reference voltage is deduced in detail below. From Figure 2 we can get:

Among them, the relationship between V _BE1 and temperature is as follows:

Combining formula (1) (2) (3) can get

According to the expression of (4), it can be obtained that the ratio of the emitter area of the bipolar transistors Q1 and Q2 and the ratio of the resistors R1 and R2 can be reasonably set to obtain a zero temperature coefficient at a specific temperature T ₀ . The base current of bipolar transistor Q2 flows into resistor R2 and contributes to the development of a voltage with a positive temperature coefficient. Because the collector current flowing through the bipolar transistors Q1 and Q2 is very small, β increases with the increase of temperature, combined with the formula (2), it can be seen that the second-order term of the reference voltage can be compensated when the temperature is high.

As shown in Figure 1 and Figure 2, the output terminal of the source follower connected to the output terminal of the negative feedback loop of the mirror current source is divided by voltage, on the one hand, it provides base bias for the bipolar transistor, on the other hand, through the division The piezoresistor outputs multiple reference voltages. in

在R11和R12之间就可以输出一个基准电压。We can see from the formula that by setting the ratio between the resistors, we can get a wide range of reference voltage values. On the branch where R1, R2, and R3 are located, we can subdivide the resistance values of these three resistors, that is, realize the same series resistance value by multiple resistors, then we can get another reference voltage between the resistors. Such as: we take

A reference voltage can be output between R11 and R12.

Because part of the current flowing through the resistor R3 is used as the base current of the bipolar transistors Q1 and Q2, there is a compromise between the current and the accuracy of the reference voltage _V2 .

In summary, the present invention can output multiple reference voltages. When outputting a reference voltage of 200mV within -40℃~+125℃, the temperature drift is less than 0.5mV

，负温系数电压是双极型晶体管Q1的V_be构成，从附图可以看出，其带隙基准电压为

其中，

M为双极性晶体管Q2、Q1的基区面积比。Q1、Q2、MP1、MP2、R2支路产生了PTAT电流，同时带隙基准电压在Q1的基极生成。The reference voltage source of the adjustable multi-valued output of the present invention passes through the negative feedback loop of current mirror (by MP1, MP2, MP5, MP6, MN1, MN2 and Q5, R6, R3, Q1, Q2, this loop is multiple Structural basis of value output) Make the collector currents flowing through the bipolar transistors Q1 and Q2 equal, and then generate a positive temperature coefficient voltage on the resistor R2

, the negative temperature coefficient voltage is composed of the V _be of the bipolar transistor Q1, as can be seen from the attached figure, its bandgap reference voltage is

in,

M is the base area ratio of the bipolar transistors Q2 and Q1. The Q1, Q2, MP1, MP2, R2 branches generate PTAT currents, while the bandgap reference voltage is generated at the base of Q1.

The above content is only a preferred embodiment of the present invention, and is not intended to limit the implementation of the present invention. Appropriate modifications or modifications made by those skilled in the art according to the concept of the present invention should be within the protection scope of the present invention. within.

Claims (3)

1. A reference voltage source of adjustable multi-valued output, comprising a reference generating circuit and a reference voltage output circuit, characterized in that: a starting circuit and a mirror current source negative feedback loop are connected between the reference generating circuit and the reference voltage output circuit One end of the start-up circuit is connected to the reference generating circuit, the other end is connected to the mirror current source negative feedback loop, and the other end of the mirror current source negative feedback loop is connected to the reference voltage output circuit. 2. The reference voltage source according to claim 1, characterized in that: the mirror image current source negative feedback loop comprises PMOS transistors MP5, MP6, NMOS transistors MN1, MN2, the grid of PMOS transistor MP5 and the reference generating circuit Connection, the source of MP5 is connected to VDD, the drain of MP5 is connected to the drain of NMOS transistor MN2, the source of NMOS transistor MN2 is grounded, the gate of NMOS transistor MN2 is connected to the gate of NMOS transistor MN1, and the drain of NMOS transistor MN1 The drain of the PMOS transistor MP6 is connected, the gate of the PMOS transistor MP6 is connected to the reference generating circuit, the source of the PMOS transistor MP6 is connected to VDD, and the drain of the PMOS transistor MP6 is connected to the reference voltage output circuit. 3. The reference voltage source according to claim 1 or 2, characterized in that: the reference voltage output circuit is a multi-valued reference voltage output circuit, which includes a source follower Q5, voltage dividing resistors R4, R5, R6 , the base of the source follower Q5 is connected to the drain of the PMOS transistor MP6 in the mirror current source negative feedback loop, the collector of Q5 is connected to VDD, the emitter is connected to the resistor R6 and leads to the output terminal of the reference voltage V2, and the resistor R6 The other end is connected to the resistor R5 and the reference generating circuit, and the bandgap reference voltage VREF output terminal is drawn between the resistors R6 and R5, and the other end of the resistor R5 is connected to the resistor R4, and the reference voltage V1 is drawn between the resistors R5 and R4 At the output end, the other end of the resistor R4 is grounded.

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