CN101834177A - Soc chip device - Google Patents

Abstract

The invention discloses an SOC chip device, which also comprises an SDRAM chip in the SOC chip device package, wherein the SDRAM chip is connected with the SOC chip through gold wires. The invention effectively reduces the electromagnetic radiation generated by the SDRAM signal wire, reduces the interference of the SDRAM signal wire to the wireless front end, improves the signal-to-noise ratio of the finally received signal and also improves the integration level of the device.

Description

SOC chip device

technical field

The invention relates to a semiconductor device, especially a SOC chip device.

Background technique

SDRAM (synchronous dynamic random access memory) synchronous dynamic random access memory is widely used in modern electronic design. Its biggest feature is high capacity and high speed, and it is used as data storage space or program storage space. It usually runs at a frequency of tens of megabytes or even hundreds of megabytes. Such a high-speed signal is extremely easy to generate high-frequency radiation signals. At the same time, there are many SDRAM signal lines, and the radiation sources also increase accordingly, which puts forward very high requirements for board-level EMI (electromagnetic compatibility). In the design of handheld terminal solutions, the radiation of high-speed devices such as SDRAM and FLASH has always been a difficult problem. In the prior art, in order to avoid the interference caused by radiation, the SDRAM chip device and the SOC chip are packaged separately, and then separately arranged on the PCB board, and the interference is reduced by increasing the distance between the two chips.

Contents of the invention

The technical problem to be solved by the present invention is to provide a SOC chip device, which can greatly reduce the mutual interference between the SDRAM chip and the radio frequency module, improve the signal-to-noise ratio of the entire link, and improve the integration degree of the device.

In order to solve the above technical problems, the technical solution of the SOC chip device of the present invention is that, in the package of the SOC chip device, an SDRAM chip is further included, and the SDRAM chip is connected to the SOC chip through a gold wire.

As a further improvement of the SOC chip device of the present invention, a rise and fall time control circuit is also provided between the SDRAM chip data signal interface and the pins of the package, and the rise and fall time control circuit includes a switch circuit, and the switch circuit From the power supply end to the ground end, it includes a first resistor, a first switch, a first PMOS transistor, a second switch and a second resistor in sequence, the first switch is connected to the source of the first PMOS transistor, and the second switch is connected to the source of the first PMOS transistor. To the gate and drain of the first PMOS transistor, the gate of the first PMOS transistor is connected to the pin of the package, the source of the first PMOS transistor is grounded through a capacitor, and the source of the first PMOS transistor The pole is also connected to the gate of the second PMOS transistor, the drain of the second PMOS transistor and the substrate end are grounded, and the source of the second PMOS transistor is connected to the data signal interface corresponding to the pin of the SDRAM chip and the package.

The invention very effectively reduces the electromagnetic radiation generated by the SDRAM signal line, reduces its interference to the wireless front end, improves the signal-to-noise ratio of the final received signal, and also improves the integration degree of the device.

Description of drawings

Below in conjunction with accompanying drawing and embodiment the present invention will be described in further detail:

FIG. 1 is a schematic diagram of the ideal signal reflow;

Figure 2 is a schematic diagram of the signal backflow in the actual situation;

Fig. 3 is a schematic diagram of magnetic field coupling of a signal loop;

Fig. 4 is the schematic diagram of rising and falling time control circuit in SOC chip device of the present invention;

FIG. 5 is a schematic diagram of chip positions in the SOC chip device of the present invention.

The references in the figure are marked as

Detailed ways

Electromagnetic interference is EMI (Electromagnetic Interference), which means that the system emits electromagnetic waves through conduction or radiation and affects the normal operation of other systems or other subsystems in the system. For EMI, it can be divided into three forms: radiation interference, conduction interference and inductive coupling interference according to the way of electromagnetic interference. Radiation interference means that if the disturbance source is not in a fully enclosed metal shell, it can radiate electromagnetic waves through space. The radiation field strength depends on the disturbance current intensity of the device, the equivalent impedance of the device, and the disturbance source. transmit frequency. If the metal shell of the disturbance source has gaps and holes, the intensity of the radiation is related to the wavelength of the interference signal. When the size and wavelength of the hole can be compared, it can form an interference sub-radiation source to radiate to the surroundings, and metal objects in the radiation field can also form secondary radiation; conduction interference, as the name implies, the source of disturbance mainly uses the wires connected to it to radiate to the outside. Emission can also bring interference into other circuits through public impedance coupling or ground loop coupling. Conducted interference is an important form of electromagnetic interference; the way of inductively coupled interference is the third between the radiation path and the conduction path. In this way, when the frequency of the disturbance source is low, the radiation capability of the disturbance power supply is limited. At the same time, the disturbance is not directly connected to other conductors. At this time, the electromagnetic disturbance energy generates inductive coupling through its adjacent conductors, transfers the electromagnetic energy to other conductors, and induces disturbance current or voltage in the adjacent conductors. Inductive coupling can occur in the form of capacitive coupling between conductors, or in the form of inductive coupling or a mixture of capacitance and inductance.

There are usually two paths for EMI generation, mainly voltage transients and signal backflow.

For high-speed digital periods, voltage transients when high-frequency AC signals are generated are an important cause of electromagnetic interference. The frequency spectrum generated by the digital signal at the switching output is not single, but a lot of high-order harmonic components are integrated. The amplitude of these harmonics is determined by the rise or fall time of the device. The faster the signal rises and falls, the higher the switching frequency , the more radiant energy is produced. The leakage of this electromagnetic energy will cause electromagnetic interference problems.

Another cause of electromagnetic radiation is signal backflow. Ideally, the return flow exists at the reference plane directly below the signal trace as shown in Figure 1. But in fact, the signal backflow is multi-faceted: the reference plane, adjacent traces, and the medium may all become the backflow path. Ideally, due to the small loop area between the signal and ground return, the EMI generated is also very low. However, if there are non-ideal factors such as gaps on the adjacent reference planes, the return area will increase, the coupling effect of low inductance will be weakened, and more electromagnetic energy radiation will increase, as shown in Figure 2.

Figure 3 analyzes the influence of EMI from the perspective of magnetic lines of force. It can be seen from the figure that the external area of the signal and the reflow can cancel each other due to the opposite polarity of the magnetic field, while the magnetic field in the middle reflow area is mutually enhanced, so it is the main source of external radiation. From this figure, we can see that as long as the distance between the signal and the return flow is shortened, the influence of the periphery can be well offset, and the influence of this loop on the external circuit can also be greatly suppressed.

The invention discloses a SOC chip device. As shown in FIG. 5 , the package of the SOC chip device further includes an SDRAM chip, and the SDRAM chip is connected to the SOC chip through a gold wire.

As shown in Figure 4, a rise and fall time control circuit is also provided between the SDRAM chip data signal interface and the pins of the package, and the rise and fall time control circuit includes a switch circuit, and the switch circuit is connected from the power supply end to the ground. The terminal includes a first resistor, a first switch, a first PMOS transistor, a second switch and a second resistor in turn, the first switch is connected to the source of the first PMOS transistor, and the second switch is connected to the first PMOS transistor The gate and drain of the first PMOS transistor are connected to the pins of the package, the source of the first PMOS transistor is grounded through a capacitor, and the source of the first PMOS transistor is also connected to the second The gate of the PMOS transistor, the drain and the substrate of the second PMOS transistor are grounded, and the source of the second PMOS transistor is connected to the data signal interface corresponding to the pin of the SDRAM chip and the package.

In the embodiment of FIG. 4, the rise and fall time control circuit includes multiple groups of switch circuits connected in parallel, the gates of the first PMOS transistors in each switch circuit are connected to the pins of the package, and the last switch circuit The source of the first PMOS transistor is connected to the capacitor.

Irctrl is a set of rise time control signals. When the switch is closed, the resistance between the power supply and the load capacitor Ci becomes smaller, the charging current becomes larger, and the signal rise time becomes shorter. Through the configuration of the Irctrl<x:0> bus control signal, where x is the number of switch circuits, the rise time of the output signal can be changed. The more switches closed, the shorter the rise time of the signal. If the rise time becomes longer, it means that the frequency of the radiated signal becomes smaller, the energy of its high-order harmonics becomes smaller, and the radiation to the high-frequency band is correspondingly reduced.

Similarly, Ifctrl is a group of falling time control signals. When the switch is closed, the discharge current from the load capacitor Ci becomes larger, the discharge time becomes shorter, and the signal fall time becomes shorter. By controlling the Ifctrl<x:0> bus signal, the fall time of the output signal can be changed, and the radiation signal introduced when the signal falls can be effectively controlled.

As shown in FIG. 5, the SDRAM chip is arranged in the area of the digital circuit part on the SOC chip.

In the SOC chip, the radio frequency module is arranged at the corner of the chip.

The SDRAM chip is connected to the SOC chip through a gold wire as short as possible.

In Figure 5, the bottom chip is an SOC chip, the top is an SDRAM chip, and the middle connection is a gold wire. In this embodiment, the layout of the SOC chip is designed in consideration of reducing electromagnetic radiation: the radio frequency circuit is arranged in area A in Figure 5, and the most easily disturbed radio frequency input pin is placed in the upper left corner of the chip. Area B is other analog circuits of the receive chain, including analog filters, phase-locked loops, digital-to-analog converters, analog-to-digital converters, etc. The digital part of the circuit is arranged in the C area, which is located directly below the SDRAM. Both are digital circuits, and the interference between them will not affect the circuit function. The connecting gold wire is very short, usually only 1 to 2 mm, and the current loop area is very small. Compared with the traditional design of placing SDRAM on the PCB, its radiation intensity is a few tenths or even smaller than that at the board level. At the same time, the loop between the SDRAM power supply and the ground also becomes very small with this design, and the radiation can be limited to a small range.

In order to reduce the radiation interference of the signal line of the SDRAM, the present invention starts from two aspects. Firstly, the area of the signal line backflow is reduced, and secondly, the rising time and the falling time of the signal line are reduced. Considering from these two starting points, the present invention packages SDRAM in the SOC (System On Chip, system on chip) chip. In the present invention, the SDRAM chip die is fixedly stacked on the SOC chip, with the pad facing upwards, and a pad connected to the SDRAM is reserved inside the SOC chip, and then the two chips are connected together with a gold wire. Since SDRAM pads and SOC pads are directly connected by gold wires, the length of gold wires is generally 1 to 2 mm, that is, the current loop area is very small, much smaller than the board-level PCB wiring loop, so the EMI radiation generated will also be reduced. It is much smaller, which can effectively reduce the interference to the wireless radio frequency front-end circuit. In addition, on the pad connected to the SDRAM of the SOC, an output drive controllable circuit is added, which can effectively control the rise time and fall time of the pad, and reduce the radiation of the signal change edge to the peripheral circuit. SDRAM is packaged in SOC so that the control of this time edge will not affect the access speed of SDRAM, because the signal delay of SDRAM is shortened correspondingly because SDRAM is packaged in SOC.

To sum up, the present invention effectively reduces the electromagnetic radiation generated by the SDRAM signal line, reduces its interference to the wireless front end, improves the signal-to-noise ratio of the final received signal, and also improves the integration of the device.

Claims (6)

1. A kind of SOC chip device, it is characterized in that, in described SOC chip device package, also comprise SDRAM chip, described SDRAM chip is connected with described SOC chip by gold wire. 2. SOC chip device according to claim 1, is characterized in that, also be provided with rise and fall time control circuit between described SDRAM chip data signal interface and the pin of encapsulation, comprise switch in the described rise and fall time control circuit A circuit, the switch circuit sequentially includes a first resistor, a first switch, a first PMOS transistor, a second switch and a second resistor from the power supply terminal to the ground terminal, the first switch is connected to the source of the first PMOS transistor, The second switch is connected to the gate and drain of the first PMOS transistor, the gate of the first PMOS transistor is connected to the pin of the package, and the source of the first PMOS transistor is grounded through a capacitor. The source of the first PMOS transistor is also connected to the gate of the second PMOS transistor, the drain and substrate of the second PMOS transistor are grounded, and the source of the second PMOS transistor is connected to the pin phase of the SDRAM chip and package. Corresponding data signal interface. 3. The SOC chip device according to claim 2, characterized in that, the rise and fall time control circuit comprises multiple groups of switch circuits connected in parallel, and the gates of the first PMOS transistors in each switch circuit are all connected to the The pin of the package, the source of the first PMOS transistor of the last switching circuit is connected to the capacitor. 4. The SOC chip device according to any one of claims 1-3, characterized in that, the SDRAM chip is arranged in the area of the digital circuit part on the SOC chip. 5. The SOC chip device according to any one of claims 1-3, characterized in that, the SOC chip further includes a radio frequency module, and the radio frequency module is arranged at a corner of the chip. 6. The SOC chip device according to any one of claims 1-3, characterized in that, the SDRAM chip is connected to the SOC chip through a gold wire as short as possible.

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