CN101807913B - Low-speed clock enable signal generation method, device and equipment - Google Patents

Abstract

The embodiment of the present invention discloses a method, device and equipment for generating a low-speed clock enable signal, which relates to the field of mobile communication technology and realizes the use of a high-speed clock to simulate a fixed-ratio low-speed clock. The device includes: an equivalent circuit that realizes the modulo operation effect by combining a first selector, a second selector, a register, a comparator, an adder and a subtractor. The method includes: in the cycle of the nth high-speed clock, the remainder M obtained by dividing n times C by P is compared with the C; if the remainder M is less than C, a valid low-speed clock enable signal is output; if the remainder M is greater than or equal to C, an invalid low-speed clock enable signal is output; wherein the integer ratio of the high-speed clock to the low-speed clock is: P/C, P is the integer value of the high-speed clock, C is the integer value of the low-speed clock, n=1,..., P. The present invention is applied to communication technology.

Description

Method, device and device for generating low-speed clock enable signal

technical field

The present invention relates to the communication field, in particular to a method, device and equipment for generating a low-speed clock enabling signal.

Background technique

With the expansion of the chip scale and the increase of functions, the number of compatible interfaces has also increased exponentially. At present, most chips have multiple clock domains. Chips with multiple clock domains have asynchronous and power consumption problems. To solve the above problems, the chip needs to be enlarged. The capacity directly leads to the increase of chip cost.

For multi-clock domain chips, the multi-clock frequency point scheme of the same source clock is mainly realized by a built-in or external phase-locked loop (Phase Locked Loop, PLL for short), and a system clock is used to generate clock branches with different clock frequency points. Limited by the configuration coefficient of the PLL, using the PLL at the same time will increase the cost of the chip or chip-level solution, and the expansion of the frequency division coefficient needs to be at the cost of an increase in cost.

In view of the above defects, the prior art provides an implementation scheme in which the highest clock frequency is used as the frequency of the system clock, and the clocks of other frequencies are replaced by the system clock + a clock enabling gap (gap). This solution can achieve the effect that only one crystal oscillator provides the clock, and different clock enable gaps represent different clock domains, which eliminates the problem of asynchronous processing.

Specifically, when a high-speed clock is used to simulate a low-speed clock, a ripple counter is used to realize the enable signal of the low-speed clock. For example, if a 100MHz clock is used to simulate a 50MHz clock, a 1-bit counter can be designed with a 100MHz clock, which can be flipped between 0/1 to indicate a frequency division factor of 1/2 to achieve the frequency division effect of a 50MHz clock. For the case where the frequency division coefficient is more complicated, A*(B*CLK+1*gap)+(C*CLK+1*gap) can be used, that is, the method of using a high-speed clock to generate two fast and slow patterns to simulate a low-speed clock. Implements a low-speed clock enable signal. Among them, ""B*CLK+1*gap" means a fast pattern, and its physical meaning is B effective clock cycles + 1 invalid clock cycle (gap); "C*CLK+1*gap" means a slow pattern, and its physical meaning is The meaning is C valid clock cycles + 1 invalid clock cycle (gap); the total formula A*(B*CLK+1*gap)+(C*CLK+1*gap) means A*(B+1 )+(C+1) clock cycles, A fast pattern and 1 slow pattern to simulate the low-speed clock enable signal, where the frequency ratio of the low-speed clock to the high-speed clock is (A*B+C)/(A* (B+1)+(C+1)).

Due to the clock index requirements of the communication transmission system, the low-speed clock simulated by the high-speed clock needs to achieve the best uniform effect in exchange for the best clock jitter performance. Therefore, the clock index of the chip system is related to the uniformity of the clock enable signal gap . When realizing the above-mentioned scheme, the inventor finds that there are at least the following problems in the technical scheme of the prior art: for the relatively complicated situation of the frequency division system N/M, especially when the least common multiple of N and M is large, using A*(B *CLK+1*gap)+(C*CLK+1*gap) The result obtained by the formula is not ideal, the generated frequency deviation is large, and the clock enable signal is uneven, which leads to deviation of the simulated clock.

Contents of the invention

Embodiments of the present invention provide a method, device and device for generating a low-speed clock enabling signal, which can simulate a low-speed clock with a fixed ratio using a high-speed clock.

In order to solve the above technical problems, the embodiment of the present invention adopts the following technical solutions:

A low-speed clock enabling signal generating device, including: a first selector, a second selector, a register, a comparator, an adder, and a subtractor, wherein the integer ratio of the high-speed clock to the low-speed clock is: P/C, P is the integer value of the high-speed clock, and C is the integer value of the low-speed clock, then,

The first input end of the first selector is used to receive the low-speed clock integer value C, its second input end is coupled to the output end of the adder, its control input end is used to receive a reset signal, and its output end is coupled to an input to said register;

The input end of the register is coupled to the output end of the first selector, its drive end is used to receive a high-speed clock, and its output end is respectively coupled to the input end of the comparator, the first selector of the second selector input and a first input of said subtractor;

The first input end of the comparator is coupled to the output end of the register, its second input end is used to receive the high-speed clock integer value P, and its output end outputs a low-speed clock enable signal and is coupled to the second selector the control input terminal;

The first input of the second selector is coupled to the output of the register, its control input is coupled to the output of the comparator, and its second input is coupled to the output of the subtractor, which an output coupled to a second input of the adder;

The first input of the subtractor is coupled to the output of the register, the second input of which is adapted to receive a high-speed clock integer value P, and the output of which is coupled to the second input of the second selector;

The adder has a first input for receiving a low-speed clock integer value C, a second input coupled to the output of the second selector, and an output coupled to the second input of the first selector end.

A method for generating a low-speed clock enable signal, comprising:

In the period of the nth high-speed clock, the remainder M obtained by dividing n times of C by P is compared with the C;

If the remainder M is less than C, an effective low-speed clock enable signal is output; if the remainder M is greater than or equal to C, an invalid low-speed clock enable signal is output;

Wherein, the integer ratio of the high-speed clock to the low-speed clock is: P/C, where P is the integer value of the high-speed clock, C is the integer value of the low-speed clock, n=1, . . . , P.

A low-speed clock enable signal generating device, comprising:

The comparison unit is used to compare the remainder M obtained by dividing n times of C by P with the C in the cycle of the nth high-speed clock; wherein, the integer ratio of the high-speed clock to the low-speed clock is : P/C, P is the integer value of the high-speed clock, C is the integer value of the low-speed clock, n=1, ..., P;

An output unit, configured to output a valid low-speed clock enable signal if the remainder M is less than C; output an invalid low-speed clock enable signal if the remainder M is greater than or equal to C.

The low-speed clock enable signal generation method, device and equipment provided by the embodiments of the present invention utilize the Sigma-Delta algorithm, and according to the integer ratio of the obtained high-speed clock to the simulated low-speed clock and the integer value of the high-speed clock and the integer value of the low-speed clock, In the cycle of the integer value of the high-speed clock, the remainder M obtained by dividing n times the integer value of the low-speed clock by the integer value of the high-speed clock is compared with the integer value of the low-speed clock, and when the remainder M is less than the integer value of the low-speed clock, an effective low-speed clock is output The enable signal, when the remainder M is greater than or equal to the integer value of the low-speed clock, an invalid low-speed clock enable signal is output, so that the equivalent circuit of the Sigma-Delta algorithm is used to output a uniform low-speed clock enable signal, thereby realizing complex clock frequency division, The high-speed clock is simulated as a fixed-ratio low-speed clock output.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only of the present invention. For some embodiments, those of ordinary skill in the art can also obtain other drawings based on these drawings without any creative effort.

1 is a flowchart of a method for generating a low-speed clock enable signal according to an embodiment of the present invention;

2 is a schematic structural diagram of a low-speed clock enable signal generating device according to an embodiment of the present invention;

3 is a schematic structural diagram of a low-speed clock enable signal generating device according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a circuit structure for bundling control of a low-speed clock enable signal and a system clock according to an embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Embodiments of the present invention provide a method, device and device for generating a low-speed clock enabling signal, so as to simulate a low-speed clock with a fixed ratio using a high-speed clock.

Embodiment one

An embodiment of the present invention provides a method for generating a low-speed clock enable signal, as shown in FIG. 1 , the method includes:

Step 101, in the cycle of the nth high-speed clock, divide the remainder M obtained by dividing n times of C by P and compare it with the C;

Step 102, if the remainder M is less than C, output a valid low-speed clock enable signal; if the remainder M is greater than or equal to C, output an invalid low-speed clock enable signal;

Wherein, the integer ratio of the high-speed clock to the low-speed clock is: P/C, where P is the integer value of the high-speed clock, C is the integer value of the low-speed clock, n=1, . . . , P.

The method provided in this embodiment uses the Sigma-Delta algorithm to generate a low-speed clock enable signal, thereby simulating the high-speed clock as a low-speed clock output. In the following, the high-speed clock is used as the system clock used by the 10GE customer service, and the simulated low-speed clock is ODU2E The service clock is taken as an example for description. Among them, 10GE and ODU2E are the service types of synchronous Ethernet and OTN transport network, with service rates of 10.3125Gbit/s and 10.3558Gbit/s respectively, and are mainly used to load low-speed transmission services and data packet services in the transport network.

When the 10GE customer service is applied to the transmission network, the data stream is encapsulated into an ODU (Optical Channel Data Unit) structure using a hardware speed-up method and then transmitted through a synchronous backplane. Use the backplane clock as the system clock, the clock frequency is 174.96MHz, and the analog clock is the ODU2E service clock. According to the corresponding relationship between 10GE and ODU2E frame structure (239/237), the clock frequency value of the ODU2E service clock is 162.49258306962025316455696202532MHz (only the digits after the decimal point are displayed here, and this value is not accurate), so the system clock cannot be used to achieve absolute The frequency deviation of 0ppm (Parts Permillion, representing parts per million) needs to intercept the value of the simulated low-speed clock to make it within the tolerable frequency deviation range of the system, such as +/-1ppm, and set the value of the ODU2E service clock 162.4925MHz, which can be converted into an integer ratio of 60865:65535, and the analog clock frequency deviation is 1.03592ppm, which is an acceptable frequency deviation range for the system.

If P=65535, C=60865, when n=1, M=(nC)MODP=60865=C=60865, then output an invalid clock enable signal; when n=2, M=(nC)MODP= 56195<C=60865, it will still output a valid clock enable signal; when n=3, M=(nC)MODP=51525<C=60865, it will still output a valid clock enable signal; when n=4 , M=(nC)MODP=46855<C=60865, then a valid clock enable signal is still output; ......When n=N, M=(nC)MODP≥C=60865, then the output is invalid clock enable signals; ......, wherein, 60865 effective clock enable signals are output, and 65535−60865=4670 invalid clock enable signals are output.

The embodiment of the present invention also provides a low-speed clock enable signal generating device, as shown in FIG. 2 , the device includes: a comparison unit 11 and an output unit 12

The comparison unit 11 is used to compare the remainder M obtained by dividing n times of C by P in the cycle of the nth high-speed clock with the C; wherein, the integer ratio of the high-speed clock to the low-speed clock Be: P/C, P is the integer value of high-speed clock, C is the integer value of low-speed clock, n=1,..., P; Output unit 12, is used for if described remainder M is less than C, then output is valid low-speed clock enable signal; if the remainder M is greater than or equal to C, an invalid low-speed clock enable signal is output. That is, if M=(nC)MODP<C, an effective low-speed clock enable signal is output; if M=(nC)MODP≥C, an invalid low-speed clock enable signal is output, and MOD is a modulo operation.

The low-speed clock enable signal generation method and device provided by the embodiments of the present invention utilize the Sigma-Delta algorithm, according to the integer ratio of the obtained high-speed clock to the simulated low-speed clock and the integer value of the high-speed clock and the integer value of the low-speed clock. In the cycle of the integer value of the clock, the remainder M obtained by dividing n times the integer value of the low-speed clock by the integer value of the high-speed clock is compared with the integer value of the low-speed clock, and when the remainder M is smaller than the integer value of the low-speed clock, the effective low-speed clock is output. Signal, when the remainder M is greater than or equal to the integer value of the low-speed clock, an invalid low-speed clock enable signal is output, so that the Sigma-Delta algorithm equivalent circuit is used to output a uniform low-speed clock enable signal, and complex clock frequency division is realized.

Embodiment two

The method for generating the low-speed clock enabling signal by using the Sigma-Delta algorithm described in Embodiment 1 is difficult to simulate by the equivalent circuit of taking the remainder, so the low-speed clock enabling signal generating device proposed in this embodiment based on the above method is An equivalent circuit that utilizes the combination of an adder and a subtractor to realize the effect of a modulo operation, as shown in Figure 3, the device includes: a first selector 1, a second selector 2, a register 3, a comparator 4, an addition The logic combination circuit formed by the device 5 and the subtractor 6 can be replaced by a fixed device, wherein the integer ratio of the high-speed clock to the low-speed clock is: P/C, P is the integer value of the high-speed clock, and C is the integer value of the low-speed clock, then,

The first input end of the first selector 1 is connected to the output end of the low-speed clock integer value C for receiving the low-speed clock integer value C, and its second input end is coupled to the output end of the adder 5, which controls The input terminal is used to receive the reset signal RST, and its output terminal is coupled to the input terminal of the register 3;

The first input end of the register 3 is coupled to the output end of the first selector 1, its second input end (ie, the driving end) is connected to a high-speed clock, and its output end is respectively coupled to the input end of the comparator 4 , the first input end of the second selector 2 and the first input end of the subtractor 6;

The first input end of the comparator 4 is coupled to the output end of the register 3, and its second input end is connected to the output end of the high-speed clock integer value P for receiving the high-speed clock integer value P, and its output end outputs the low-speed clock integer value P. A clock enable signal coupled to the control input of the second selector 2;

The first input terminal of the second selector 2 is coupled to the output terminal of the register 3, its control input terminal is coupled to the output terminal of the comparator 4, and its second input terminal is coupled to the subtractor 6 an output terminal, the output terminal of which is coupled to the second input terminal of the adder 5;

The first input end of the subtractor 6 is coupled to the output end of the register 3, and its second input end is connected to the output end of the output high-speed clock integer value P for receiving the high-speed clock integer value P, and its output end coupled to the second input of the second selector 2;

The first input end of the adder 5 is connected to the output end of the output low-speed clock integer value C for receiving the low-speed clock integer value C, and its second input end is coupled to the output end of the second selector 2, Its output terminal is coupled to the second input terminal of the first selector 1 .

Wherein, the register can be a rising edge trigger or a falling edge trigger, driven by a high-speed clock, and flipped according to the high-speed clock. Alternatively, if a double-edge trigger is adopted, a rising-edge trigger or a falling-edge trigger can be selected as the flip condition of the trigger according to actual system applications. Further, the high-speed clock may use a system clock.

Still taking the high-speed clock as the system clock used by the 10GE customer service and the analog low-speed clock as the ODU2E service clock as an example for illustration.

The clock frequency of the 10GE customer service is 174.96MHz, and the analog clock is the ODU2E service clock. According to the corresponding relationship between 10GE and ODU2E frame structure (239/237), the clock frequency value of the ODU2E service clock is 162.49258306962025316455696202532MHz, and the value of the ODU2E service clock is 162.4925MHz, which can be converted into an integer ratio of the two: 60865:65535, The simulated clock frequency deviation is 1.03592ppm, which is the acceptable frequency deviation range of the system.

The values 60865 and 65535 are respectively used as the input values C and P of the Sigma-Delta equivalent circuit, and the system clock (clk_sys=174.96MHz) is used as the driving clock of the circuit, then the output low-speed clock enable signal gap and the system clock (clk_sys= 174.96MHz) is equivalent to an analog clock (ODU2E), that is, the low-speed clock enable signal gap is used as an indication of the high-speed clock, and is used in conjunction with the high-speed clock, that is, the system clock. If the low-speed clock enable signal gap is valid, the system clock is output; the low-speed clock If the enable signal gap is invalid, the system clock is shielded.

If W _N =(Y _N-1 +C)<P, output an invalid low-speed clock enable signal; if W _N =(Y _N-1 +C)≥P, output a valid low-speed clock enable signal. (Wherein, if W _N-1 <P, then Y _N-1 =P; if W _N-1 ≥P, then Y _N-1 =W _N-1 -P; W is the value output in register 3, Y is the value output in the second selector.)

Then in the cycles of P high-speed clocks, as shown in Figure 3, the comparator 4 obtains the value W in the register 3 and compares it with P, and if W<P, an invalid low-speed clock enable signal is output; if W≥P , then output an effective low-speed clock enable signal, that is, essentially generate a low-speed clock enable signal gap, indicating that within 65535 (P) clock cycles, there are 60865 (C) effective low-speed clock enable signals, using gap=0 Indication; 4670 (65535-60865) invalid low-speed clock enable signals, indicated by gap=1. Among them, the effective low-speed clock enable signal (C) is evenly distributed in all clock cycles (P), and the implementation process is as follows:

The driving clock is the system clock (clk_sys=174.96MHz), and the register 3 can be triggered by the rising edge of the clock, that is, the register value is updated once every clock cycle;

In P clock cycles, initialization is first performed, the reset signal RST is valid, and the first selector 1 resets the register 3 to the C value after the circuit is started, and the comparator 4 compares the register value (C) with the P value at this time, Since C<P, the low-speed clock enable signal gap output at this time is 1, indicating that the first clock cycle position is an invalid low-speed clock enable signal; at the same time, the low-speed clock enable signal gap=1 controls the second selector 2 select the register value (C) as the input of the adder 5, then the output value of the adder is 2C;

At the rising edge of the first system clock clk_sys after the reset is canceled, the register 3 latches the input value. Since the reset signal has been canceled at this time, the first selector 1 selects the output value of the adder 5 as the input of the register 3, then The stored value of register 3 is refreshed to 2C; the comparator 4 compares the register value (2C) with the P value, and since 2C>P, the low-speed clock enable signal gap output at this time is 0, indicating that the clock cycle position is valid Low-speed clock enable signal; Simultaneously, this clock enable signal gap=0 controls the second selector 2 to select the output value (2C-P) of subtractor 6 as the input of adder 6, then adder 6 output value (3C -P);

At the rising edge of the second system clock clk_sys, register 3 latches the input value again, and the subsequent work is consistent with the above;

In P clock cycles, the circuit outputs signal gap=0 for C clock cycles, indicating that the low-speed clock enable signal of this clock cycle is valid; (P-C) clock cycle output signal gap=1, indicating that the low-speed clock enable signal of this clock cycle is valid. The energy signal is invalid.

After the circuit works for P clock cycles, the register value is re-duplicated as C after operation, then the first operation cycle ends and the next operation cycle enters. The reversal of the circuit is completely consistent with the output of the low-speed clock enable signal gap.

As shown in FIG. 3, the reset signal RST of the first selector 1 is used to control the first selector 1. When the reset signal is valid, the first selector 1 selects and outputs the received low-speed clock integer value C. When When the reset signal is invalid, the first selector 1 selects and outputs the value obtained from the adder 5 . Those skilled in the art can understand that the reset mode is not limited to the one shown in FIG. 3 , and the second input terminal of the first selector 1 can be controlled by software or hardware to input a reset signal when reset is required.

Further, the device shown in FIG. 3 may further include: a low-speed clock generating unit, configured to generate the low-speed clock by using the low-speed clock enabling signal and the high-speed clock.

The low-speed clock enable signal gap output by the device provided in this embodiment is used in conjunction with the system clock clk_sys to control the inversion of the circuit, that is, when the low-speed clock enable signal gap is valid, the circuit works normally; when the low-speed clock enable signal gap is invalid , the circuit remains. As shown in Figure 4, the low-speed clock enable signal gap is bundled with the system clock clk_sys to control the inversion of the D flip-flop, and further, the low-speed clock enable signal gap can be used as the gating clock clock-gate of the system clock The control signal can achieve the effect of reducing the dynamic power consumption of the circuit. The clock-gate circuit of the gated clock is generally provided by the back-end manufacturer to realize low-power processing of the circuit. The working principle in Figure 4 is that the clock-gate outputs a clock to drive the D flip-flop to flip when gap=0, and flips when gap=1 If the clock is shielded, the D flip-flop keeps the original value without flipping at this time, so as to achieve the effect of low power consumption.

In the technical solution of this embodiment, the equivalent circuit of the Sigma-Delta algorithm is used. According to the integer ratio of the obtained high-speed clock and the simulated low-speed clock and the integer value of the high-speed clock and the integer value of the low-speed clock, the integer value of the high-speed clock In the period of , the first comparator 1 obtains the value W in the register 3 and compares it with P, if W<P, then outputs a valid low-speed clock enable signal; if W≥P, then outputs an invalid low-speed clock enable signal , so that the high-speed clock is simulated as a low-speed clock output by using the equivalent circuit of the Sigma-Delta algorithm, realizing complex clock frequency division, outputting a uniform low-speed clock enable signal, and further achieving uniformity, avoiding unnecessary frequent jumps , to get the best clock jitter and drift performance.

Through the description of the above embodiments, those skilled in the art can clearly understand that the present invention can be realized by means of software plus necessary general-purpose hardware, and of course also by hardware, but in many cases the former is a better embodiment . Based on this understanding, the essence of the technical solution of the present invention or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product is stored in a readable storage medium, such as a floppy disk of a computer , a hard disk or an optical disk, etc., including several instructions for enabling a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments of the present invention.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (10)

1. a low-speed clock enable signal produces equipment, it is characterized in that, comprising: first selector, second selector, register, comparator, adder and subtracter; Wherein, The integer ratio of high-frequency clock and low-speed clock is: P/C, P are the high-frequency clock integer value, and C is the low-speed clock integer value; Then

The first input end of said first selector is used to receive low-speed clock integer value C; Its second input is coupled to the output of said adder, and its control input end is used to receive reset signal, and its output is coupled to the input of said register; When said reset signal is effective; The low-speed clock integer value C that said first selector selects output to receive, when said reset signal is invalid, the value that said first selector selects output to obtain from said adder;

The input of said register is coupled to the output of said first selector; Its drive end is used to receive high-frequency clock, and its output is coupled respectively to the first input end of the input of said comparator, said second selector and the first input end of said subtracter;

The first input end of said comparator is coupled to the output of said register, and its second input is used to receive high-frequency clock integer value P, and its output is exported low-speed clock enable signal gap and is coupled to the control input end of said second selector; If W＜P; Then export invalid low-speed clock enable signal gap=1, if W >=P then exports effective low-speed clock enable signal gap=0; Wherein, W is the value of exporting in the said register;

The first input end of said second selector is coupled to the output of said register; Its control input end is coupled to the output of said comparator; Its second input is coupled to the output of said subtracter; Its output is coupled to second input of said adder; Invalid low-speed clock enable signal gap=1 controls said second selector and selects the input of the value of said register as said adder, and effectively low-speed clock enable signal gap=0 controls said second selector and selects the input of the output valve of subtracter as adder;

The first input end of said subtracter is coupled to the output of said register, and its second input is used to receive high-frequency clock integer value P, and its output is coupled to second input of said second selector;

The first input end of said adder is used to receive low-speed clock integer value C, and its second input is coupled to the output of said second selector, and its output is coupled to second input of said first selector.

2. equipment according to claim 1 is characterized in that, said register is rising edge trigger or trailing edge trigger.

3. equipment according to claim 1; It is characterized in that; The low-speed clock enable signal of said comparator output is used to control said second selector, when said low-speed clock enable signal is effective clock enable signal, and the value that said second selector selects output to obtain from said register; When said low-speed clock enable signal is invalid clock enable signal, the value that said second selector selects output to obtain from said subtracter.

4. equipment according to claim 1; It is characterized in that; Said reset signal is used to control said first selector, when reset signal is effective, and the low-speed clock integer value C that said first selector selects output to receive; When reset signal is invalid, the value that said first selector selects output to obtain from said adder.

5. according to each described equipment in the claim 1 to 4, it is characterized in that, also comprise:

The low-speed clock generation unit is used to utilize said low-speed clock enable signal and said high-frequency clock to generate said low-speed clock.

6. a low-speed clock enable signal production method is characterized in that, comprising:

In the cycle of n high-frequency clock, the n of C is doubly compared with said C divided by the resulting remainder M of P;

If said remainder M less than C, then exports effective low-speed clock enable signal; If said remainder M more than or equal to C, then exports invalid low-speed clock enable signal;

Wherein, the integer ratio of said high-frequency clock and said low-speed clock is: P/C, P are the high-frequency clock integer value, and C is the low-speed clock integer value, n=1 ..., P.

7. method according to claim 6 is characterized in that, said high-frequency clock is a system clock.

8. according to claim 6 or 7 described methods, it is characterized in that, also comprise: utilize the low-speed clock enable signal and the said high-frequency clock of output to generate said low-speed clock.

9. a low-speed clock enable signal generation device is characterized in that, comprising:

Comparing unit was used in the cycle of n high-frequency clock, and the n of C is doubly compared with said C divided by the resulting remainder M of P; Wherein, the integer ratio of said high-frequency clock and said low-speed clock is: P/C, P are the high-frequency clock integer value, and C is the low-speed clock integer value, n=1 ..., P;

Output unit is used for if said remainder M less than C, then exports effective low-speed clock enable signal; If said remainder M more than or equal to C, then exports invalid low-speed clock enable signal.

10. device according to claim 9 is characterized in that, said high-frequency clock is a system clock.

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