CN101803917A - Bio-electrical impedance imaging hardware system - Google Patents

Abstract

The invention requests to protect a bio-electrical impedance imaging hardware system and relates to medical equipment. The bio-electrical impedance imaging hardware system comprises an upper computer 1, a USB interface chip 2, a D/A converter, a filter and pressure flow switching circuit 3, multiplex switches 4 and 6, a tested object 5, an amplifying, filter and A/D switching circuit 7 and an FPGA controller 8. The core component of the system is the FPGA controller and comprises a constant flow source control module, a multiplex switch selecting control module, an A/D converting sampling control module, a digital phase sensitive detection module, a USB transmission control module and a master control module. The system uses the FPGA technology to realize the functional modules and improves integrated level, expandability and upgradability of the circuit so as to greatly reduce the volume and power consumption of the imaging hardware system, reduce the cost and improve the anti-interference performance.

Description

A bioelectrical impedance imaging hardware system

technical field

The invention relates to a medical device, in particular to a bioelectrical impedance imaging hardware system.

Background technique

Bioelectrical impedance imaging is a new, cheap, and non-destructive imaging technology. Its basic principle is to inject safe electrical physical quantities (such as current or voltage) into the human body, measure the corresponding electrical physical quantities on the body surface, and analyze the distribution of electrical impedance in the target body. A novel imaging method for reconstruction. In bioelectrical impedance imaging, the quality of imaging images is closely related to the number of electrodes, and the larger the number of electrodes, the greater the amount of data information transmitted. The existing bioelectrical impedance imaging system data acquisition and data transmission circuit is basically composed of an analog signal generation circuit, a multi-channel selection integrated circuit, a counter integrated circuit, a single-chip microcomputer main control chip, a serial communication circuit and a filter circuit, etc., and the circuit is relatively complicated. , There are many analog circuit components, resulting in high power consumption, large volume, weak anti-interference ability, high maintenance and upgrade costs, and low data acquisition speed of the bioelectrical impedance imaging system. In view of the above problems, although some researchers have made local improvements to the bioelectrical impedance imaging hardware system, such as the constant current source of the FPGA-based bioelectrical impedance imaging system developed by Professor Wang Huaxiang of Tianjin University, the above problems have not been solved. System solved. The biological electrical impedance imaging hardware system of the present invention improves the integration degree of the circuit, and enhances its scalability and upgradeability, thereby greatly reducing the volume and power consumption of the hardware system, saving costs, and improving the anti-interference performance.

Contents of the invention

The technical problem to be solved by the present invention is, aiming at the defects in the prior art, design a kind of utilizing Field Programmable Gate Array technology (Field Programmable Gate Array, FPGA) and USB communication technology to realize volume is small, power consumption is low, and circuit structure is simple , easy to maintain and upgrade bioelectrical impedance imaging hardware system.

The general technical scheme that the present invention adopts is:

A bioelectrical impedance imaging hardware system includes the following parts:

The upper computer is used to receive the collected voltage data, reconstruct and display the image;

The USB interface chip is used to receive control signals and data from the FPGA controller to complete the USB transmission function;

D/A conversion, filtering and voltage-current conversion circuits, including D/A conversion devices, band-pass filter circuits and Howland circuits, are used to convert the data output by the FPGA controller into a constant current that can be injected into the measured object;

The multi-way switch is used to receive the control signal output by the FPGA controller so as to determine the gated electrodes on the measured object;

Amplification, filtering and A/D conversion circuits, including amplification circuits, band-pass filter circuits and A/D conversion circuits, are used to preprocess the measured voltage signals and perform analog-to-digital conversion on the preprocessed signals, and finally convert The converted data is input to the FPGA controller;

The FPGA controller is used to control the coordinated work of the above-mentioned parts.

The control process of the FPGA controller specifically includes, receiving commands from the host computer by controlling the USB interface chip and transmitting imaging data to the host computer, controlling the multi-way switch to determine the gate electrode, receiving amplification, filtering and A/D conversion circuits The input digital voltage signal is digitally phase-sensitively demodulated, and the D/A conversion, filtering and voltage-current conversion circuits are controlled to output a constant current.

The FPGA controller includes a constant current source control module, a multi-way switch selection control module, an A/D conversion sampling control module, a digital phase-sensitive demodulation module, a USB transmission control module and a total control module, wherein,

The constant current source control module is used to output data that can be converted into a constant current injected into the measured object;

The multi-way switch selection control module is used to control the multi-way switch to select different injection circuit voltage measurement modes;

The A/D conversion sampling control module is used to control the A/D conversion frequency of the amplification, filtering and A/D conversion circuit and receive the data converted by the A/D conversion circuit;

The digital phase-sensitive demodulation module calculates the above-mentioned converted data and FPGA internal sine and cosine tables by means of digital phase-sensitive demodulation, and demodulates digital signals comprising real and imaginary parts;

The USB transmission control module controls the batch transmission mode in which the USB interface chip works, and completes the USB transmission function;

The general control module controls the work of each module, determines the working status of the above modules by distributing control words, and completes the functions of data buffering and transmission between modules.

Each module of the FPGA controller is implemented in the FPGA using hardware description language programming.

The constant current source control module outputs the sine table data in its internal ROM to the D/A conversion, filtering and voltage-current conversion circuits through FPGA.

The function of the multi-way switch selection control module is realized by writing a state machine in FPGA.

The sampling clock generated by the A/D conversion sampling control module is completed by a timer programmed inside the FPGA, and the function of receiving A/D converted data is realized by a dual-port ROM written inside the FPGA.

Described total control module is realized by state machine written by hardware description language Verlog HDL, specifically: total control module is divided into five states, is respectively waiting for command, receiving command, distributing control word, receiving phase-sensitive demodulation data and transmission Phase-sensitive demodulation data, the waiting command state is continuously polling whether the USB transmission control module has data input; the receiving command state is receiving the command data from the USB transmission control module and analyzing the integrity and correctness of these data, That is to judge whether the value of each command control word is within its respective value range; the state of the distribution control word is to transmit each received command control word to the corresponding module respectively; the state of receiving phase-sensitive demodulation data To check whether the work of the digital phase-sensitive demodulation module is completed, if the phase-sensitive demodulation is completed, the incoming data of the digital phase-sensitive demodulation module is received, otherwise wait; the state of the transmitted phase-sensitive demodulation data is the received The phase-sensitive demodulation data is sent to the USB transmission control module.

The bioelectrical impedance imaging hardware system designed with FPGA technology improves the integration of the circuit, and enhances its scalability and upgradeability, thereby greatly reducing the size and power consumption of the hardware system, saving costs, and improving anti-interference performance. It has broad application prospects in information collection and medical electronic instruments.

Description of drawings

Fig. 1 is the overall block diagram of the bioelectrical impedance imaging system;

Fig. 2 is the block diagram of FPGA controller;

Fig. 3 is the principle diagram that utilizes direct digital frequency synthesis technology (DDS) to generate the excitation constant current source;

Figure 4 is a schematic diagram of the digital phase-sensitive demodulation module.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.

The present invention has designed a kind of bioelectrical impedance imaging hardware system based on FPGA technology, and this system comprises following several parts:

Host computer 1, this part is composed of industrial computer or PC, which is used to receive the collected voltage data, and use conventional software algorithms (such as equipotential line back projection) to reconstruct and display images;

USB interface chip 2, this part is composed of USB interface chip, receives the control signal and data of the FPGA controller, and completes the USB transmission function;

D/A conversion, filtering and voltage-current conversion circuit 3, this part is composed of D/A conversion device, band-pass filter circuit and Howland circuit, converts the data output by the FPGA controller into a constant current that can be injected into the measured object 5 ;

Multi-way switches 4 and 6, this part is composed of multi-way switch chips, which receive the control signal output by the FPGA controller to determine which electrode is gated;

There are 7 parts of amplification, filtering and A/D conversion circuit. This part is composed of amplification circuit, band-pass filter circuit and A/D conversion circuit. The measured voltage signal is preprocessed and the A/D conversion device is controlled by the FPGA controller. The preprocessed signal is converted from analog to digital, and finally the converted data is input to the FPGA controller.

FPGA controller part, this part is composed of constant current source control module, multi-way switch selection control module, A/D conversion sampling control module, digital phase-sensitive demodulation module, USB transmission control module, and general control module.

As shown in Figure 2, all modules of the FPGA controller are completed in the FPGA, and the structure and functions of each module are described in detail as follows:

1. Constant current source control module

This module uses direct digital frequency synthesis (DDS) technology, uses Matlab software to generate sine table data, and stores these data in the read-only ROM inside the FPGA chip. Using the phase-locked loop circuit (PLL) inside the FPGA to output a stable clock, this stable clock and the address signal generated by the accumulator will drive the read-only ROM inside the FPGA together, and output the sine table data in the ROM to the D/A conversion , filtering and pressure-current conversion circuit 3, during this process the initial value of the accumulator is determined by the input phase control word, the step size of the accumulator is determined by the input frequency control word, and the phase control word and frequency control word are distributed by the general control module. The digital signal output by this module undergoes D/A conversion, filtering, amplification and isolation, and finally restores to a sinusoidal voltage signal determined by the phase control word and frequency control word. The sinusoidal voltage signal is converted into a current signal through the improved Howland circuit so as to be injected into the measured object 5 . The schematic diagram of the excitation source produced by DDS technology is shown in Figure 3.

2. Multi-way switch selection module

The multi-way switch selection module is implemented by writing a state machine in the FPGA. This module generates A0, A1, A2, and A3 respectively as four-digit binary address signals. Among them, A0 and A1 are used to select the electrodes that load the excitation current, A2, A3 is used to select the electrode for measuring voltage. By receiving different mode control words (MODE), the change mode of A0, A1, A2, and A3 can be selected, so as to generate different voltage measurement modes, such as adjacent injection current adjacent voltage measurement mode , Adjacent current injection relative voltage measurement mode, relative current injection adjacent voltage measurement mode, etc., can realize flexible and changeable measurement. The above different measurement modes can be completed by writing different state machines in hardware description language, so that The realization of custom measurement mode provides a good hardware platform for the development of electrical impedance imaging technology in the later stage.

The address signal generated by this module controls the two parts of multi-way switch 4 and multi-way switch 6, that is, generates A0 and A1 address signals according to the required excitation mode to control the multi-way switch 4 part to load the excitation current to the required 16 excitation electrodes. On a pair of electrodes, A2 and A3 address signals are generated according to the required measurement method to control the multi-way switch. Part 6 loads the voltage on a pair of electrodes among the 16 measuring electrodes to the amplification, filtering and A/D conversion circuit in part 7. input.

The multi-channel switch part in this implementation example adopts the CMOS sixteen-channel analog multi-channel switch MAX306 produced by Maxim (the maximum on-resistance is 100Ω, the maximum resistance matching error between channels is 5Ω, and the switching time is less than 400ns)

3. A/D conversion sampling control module

The A/D conversion sampling control module is implemented by hardware description language programming, completes the output of the sampling clock and the reception of the A/D conversion data and transmits it to the digital phase-sensitive demodulation module. The sampling clock is completed by the timer programmed inside the FPGA. The cycle of the device is determined by the sampling frequency control word distributed by the general control module, and the function of receiving A/D converted data and passing it into the digital phase-sensitive demodulation module is realized by the dual-port ROM written inside the FPGA. This module is used to control the A/D conversion frequency of the 7 parts of the amplification, filtering and A/D conversion circuit and receive the A/D converted data.

4. Digital phase-sensitive demodulation module

The digital phase-sensitive demodulation module is programmed by the hardware description language. In this embodiment, the A/D conversion device is used to sample 250 times in one cycle of the sine wave periodic voltage signal, and 250 data are generated. These data are then stored in two tables in the ROM of the FPGA for calculation, one is a sine table and the other is a cosine table. The general formula for calculating the imaginary component I and the real component Q in one cycle is as follows:

$r\left(\mathrm{no}\right)=\cos \left(\frac{2\mathrm{\π}}{N}\mathrm{no}\right)$ and $q\left(\mathrm{no}\right)=\sin \left(\frac{2\mathrm{\π}}{N}\mathrm{no}\right)$

The schematic diagram implemented in the FPGA is shown in Figure 4. After the FPGA demodulates the I and Q values, the values are sent to the general control module, which then transmits the data to the USB transmission control module, and the USB transmission control module controls the USB The interface chip transmits the phase-sensitive demodulated data to the host computer. The following formula can be used to calculate the amplitude and phase of the voltage signal in the host computer.

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; N</span>}}\sqrt{{\mathrm{<span\; class="notranslate">\; I</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}$

为初始相位。Among them, V(n) is the data sampled by the A/D conversion device, q(n) and r(n) are sine tables and cosine tables respectively. N is a natural number, and N gets 250 in the system of the present embodiment, and Vm is amplitude,

is the initial phase.

5. USB transmission control module

The interface chip to be controlled by the USB transmission control module is EZ-USB FX2 (namely CY7C68013) produced by CYPRESS. This chip integrates the USB communication control engine (SIE) and the improved 8051 core, and can complete three modes of transmission, USB low-speed transmission of 1.5Mbps, full-speed transmission of 12Mbps and high-speed transmission of 480Mbps. The USB transmission control module generates a small amount of control signals (read signal SLRD, write signal SLWD, enable signal SLOE, write full signal FLAGB, port selection signals FADDR0 and FADDR1) and data bus to perform high-speed USB transmission. The USB control signal is issued by the USB transmission control module, which is implemented by writing a state machine in a hardware description language in the FPGA.

The firmware program of the interface chip controlled by the USB transmission control module is programmed under the firmware framework program provided by CPYPRESS, and only needs to modify the initialization functions TD_Init() and TD_POLL(), which is convenient and simple. In this system, the value of the interface chip register is set. The driving frequency of the USB is 48MHz, from the FIFO mode, asynchronously read and write, and the IFCLK pin is not used.

In order to complete the USB communication function, the USB driver of the upper computer directly uses the driver ezusb.sys provided by CYPRESS, and the application program calls its API functions, mainly CreatFile() and DeviceIoControl(). The function of CreatFile() is to obtain the device handle, and the function of DeviceIoControl() is to send a request to the device driver. The main function of the application is to turn on or off the USB device, set the transmission parameters, start or stop the acquisition and transmission, etc.

6. General control module

The total control module is the core part of the entire circuit. It is a powerful processing system, which is realized by writing a state machine in the hardware description language Verlog HDL. The total control module is divided into five states, which are respectively waiting for commands, receiving commands, and distributing control Word, receive phase-sensitive demodulation data, transmit phase-sensitive demodulation data. The waiting command state is to constantly poll whether the USB transmission control module has data input, and the receiving command state is to receive the command data sent by the USB transmission control module and analyze the integrity and correctness of these data (judging whether the value of each command control word is within its within the range of their respective value ranges), the status of the distribution control word is to transmit the received command control words to the corresponding modules respectively. The status of receiving phase-sensitive demodulation data is to check whether the work of the digital phase-sensitive demodulation module is completed. If the phase-sensitive demodulation is completed, it will receive the data from the digital phase-sensitive demodulation module, otherwise wait. The state of transmitting phase-sensitive demodulated data is to send the received phase-sensitive demodulated data to the USB transmission control module, and the USB transmission control module is responsible for transmitting the phase-sensitive demodulated data to the host computer through the USB interface chip. The main function of the general control module is to coordinate and control the work of each module, to enable each module, to receive and distribute control words, to buffer and transmit data, etc.

After the system is powered on, it works as follows:

(1) The FPGA chip in the system enters the user mode after power-on reset and configuration. In the user mode, the USB transmission control module in the FPGA is initialized first, controls the specified transmission endpoint, and checks the empty (empty) signal of the endpoint FIFO. Wait for the command from the host computer.

(2) If a command transmission is detected, the USB transmission control module controls the USB interface chip to perform USB transmission, and transmits the command data to the total control module, which accepts the command and judges whether it is valid. If the command control word is invalid, the total control The module returns to the state of waiting for commands without further action.

(3) If the command is valid, the master control module will transmit the frequency control word, phase control word, mode selector control word, and digital phase-sensitive demodulation sampling rate control word to their respective modules, and each module will follow the working mode determined by the control word Execute a measurement cycle. The measured object 5 is composed of a cylinder model with 16 electrodes (expandable) placed in a circle around it, and substances with different impedance values are arranged in the cylinder, which can be used for the measurement of the bioelectrical impedance imaging hardware system;

An example of the measurement cycle is as follows: If this system uses a method of injecting current into adjacent electrodes and measuring voltage on adjacent electrodes, there are 16 electrodes in total (expandable), first use 1-2 electrodes to inject current, and then measure 3- 4 electrode pairs, 4-5 electrode pairs until 15-16 electrode pairs, a total of 13 pairs of electrode voltage signals, and then change 2-3 electrode pairs to inject current, measure 4-5 electrode pairs, 5-6 electrode pairs until 16- 1 electrode pair, a total of 13 pairs of electrode voltage signals, so a total of 13 (pairs) * 16 (times) a total of 208 voltage signals, these voltage signals are amplified, filtered and A/D conversion circuit 7 parts and then input into A/D D converts the sampling control module, and finally sends the data to the digital phase-sensitive demodulation module to complete a measurement cycle.

(4) The digital phase-sensitive demodulation module demodulates the received data.

(5) The general control module receives the data demodulated by the digital phase-sensitive demodulation module and sends the data to the USB transmission control module, and then the USB transmission control module controls the USB interface chip to transmit the data to the host computer.

(6) After completing one measurement acquisition, repeat steps (2)-(4) for the next acquisition.

(7) In the host computer, the host computer receives the data from the USB interface, and uses the equipotential line back-projection algorithm or one-step Newton method to reconstruct and display the target image.

The hardware description language programming carrier of this invention can be used Altera's Cylone series chips, most of the content of the system can be completed by FGPA integrated circuits, only a small amount of external cooperation with chips, such as A/D, D/A, COMS multi-way switch, USB Interface chips, etc., which can improve the integration of the hardware system, perform proper front-end processing on the measured data, reduce its size, reduce power consumption, save costs, improve maintainability and increase data transmission speed, and can be upgraded Good sex.

The present invention can be summarized by other specific forms that do not deviate from the spirit or main characteristics of the present invention. The above-mentioned embodiments of the present invention can only be considered as illustrations of the present invention and cannot limit the present invention. They are equivalent to the claims of the present invention. Any change within the meaning and scope should be considered to be included in the scope of the claims. Therefore, the present invention is based on the protection scope of the claims.

Claims (8)

1. A bioelectrical impedance imaging hardware system, comprising the following parts: The upper computer (1) is used to receive the collected voltage data, reconstruct and display the image; The USB interface chip (2) is used to receive the control signal and data of the FPGA controller (8) to complete the USB transmission function; D/A conversion, filtering and pressure-current conversion circuit (3), including a D/A conversion device, a band-pass filter circuit and a Howland circuit, for converting the data output by the FPGA controller (8) into data that can be injected into the measured object (5) constant current; A multi-way switch (4, 6) is used to receive the control signal output by the FPGA controller (8) so as to determine the gated electrodes on the measured object (5); Amplification, filtering and A/D conversion circuit (7), including an amplification circuit, a band-pass filter circuit and an A/D conversion circuit, used to preprocess the measured voltage signal and perform analog-to-digital conversion on the preprocessed signal , and finally input the converted data into the FPGA controller; The FPGA controller (8) is used to control the coordinated work of the above-mentioned parts. 2. A kind of bioelectrical impedance imaging hardware system according to claim 1, is characterized in that, described FPGA controller (8) control process specifically comprises, by controlling USB interface chip (2) to receive host computer to transmit Command and transmit the imaging data to the host computer, control the multi-way switch (4, 6) to determine the gate electrode, receive the digital voltage signal input by the amplification, filtering and A/D conversion circuit (7), and perform digital phase-sensitive analysis on the voltage signal adjust, and control the D/A conversion, filtering and voltage-current conversion circuit (3) to output a constant current. 3. A kind of bioelectrical impedance imaging hardware system according to claim 1 or 2, is characterized in that, described FPGA controller (8) comprises constant current source control module, multiplex switch selection control module, A/D conversion sampling control module, digital phase-sensitive demodulation module, USB transmission control module and total control module, wherein, The constant current source control module is used to output data that can be converted into a constant current injected into the measured object (5); The multi-way switch selection control module is used to control the multi-way switches (4, 6) to select different injection circuit voltage measurement modes; The A/D conversion sampling control module is used to control the A/D conversion frequency of the amplification, filtering and A/D conversion circuit (7) and receive the data converted by the A/D conversion circuit; The digital phase-sensitive demodulation module calculates the above-mentioned converted data and FPGA internal sine and cosine tables by means of digital phase-sensitive demodulation, and demodulates digital signals comprising real and imaginary parts; The USB transmission control module controls the batch transmission mode in which the USB interface chip works, and completes the USB transmission function; The general control module controls the work of each module, determines the working status of the above modules by distributing control words, and completes the functions of data buffering and transmission between modules. 4. A kind of bioelectrical impedance imaging hardware system according to any one of claims 1-3, characterized in that, each module of the FPGA controller (8) is implemented in the FPGA using hardware description language programming. 5. A kind of bioelectrical impedance imaging hardware system according to claim 3 or 4, is characterized in that, described constant current source control module outputs the sine table data in its internal ROM to described D by FPGA /A conversion, filtering and pressure-current conversion circuit (3). 6. A bioelectrical impedance imaging hardware system according to any one of claims 3-5, characterized in that the function of the multi-way switch selection control module is realized by programming a state machine in FPGA. 7. according to a kind of bioelectrical impedance imaging hardware system described in one of claim 3-6, it is characterized in that, the sampling clock that described A/D conversion sampling control module produces is finished by the timer that FPGA interior writes, receives The function of the data converted by A/D is realized by the dual-port ROM written inside the FPGA. 8. according to a kind of bioelectrical impedance imaging hardware system described in one of claim 3-7, it is characterized in that, described total control module is realized by hardware description language Verlog HDL writing state machine, is specifically: total control module It is divided into five states, which are respectively waiting for commands, receiving commands, distributing control words, receiving phase-sensitive demodulated data and transmitting phase-sensitive demodulated data. The waiting command state is to continuously poll whether the USB transmission control module has data input; The receiving command state is to receive the command data from the USB transmission control module and analyze these data integrity and correctness, that is, to judge whether the value of each command control word is within its respective value range; the distribution control word state In order to transmit the received command control words to the corresponding modules respectively; the state of receiving phase-sensitive demodulation data is to check whether the work of the digital phase-sensitive demodulation module is completed, and if the phase-sensitive demodulation is completed, the digital phase-sensitive demodulation is received. Demodulate the incoming data from the module, otherwise wait; the state of transmitting phase-sensitive demodulated data is to send the received phase-sensitive demodulated data to the USB transmission control module.

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