CN101794860A - Conducting microchannel memory element and manufacturing method thereof - Google Patents
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- CN101794860A CN101794860A CN200910009980A CN200910009980A CN101794860A CN 101794860 A CN101794860 A CN 101794860A CN 200910009980 A CN200910009980 A CN 200910009980A CN 200910009980 A CN200910009980 A CN 200910009980A CN 101794860 A CN101794860 A CN 101794860A
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 58
- 239000002184 metal Substances 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000007784 solid electrolyte Substances 0.000 claims abstract description 16
- 239000003792 electrolyte Substances 0.000 claims description 38
- 239000000463 material Substances 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 14
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 9
- 150000001786 chalcogen compounds Chemical class 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 7
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 230000002146 bilateral effect Effects 0.000 claims description 6
- 238000003384 imaging method Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- HTRSGQGJZWBDSW-UHFFFAOYSA-N [Ge].[Se] Chemical compound [Ge].[Se] HTRSGQGJZWBDSW-UHFFFAOYSA-N 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims description 4
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- 239000007769 metal material Substances 0.000 claims description 4
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- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 4
- 229940065287 selenium compound Drugs 0.000 claims description 4
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- 239000010937 tungsten Substances 0.000 claims description 4
- 229910001930 tungsten oxide Inorganic materials 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 2
- 229910052946 acanthite Inorganic materials 0.000 claims 2
- OMZSGWSJDCOLKM-UHFFFAOYSA-N copper(II) sulfide Chemical compound [S-2].[Cu+2] OMZSGWSJDCOLKM-UHFFFAOYSA-N 0.000 claims 2
- XUARKZBEFFVFRG-UHFFFAOYSA-N silver sulfide Chemical compound [S-2].[Ag+].[Ag+] XUARKZBEFFVFRG-UHFFFAOYSA-N 0.000 claims 2
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Abstract
一种导通微通道存储器(CBRAM)元件及其制造方法，其中的导通微通道存储器元件包括第一电极层、介电层、固态电解质层、第二电极层以及金属层。上述固态电解质层是位于第一电极层上，第二电极层是位于固态电解质层上，至于金属层是位于固态电解质层旁。而介电层是在固态电解质层与金属层之间。由于导通微通道存储器元件的固态电解质层旁配置有金属层，所以可在擦除过程中使金属层产生正电场，加速打断相互连接的金属细丝。
A conductive microchannel memory (CBRAM) element and a manufacturing method thereof, wherein the conductive microchannel memory element comprises a first electrode layer, a dielectric layer, a solid electrolyte layer, a second electrode layer and a metal layer. The solid electrolyte layer is located on the first electrode layer, the second electrode layer is located on the solid electrolyte layer, and the metal layer is located next to the solid electrolyte layer. The dielectric layer is between the solid electrolyte layer and the metal layer. Since the metal layer is arranged next to the solid electrolyte layer of the conductive microchannel memory element, a positive electric field can be generated in the metal layer during the erasing process to accelerate the breaking of the interconnected metal filaments.
Description
Technical field
The present invention relates to a kind of conductive bridging random access memory (Conductive Bridging Random AccessMemory, CBRAM) element and manufacture method thereof.
Background technology
Conductive bridging random access memory (CBRAM) is a kind of non-volatile memory technologies of utilizing resistance change to carry out data access, belongs to the category of resistance-type memory (RRAM) together.The component structure of conductive bridging random access memory can be considered electrolysis tank, is made up of middle the filling out with solid electrolyte (Solid electrolyte) of metal anode (Ag or Cu) and inert cathode (Ni, W or Pt).The material of this solid electrolyte is the chalcogen compound (Chalcogenide) or the glass oxide of vitreousness.After applying small voltage between two utmost points, anode produces can oxidation reaction, makes to present ionic state behind the metal ejected electron of electrode surface and dissolve in electrolyte.Cause because of electrically moving will move toward cathode direction, separate out the conducting metal atom but carry out reduction reaction at cathode surface at last, and will further form filament (Filament), and the solid electrolyte overall resistance is descended, and finish the action of writing (Write).Otherwise, when wiping (Erase) operation, then voltage reversal is exchanged, but the filament of conducting metal atom formation is disappeared in electrolyte, allow resistance go up to initial state gradually.
For the oxide variable resistor that has the conversion of bistable resistance, its low resistance path-filament is the key of decision resistance conversion, filament is the low resistance path in the CBRAM memory, behind the durability test of element high low resistance conversion through tens thousand of times, quantity and the distribution number of times that may reduce element circulation (Cycling) of filament in solid electrolyte, and the time (Switching time) of height configuration conversion.
Summary of the invention
The present invention proposes a kind of conductive bridging random access memory (CBRAM) element, comprises first electrode layer, dielectric layer, solid-state electrolyte layer, the second electrode lay and metal level.Above-mentioned solid-state electrolyte layer is to be positioned on first electrode layer, and the second electrode lay is to be positioned on the solid-state electrolyte layer, is to be positioned at by the solid-state electrolyte layer as for metal level.And dielectric layer is between solid-state electrolyte layer and metal level.
The present invention proposes a kind of method of making conductive bridging random access memory element in addition, comprises forming dielectric layer earlier on first electrode layer, carries out exposure imaging and etching again, to form at least one first groove in dielectric layer.Subsequently, fill up metal level in groove, carry out exposure imaging and etching again, with formation second groove in the other dielectric layer of first groove, and second groove exposes the part surface of first electrode layer.Then, in second groove, deposit solid-state electrolyte layer, on solid-state electrolyte layer, deposit the second electrode lay again.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 is the generalized section according to a kind of conductive bridging random access memory element of embodiments of the invention.
Fig. 2 is the generalized section according to the another kind of conductive bridging random access memory element of embodiments of the invention.
Fig. 3 is a kind of vertical view of example of the metal level of Fig. 2.
Fig. 4 is the vertical view of another kind of example of the metal level of Fig. 2.
Fig. 5 is the part enlarged drawing of Fig. 1 or Fig. 2.
Fig. 6 A to Fig. 6 F is the manufacturing process generalized section according to a kind of conductive bridging random access memory element of another embodiment of the present invention.
Description of reference numerals
100: conductive bridging random access memory element 102,600: the first electrode layers
110,602: dielectric layer 104,612: solid-state electrolyte layer
106,614: the second electrode lay 108,108a, 108b, 500,608: metal level
112: groove 114: inner surface
400: most advanced and sophisticated 604: the first grooves
606: 610: the second grooves in surface
Embodiment
Fig. 1 is the generalized section according to a kind of conductive bridging random access memory (CBRAM) element of embodiments of the invention.
Please refer to Fig. 1, the conductive bridging random access memory element 100 of present embodiment comprises first electrode layer 102, dielectric layer 110, solid-state electrolyte layer 104, the second electrode lay 106 and metal level 108, wherein the material of first electrode layer 102 is for example inert metal, as platinum (Pt), tungsten (W), titanium nitride (TiN) or nickel.Above-mentioned solid-state electrolyte layer 104 is to be positioned on first electrode layer 102, and the material of described solid-state electrolyte layer 104 comprises chalcogen compound (Chalcogenide), as germanium selenium compound (Ge-Se) or germanium sulphur compound (Ge-S); Or silver sulfide (Ag
2S), copper sulfide (Cu
2S), tantalum oxide (Ta
2O
5), tungsten oxide (W
2O
3) or silica (SiO
2).And the second electrode lay 106 is to be arranged on the solid electrolyte 104, and wherein the material of the second electrode lay 106 comprises silver (Ag) or copper (Cu).As for metal level 108 can be a kind of single-side structural, and it is other to be positioned at solid-state electrolyte layer 104, and wherein the material of metal level 108 is conductive metallic composite or metal material.Moreover the metal level 108 and first electrode layer 102 are electrical connected in Fig. 1.110 of dielectric layers are arranged between solid electrolyte 104 and the metal level 108, wherein the material of dielectric layer 110 silica (SiO for example
2), silicon nitride (SiN) or polymethyl methacrylate (Polymethylmethacrylate, PMMA).
In Fig. 1, dielectric layer 110 can have groove 112, and makes solid-state electrolyte layer 104 be positioned at groove 112.
The conductive bridging random access memory element 100 of Fig. 1 is in wiping (erase) process, owing to apply positive voltage at first electrode layer 102, connected metal level 108 can produce positive electric field, repel the metal ion that is scattered in the solid-state electrolyte layer 104, make that interconnective filament (Filament) is easily interrupted, promote element and change the efficient of paramount configuration by hanging down configuration, expection can improve the endurance (Endurance) of element and reduce switching time (Switching time).In addition, metal level 108 is also by external circuit, so that produce positive electric field in the erase process of conductive bridging random access memory element 100.
Fig. 2 is the generalized section according to the another kind of conductive bridging random access memory element of embodiments of the invention, wherein uses with Fig. 1 components identical symbol and represents same or analogous member.
Please refer to Fig. 2, conductive bridging random access memory element 200 wherein is that with the difference of Fig. 1 metal level 108 is bilateral structures, and solid-state electrolyte layer 104 then covers its inner surface with groove 112 profiles.Can be as for the second electrode lay 106 according to the form of solid-state electrolyte layer 104, the part position is in groove 112.
Fig. 3 and Fig. 4 are the vertical views of two kinds of examples of the metal level 108 of Fig. 2.Metal level 108a in Fig. 3 is the block structure of square type, and the metal level 108b among Fig. 4 is slightly crooked ear shape structure.
In addition, the metal level 108 of Fig. 1 or Fig. 2 also can have other distortion, as shown in Figure 5.Fig. 5 is the part enlarged drawing of Fig. 1 or Fig. 2, and metal level 108 wherein also comprises a tip (tip) 500, towards solid-state electrolyte layer 104 configurations, in order to add the highfield effect.
Fig. 6 A to Fig. 6 F is the manufacturing process generalized section according to a kind of conductive bridging random access memory element of another embodiment of the present invention.
Please refer to Fig. 6 A, on first electrode layer 600, form dielectric layer 602 earlier.The material of aforementioned first electrode layer 600 is for example inert metal, as platinum (Pt), tungsten (W), titanium nitride (TiN) or nickel.The material of aforementioned dielectric layer 602 is silica (SiO for example
2), silicon nitride (SiN) or polymethyl methacrylate (PMMA).
Subsequently, please refer to Fig. 6 B, carry out exposure imaging and etching, to form first groove 604 in dielectric layer 602, it exposes the surface 606 of first electrode layer 600.Form etching mode that above-mentioned groove 604 adopted for example dry-etching or Wet-type etching.And, still the invention is not restricted to this though show two first grooves 604 in the present embodiment, can also be single or plural structure.
Then, please refer to Fig. 6 C, in first groove 604, fill up the metal level 608 that can produce extra electric field, its step for example is prior to depositing metal layers 608 on the dielectric layer 602 and on the surface 606 of first electrode layer 600, utilizes chemico-mechanical polishing (CMP) mode to remove the metal level 608 on dielectric layer 602 surfaces again.Above-mentioned metal level 608 is conductive metallic composite or metal material.
Then, please refer to Fig. 6 D, carry out exposure imaging and etching, with formation second groove 610 in the dielectric layer 602 on first groove, 604 sides, and second groove 610 exposes the surface 606 of first electrode layer 600.In the present embodiment, the size of second groove 610 is greater than the size of first groove 604.In addition, the metal level 608 of present embodiment is a bilateral structure, so groove 610 can be formed between the bilateral structure.
In addition, the width w of the dielectric layer 602 between second groove 610 and first groove 604 is healed better little, can make the metal level 608 in first groove 604 produce significant electric field effect.And form etching mode that above-mentioned second groove 610 adopted for example dry-etching or Wet-type etching.
Come again, please refer to Fig. 6 E, on the dielectric layer 602, conformally deposit solid-state electrolyte layer 612 on the surface 606 of the inwall of second groove 610 and first electrode layer 600, its material such as chalcogen compound (Chalcogenide) are as germanium selenium compound (Ge-Se) or germanium sulphur compound (Ge-S); Or silver sulfide (Ag
2S), copper sulfide (Cu
2S), tantalum oxide (Ta
2O
5), tungsten oxide (W
2O
3) or silica (SiO
2) etc.Afterwards, deposition the second electrode lay 614 on solid-state electrolyte layer 612, its material is silver (Ag) or copper (Cu) etc. for example.
Then, please refer to Fig. 6 F, can remove second groove 610 solid-state electrolyte layer 612 and the second electrode lay 614 in addition, but, still can on the dielectric layer 602 beyond second groove 610, leave partly solid-state electrolyte layer 612 and the second electrode lay 614 as long as solid-state electrolyte layer 612 can not contact with metal level 608.And remove mode such as the dry-etching or the Wet-type etching of above-mentioned solid-state electrolyte layer 612 and the second electrode lay 614.
In sum, the present invention adds the metal level that affiliation produces extra electric field in original conductive bridging random access memory element, so when can be in erase process first electrode layer being applied positive voltage, make the metal level that is connected with first electrode layer produce positive electric field, repel the metal ion that is scattered in the solid-state electrolyte layer, to quicken to interrupt interconnective filament (Filament), promote element and change the efficient of paramount configuration, and then improve the endurance of element and reduce switching time by low configuration.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; those of ordinary skill in the technical field under any; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when looking being as the criterion that accompanying Claim defines.
Claims (30)
1. conductive bridging random access memory element, it is characterized in that: this conductive bridging random access memory element comprises:
First electrode layer;
Solid-state electrolyte layer is arranged on this first electrode layer;
The second electrode lay is arranged on this solid electrolyte;
Metal level is arranged at by this solid electrolyte; And
Dielectric layer is arranged between this solid electrolyte and this metal level.
2. conductive bridging random access memory element as claimed in claim 1 is characterized in that: this dielectric layer has groove.
3. conductive bridging random access memory element as claimed in claim 2 is characterized in that: this solid-state electrolyte layer is positioned at this groove.
4. conductive bridging random access memory element as claimed in claim 2 is characterized in that: this solid-state electrolyte layer covers the inner surface of this groove.
5. conductive bridging random access memory element as claimed in claim 1 is characterized in that: this metal level and this first electrode layer are electrical connected.
6. conductive bridging random access memory element as claimed in claim 1 is characterized in that: this metal level also comprises at least one tip, towards this solid-state electrolyte layer configuration.
7. conductive bridging random access memory element as claimed in claim 1 is characterized in that: this metal level is a single-side structural.
8. conductive bridging random access memory element as claimed in claim 1 is characterized in that: this metal level is a bilateral structure.
9. conductive bridging random access memory element as claimed in claim 1 is characterized in that: the material of this metal level is conductive metallic composite or metal material.
10. conductive bridging random access memory element as claimed in claim 1 is characterized in that: the material of this first electrode layer comprises inert metal.
11. conductive bridging random access memory element as claimed in claim 10 is characterized in that: this inert metal comprises platinum, tungsten, titanium nitride or nickel.
12. conductive bridging random access memory element as claimed in claim 1 is characterized in that: the material of this dielectric layer comprises silica, silicon nitride or polymethyl methacrylate.
13. conductive bridging random access memory element as claimed in claim 1 is characterized in that: the material of this solid-state electrolyte layer comprises chalcogen compound or silver sulfide, copper sulfide, tantalum oxide, tungsten oxide or silica.
14. conductive bridging random access memory element as claimed in claim 13 is characterized in that: this chalcogen compound comprises germanium selenium compound or germanium sulphur compound.
15. conductive bridging random access memory element as claimed in claim 1 is characterized in that: the material of this second electrode lay comprises silver or copper.
16. a method of making conductive bridging random access memory element is characterized in that: this method comprises:
On first electrode layer, form dielectric layer;
Carry out exposure imaging and etching, in this dielectric layer, to form at least one first groove;
In this first groove, fill up metal level;
Carry out exposure imaging and etching, to form second groove in this other dielectric layer of this first groove, this second groove exposes the part surface of this first electrode layer;
In this second groove, deposit solid-state electrolyte layer; And
On this solid-state electrolyte layer, deposit the second electrode lay.
17. the method for manufacturing conductive bridging random access memory element as claimed in claim 16 is characterized in that: the step that forms this first groove comprises: make this first groove expose the surface of this first electrode layer.
18. the method for manufacturing conductive bridging random access memory element as claimed in claim 17 is characterized in that: the step that deposits this solid-state electrolyte layer is included on this dielectric layer, conformally deposit this solid-state electrolyte layer on this surface of the inwall of this second groove and this first electrode layer.
19. the method for manufacturing conductive bridging random access memory element as claimed in claim 16 is characterized in that: form the etching mode that this first groove and this second groove adopted and comprise dry-etching or Wet-type etching.
20. the method for manufacturing conductive bridging random access memory element as claimed in claim 16 is characterized in that: also comprise this second groove of removal this solid-state electrolyte layer and this second electrode lay in addition after depositing this second electrode lay.
21. the method for manufacturing conductive bridging random access memory element as claimed in claim 20 is characterized in that: remove this solid-state electrolyte layer beyond this second groove and the mode of this second electrode lay and comprise dry-etching or Wet-type etching.
22. the method for manufacturing conductive bridging random access memory element as claimed in claim 16 is characterized in that: the step of filling up this metal level in this first groove comprises:
Depositing this metal level on this dielectric layer and on this surface of this first electrode layer; And
Remove this metal level on this dielectric layer surface in the chemico-mechanical polishing mode.
23. the method for manufacturing conductive bridging random access memory element as claimed in claim 16 is characterized in that: when this metal level is bilateral structure, form this second groove in this dielectric layer between this bilateral structure.
24. the method for manufacturing conductive bridging random access memory element as claimed in claim 16 is characterized in that: this metal level is conductive metallic composite or metal material.
25. the method for manufacturing conductive bridging random access memory element as claimed in claim 16 is characterized in that: the material of this first electrode layer comprises inert metal.
26. the method for manufacturing conductive bridging random access memory element as claimed in claim 25 is characterized in that: this inert metal comprises platinum, tungsten, titanium nitride or nickel.
27. the method for manufacturing conductive bridging random access memory element as claimed in claim 16 is characterized in that: the material of this dielectric layer comprises silica, silicon nitride or polymethyl methacrylate.
28. the method for manufacturing conductive bridging random access memory element as claimed in claim 16 is characterized in that: the material of this solid-state electrolyte layer comprises chalcogen compound or silver sulfide, copper sulfide, tantalum oxide, tungsten oxide or silica.
29. the method for manufacturing conductive bridging random access memory element as claimed in claim 28 is characterized in that: this chalcogen compound comprises germanium selenium compound or germanium sulphur compound.
30. the method for manufacturing conductive bridging random access memory element as claimed in claim 16 is characterized in that: the material of this second electrode lay comprises silver or copper.
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| CN 200910009980 CN101794860B (en) | 2009-02-04 | 2009-02-04 | Conducting microchannel memory element and method of manufacturing the same |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105027309A (en) * | 2013-03-13 | 2015-11-04 | 密克罗奇普技术公司 | Sidewall-type memory cell |
| CN106415870A (en) * | 2014-02-19 | 2017-02-15 | 密克罗奇普技术公司 | Resistive memory cell having reduced conductive path area |
| CN106684242A (en) * | 2015-11-05 | 2017-05-17 | 华邦电子股份有限公司 | Conductive bridge type random access memory |
| US9865813B2 (en) | 2014-02-19 | 2018-01-09 | Microchip Technology Incorporated | Method for forming resistive memory cell having a spacer region under an electrolyte region and a top electrode |
| US9865814B2 (en) | 2014-02-19 | 2018-01-09 | Microchip Technology Incorporated | Resistive memory cell having a single bottom electrode and two top electrodes |
| US10003021B2 (en) | 2014-02-19 | 2018-06-19 | Microchip Technology Incorporated | Resistive memory cell with sloped bottom electrode |
| CN111936862A (en) * | 2019-03-11 | 2020-11-13 | 京东方科技集团股份有限公司 | Micro-channel and preparation method and operation method thereof |
Family Cites Families (1)
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| CN100334735C (en) * | 2002-04-30 | 2007-08-29 | 独立行政法人科学技术振兴机构 | Solid electrolyte switching device, FPGA using same, memory device, and method for manufacturing solid electrolyte switching device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105027309A (en) * | 2013-03-13 | 2015-11-04 | 密克罗奇普技术公司 | Sidewall-type memory cell |
| CN105027309B (en) * | 2013-03-13 | 2018-03-02 | 密克罗奇普技术公司 | Lateral wall type memory cell |
| US10056545B2 (en) | 2013-03-13 | 2018-08-21 | Microchip Technology Incorporated | Sidewall-type memory cell |
| CN106415870A (en) * | 2014-02-19 | 2017-02-15 | 密克罗奇普技术公司 | Resistive memory cell having reduced conductive path area |
| US9865813B2 (en) | 2014-02-19 | 2018-01-09 | Microchip Technology Incorporated | Method for forming resistive memory cell having a spacer region under an electrolyte region and a top electrode |
| US9865814B2 (en) | 2014-02-19 | 2018-01-09 | Microchip Technology Incorporated | Resistive memory cell having a single bottom electrode and two top electrodes |
| US9917251B2 (en) | 2014-02-19 | 2018-03-13 | Microchip Technology Incorporated | Resistive memory cell having a reduced conductive path area |
| US10003021B2 (en) | 2014-02-19 | 2018-06-19 | Microchip Technology Incorporated | Resistive memory cell with sloped bottom electrode |
| CN106684242A (en) * | 2015-11-05 | 2017-05-17 | 华邦电子股份有限公司 | Conductive bridge type random access memory |
| CN106684242B (en) * | 2015-11-05 | 2019-03-01 | 华邦电子股份有限公司 | Conductive bridge type random access memory |
| CN111936862A (en) * | 2019-03-11 | 2020-11-13 | 京东方科技集团股份有限公司 | Micro-channel and preparation method and operation method thereof |
| CN111936862B (en) * | 2019-03-11 | 2024-06-11 | 京东方科技集团股份有限公司 | Micro-channel, preparation method and operation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101794860B (en) | 2013-07-10 |
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