CN103515530B - Resistive memory and manufacturing method thereof - Google Patents

Abstract

The invention relates to a resistive memory and a manufacturing method thereof. The resistive memory comprises a first electrode, a second electrode, a variable resistance material layer, a first dielectric layer and a second dielectric layer. The first electrode has a first portion and a second portion. The second electrode is disposed opposite to the first electrode. The variable resistance material layer is provided with a side wall, a first surface and a second surface which are opposite, wherein the first surface of the variable resistance material layer is connected with the first part of the first electrode; the second surface of the variable resistance material layer is electrically connected with the second electrode, and the second part surrounds the side wall of the variable resistance material layer and is connected with the first part. The first dielectric layer is configured between the first electrode and the second electrode. The second dielectric layer is configured between the variable resistance material layer and the second part of the first electrode.

Description

Resistive memory and manufacturing method thereof

technical field

The present invention relates to a semiconductor device and its manufacturing method, and in particular to a resistive memory and its manufacturing method.

Background technique

In recent years, resistive memory has become a new type of memory with the most development potential because of its advantages such as low operating voltage, fast operation speed, simple structure, and good durability. Generally speaking, the operation modes of the resistive memory to switch its storage state include unipolar switching and bipolar switching. Wherein, the operation mode of unipolar switching uses voltage pulses of the same polarity (for example, positive voltage pulses or negative voltage pulses) to perform programming and erasing operations of memory cells. In addition, the operation mode of the bipolar switching uses voltage pulses of different polarities to respectively perform the programming operation and the erasing operation of the memory cells.

In addition, for the existing resistive memory, when the operating current passes through the electrodes, heat energy will be generated due to the resistance characteristics of the electrodes, and the heat energy can change the resistance state of the variable resistance material layer in the memory cell, and then switch the storage state of the memory cell. However, since the operating current heats the entire electrode, and the variable resistance material layer is only in contact with a part of the electrode, when the heat energy generated is sufficient to change the resistance state of the variable resistance material layer, the electrode is not connected to the variable resistance material layer. The thermal energy generated at the contacted area will not be used and will be wasted. In addition, if the operating current is reduced in order to avoid energy consumption, the operating efficiency of the device may be reduced.

Contents of the invention

The present invention provides a resistive memory whose electrodes have a small thickness above a layer of variable resistance material.

The invention provides a method for manufacturing a resistive memory, which is used for manufacturing the resistive memory provided by the invention.

The present invention provides a resistive memory, which includes a first electrode, a second electrode, a variable resistance material layer, a first dielectric layer and a second dielectric layer. The first electrode has a first part and a second part. The second electrode is arranged relative to the first electrode. The variable resistance material layer has sidewalls and opposite first and second surfaces, wherein the first surface of the variable resistance material layer is connected to the first part of the first electrode; the second surface of the variable resistance material layer is connected to the second The electrodes are electrically connected, and the second part surrounds the sidewall of the variable resistance material layer and is connected with the first part. The first dielectric layer is disposed between the first electrode and the second electrode. The second dielectric layer is disposed between the variable resistance material layer and the second portion of the first electrode.

In an embodiment of the present invention, the material of the first part is different from the material of the second part, and the resistance of the material of the first part is higher than that of the material of the second part. The material of the first part includes titanium nitride (TiN), tantalum nitride (TaN) or polysilicon, and the material of the second part includes tungsten, copper, aluminum, aluminum-copper alloy or aluminum-silicon-copper alloy.

In an embodiment of the present invention, the material of the first part is the same as that of the second part, and the material of the first electrode includes titanium nitride, tantalum nitride, tungsten, copper, aluminum, aluminum-copper alloy or aluminum-copper alloy. Silicon-copper alloy.

In an embodiment of the present invention, the above-mentioned resistive memory further includes a conductor layer, and the conductor layer is connected to the variable resistance material layer and the second electrode.

In an embodiment of the present invention, the material of the variable resistance material layer includes chalcogenide or transition metal oxide.

In an embodiment of the present invention, the above-mentioned second electrode has a third part and a fourth part, and the second surface of the variable resistance material layer is connected to the third part of the second electrode, and the fourth part surrounds the variable resistance material layer. The side wall of the resistive material layer is connected with the third part.

In an embodiment of the present invention, the above-mentioned second dielectric layer is disposed between the variable resistance material layer and the second portion of the first electrode, and disposed between the variable resistance material layer and the fourth portion of the second electrode between.

In an embodiment of the present invention, the material of the third part of the second electrode is different from the material of the fourth part, and the resistance of the material of the third part is higher than that of the material of the fourth part. The material of the third part includes titanium nitride, tantalum nitride or polysilicon, and the material of the fourth part includes tungsten, copper, aluminum, aluminum-copper alloy or aluminum-silicon-copper alloy.

In an embodiment of the present invention, the material of the third part of the second electrode is the same as that of the fourth part, and the material of the second electrode includes titanium nitride, tantalum nitride, tungsten, copper, aluminum, aluminum- Copper alloy or aluminum-silicon-copper alloy.

The present invention further provides a resistive memory, which includes a first electrode, a second electrode, a memory element and a dielectric layer. The first electrode has a first thickness and a second thickness, and the first thickness is greater than the second thickness. The second electrode is arranged relative to the first electrode. The storage element has a first surface and a second surface, and the storage element is located between the first electrode and the second electrode with a second thickness. A dielectric layer surrounds the storage element, wherein the dielectric layer is coplanar with the first surface of the storage element, and contacts the first electrode having a second thickness with the first surface of the storage element.

In another embodiment of the present invention, the material of the first electrode includes titanium nitride, tantalum nitride, tungsten, copper, aluminum, aluminum-copper alloy or aluminum-silicon-copper alloy.

In another embodiment of the present invention, the above-mentioned resistive memory further includes a conductor layer, and the conductor layer is connected to the memory element and the second electrode.

In another embodiment of the present invention, the material of the above storage element includes chalcogen compound or transition metal oxide.

In another embodiment of the present invention, the above-mentioned second electrode has a third thickness and a fourth thickness, the third thickness is greater than the fourth thickness, and the storage element is located between the first electrode with the second thickness and the first electrode with the fourth thickness. Between the two electrodes, the dielectric layer and the second surface of the storage element are coplanar, and the dielectric layer and the second surface of the storage element are in contact with the second electrode having a fourth thickness.

In another embodiment of the present invention, the material of the second electrode includes titanium nitride, tantalum nitride, tungsten, copper, aluminum, aluminum-copper alloy or aluminum-silicon-copper alloy.

The present invention further provides a method for manufacturing a resistive memory, which includes forming a first electrode, and the first electrode includes a first part and a second part. A second electrode opposite to the first electrode is formed. A first dielectric layer is formed between the first electrode and the second electrode. Forming a second dielectric layer and a variable resistance material layer in the first dielectric layer, wherein the variable resistance material layer has sidewalls and opposite first and second surfaces, and the second dielectric layer surrounds the variable resistance material The side wall of the layer, the first part of the first electrode is connected to the first surface of the variable resistance material layer, the second electrode is electrically connected to the second surface of the variable resistance material layer, and the second part surrounds the side wall of the variable resistance material layer And connected with the first part, and the second dielectric layer is located between the second part of the first electrode and the variable resistance material layer.

In yet another embodiment of the present invention, the manufacturing method of the resistive memory includes the following steps. Form the second electrode. A first dielectric layer is formed on the second electrode. An opening is formed in the first dielectric layer, the opening exposing a portion of the second electrode. A second dielectric layer is formed on sidewalls of the openings. The variable resistance material layer is filled in the opening. A part of the first dielectric layer is removed to expose a part of the second dielectric layer, and a first electrode is formed on the first dielectric layer and the variable resistance material layer.

In yet another embodiment of the present invention, after forming the second dielectric layer and before filling the variable resistance material layer, filling the opening with a conductor layer is further included.

In yet another embodiment of the present invention, the first portion of the first electrode is a relatively high-resistance layer, and the second portion of the first electrode is a relatively low-resistance layer.

In yet another embodiment of the present invention, the method for forming the first electrode on the first dielectric layer and the variable resistance material layer includes the following steps. A relatively low resistance material layer is formed on the first dielectric layer and the variable resistance material layer. A planarization process is performed to remove part of the relatively low resistance material layer to expose the first surface of the second dielectric layer and the variable resistance material layer. forming a relatively high resistance material layer on the relatively low resistance material layer and the variable resistance material layer, and patterning the relatively low resistance material layer and the relatively high resistance material layer to form a first electrode.

In yet another embodiment of the present invention, the manufacturing method of the resistive memory includes the following steps. A first electrode material layer is formed. A first dielectric layer is formed on the first electrode material layer. removing part of the first dielectric layer and part of the first electrode material layer to form an opening and a first electrode, wherein the first electrode material layer around the opening is a second part, and the first electrode located under the second part The material layer is the first part. A second dielectric layer is formed on sidewalls of the openings. The variable resistance material layer is filled in the opening, and the second electrode is formed on the first dielectric layer and the variable resistance material layer.

In yet another embodiment of the present invention, after filling the variable resistance material layer and before forming the second electrode, filling the opening with a conductor layer is further included.

In yet another embodiment of the present invention, the first portion of the first electrode is a relatively high-resistance layer, and the second portion of the first electrode is a relatively low-resistance layer.

In yet another embodiment of the present invention, the method for forming the opening and the first electrode includes the following steps. A layer of relatively high resistance material is formed. A relatively low resistance material layer is formed on the relatively high resistance material layer. The layer of relatively low resistance material and the layer of relatively high resistance material are patterned. A first dielectric layer is formed on the relatively low resistance material layer, and part of the first dielectric layer and part of the relatively low resistance material layer are removed.

In yet another embodiment of the present invention, before forming the second electrode on the first dielectric layer and the variable resistance material layer, further comprising removing part of the first dielectric layer to expose part of the second dielectric layer, Wherein the second electrode includes a third part and a fourth part, the third part of the second electrode is connected to the second surface of the variable resistance material layer, and the fourth part surrounds the sidewall of the variable resistance material layer and is connected to the third part, And the second dielectric layer is located between the fourth part of the second electrode and the variable resistance material layer.

In yet another embodiment of the present invention, the third portion of the second electrode is a relatively high-resistance layer, and the fourth portion of the second electrode is a relatively low-resistance layer.

In yet another embodiment of the present invention, the method for forming the second electrode on the first dielectric layer and the variable resistance material layer includes the following steps. A relatively low resistance material layer is formed on the first dielectric layer and the variable resistance material layer. A planarization process is performed to remove part of the relatively low resistance material layer to expose the second surface of the second dielectric layer and the variable resistance material layer. forming a relatively high resistance material layer on the relatively low resistance material layer and the variable resistance material layer, and patterning the relatively low resistance material layer and the relatively high resistance material layer to form a second electrode.

Based on the above, in the resistive memory of the present invention, the part of the electrode located on the variable resistance material layer has a smaller thickness than other parts of the electrode, so the part of the electrode located on the variable resistance material layer can have higher resistance. In this way, when the operating current flows through the electrodes, a better heating effect can be generated on the variable resistance material layer, thereby effectively changing the resistance state of the variable resistance material layer, and avoiding energy waste and improving the performance of the element. operating efficiency.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a three-dimensional structure of a resistive memory.

2A to 2D are flowcharts of manufacturing the resistive memory according to the first embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of a resistive memory according to a second embodiment of the present invention.

4A to 4C are flowcharts of manufacturing the resistive memory according to the third embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of a resistive memory according to a fourth embodiment of the present invention.

6 and 7A to 7B are flowcharts of manufacturing the resistive memory according to the fifth embodiment of the present invention.

8A and 8B are schematic views of the operation of the resistive memory according to the first embodiment of the present invention, wherein FIG. 8B is a cross-sectional view along line C-C of FIG. 8A .

9A and 9B are schematic views of another operation of the resistive memory according to the first embodiment of the present invention, wherein FIG. 8B is a cross-sectional view along line C-C of FIG. 8A .

Description of main component symbols

100: Dielectric substrate

102, 114, 201, 202, 214, 714: electrodes

104, 108: dielectric layer

106: opening

110: conductor layer

112: variable resistance material layer

114a, 202a: Part I

114b, 202b: Part II

714a: Part III

714b: Part IV

D ₁ , D ₂ , D ₃ , D ₄ : Thickness

I ₁ , I ₂ : Current

Detailed ways

For a more complete understanding of embodiments of the present invention, please refer to the accompanying drawings below. However, this invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

FIG. 1 is a schematic diagram of a three-dimensional structure of a resistive memory. Referring to FIG. 1 , the resistive memory 10 includes a strip-shaped electrode 12 , a strip-shaped electrode 14 , a conductor layer 16 and a variable resistance material layer (not shown). In this embodiment, the extension direction of the electrode 12 intersects the extension direction of the electrode 14, the electrode 12 can be regarded as the upper electrode, the electrode 14 can be regarded as the lower electrode, and the conductor layer 16 is used to connect the variable resistance material layer and the electrode. 12 or electrode 14.

The structure of the resistive memory proposed by the present invention is presented as the structure shown in Figure 1, wherein the section obtained along the A-A line in Figure 1 is the A section, and the section obtained along the B-B line in Figure 1 is B profile. Hereinafter, the manufacturing method of the resistive memory of the present invention will be described in detail with A cross-section and/or B cross-section.

2A to 2D are flow charts of manufacturing the resistive memory according to the first embodiment of the present invention, which are cross-sectional views along the A section.

First, please refer to FIG. 2A , a strip-shaped electrode 102 is formed on a dielectric substrate 100 . The dielectric substrate 100 is, for example, a dielectric layer formed on a silicon substrate. The material of the electrode 102 is, for example, titanium nitride, tantalum nitride, tungsten, copper, aluminum, aluminum-copper alloy or aluminum-silicon-copper alloy. The formation method of the electrode 102 is, for example, first forming a conductive material layer on the dielectric substrate 100, and then patterning the conductive material layer. Then, a dielectric layer 104 is formed on the electrode 102 . The material of the dielectric layer 104 is, for example, silicon oxide. The dielectric layer 104 is formed by, for example, performing a chemical vapor deposition process. Next, an opening 106 is formed in the dielectric layer 104 , wherein the opening 106 exposes a portion of the electrode 102 . The opening 106 is formed by, for example, performing an anisotropic etching process. In this embodiment, the electrode 102 is the second electrode and serves as the lower electrode of the resistive memory.

Next, referring to FIG. 2B , a sidewall dielectric layer 108 is formed on the sidewall of the opening 106 . The material of the sidewall dielectric layer 108 is, for example, silicon nitride. The formation method of the sidewall dielectric layer 108 is, for example, to conformally form a dielectric material layer on the dielectric substrate 100 first, and then perform an anisotropic etching process on the dielectric material layer to remove the dielectric layer 104 and A dielectric material layer is located on the portion of the electrode 102 exposed by the opening 106 to form a sidewall dielectric layer 108 . Then, a conductive material is filled into part of the opening 106 to form the conductive layer 110 . Conductor materials are, for example, titanium nitride, tantalum nitride, tungsten, copper, aluminum, aluminum-copper alloys or aluminum-silicon-copper alloys. Next, the variable resistance material is filled into the opening 106 to form the variable resistance material layer 112 (ie, the memory element). The variable resistance material is, for example, a chalcogen compound or a transition metal oxide. Chalcogenides are, for example, germanium-antimony-tin alloy (GeSbTe), silver-indium-antimonium-zinc alloy (AgInSbTe), aluminum-arsenic-zinc alloy (AlAsTe), or the like. Transition metal oxides are, for example, tungsten oxide (WO _x ), hafnium oxide (HfO _x ), tantalum oxide (TaO _x ), titanium oxide (TiO _x ), copper oxide (CuO _x ), nickel oxide (NiO _x ), zinc oxide (ZnO _x ) or the like. In this embodiment, when the material of the conductive layer 110 is the same as that of the electrode 102 , the conductive layer 110 can be regarded as a protruding portion of the electrode 102 . However, the present invention is not limited thereto. In other embodiments, according to actual application requirements, the electrode 102 may not have the conductor layer 110, but the variable resistance material layer 112 is formed in the entire opening 106 and connected to the part of the electrode 102 exposed by the opening 106. .

In this embodiment, the etching rate of the sidewall dielectric layer 108 is lower than the etching rate of the dielectric layer 104, so as to protect the variable resistance material layer 112 and the conductive layer 110 in the subsequent etching process (described below). layer, avoiding the problem of short circuit caused by the exposure of the variable resistance material layer 112 and the conductor layer 110 . In other embodiments, if the above-mentioned short circuit problem can be avoided, the sidewall dielectric layer 108 does not need to be formed in the opening 106 .

Referring to FIG. 2C , a portion of the dielectric layer 104 is removed to expose a portion of the sidewall dielectric layer 108 . A method for removing part of the dielectric layer 104 is, for example, performing an anisotropic etching process.

Referring to FIG. 2D , strip-shaped electrodes 114 are formed on the dielectric layer 104 and the variable resistance material layer 112 to complete the fabrication of the resistive memory in this embodiment. The material of the electrode 114 is, for example, titanium nitride, tantalum nitride, tungsten, copper, aluminum, aluminum-copper alloy or aluminum-silicon-copper alloy. The formation method of the electrode 114 is, for example, to form a conductive material layer first, and then pattern the conductive material layer. The electrode 114 includes a first portion 114a and a second portion 114b, wherein the second portion 114b surrounds the variable resistance material layer 112 and is separated from the variable resistance material layer 112 by the sidewall dielectric layer 108, and the first portion 114a is located on the second The portion 114b is on the variable resistance material layer 112 , and the first portion 114a is connected to the variable resistance material layer 112 . In this embodiment, the electrode 114 is the first electrode and serves as the upper electrode of the resistive memory.

In addition, the thickness D ₁ of the electrode 114 (including the first portion 114 a and the second portion 114 b ) on the dielectric layer 104 is greater than the thickness D ₂ of the electrode 114 (the first portion 114 a ) on the variable resistance material layer 112 . Therefore, when operating the resistive memory of this embodiment, the cross-sectional area of the electrode 114 on the dielectric layer 104 in the vertical current direction is larger than the cross-sectional area of the electrode 114 on the variable resistance material layer 112 in the vertical current direction, so that The electrode 114 on the variable resistance material layer 112 has a higher current density. Therefore, when operating the resistive memory of the present invention, when the operating current flows through the electrode 114 on the variable resistance material layer 112, the electrode 114 on the variable resistance material layer 112 can have a better heating effect, and then The resistance state of the variable resistance material layer 112 can be effectively changed, and thus the operating efficiency of the resistive memory is improved.

In addition, in this embodiment, the materials of the first portion 114 a and the second portion 114 b of the electrode 114 are the same, which means that the electrode 114 has a single-layer structure. However, the present invention is not limited thereto.

FIG. 3 is a schematic cross-sectional view of a resistive memory according to a second embodiment of the present invention, which is a cross-sectional view along the A section. In this embodiment, the same elements as in FIG. 2D will be denoted by the same reference numerals. Referring to FIG. 3 , the materials of the first portion 114 a and the second portion 114 b of the electrode 114 are different. That is to say, the electrode 114 has a double-layer structure, wherein the resistance of the material of the first part 114a is higher than that of the material of the second part 114b, which means that the first part 114a is a relatively high resistance layer, while the second part 114b is a relatively low resistance layer. layer. The material of the relatively high resistance layer is, for example, titanium nitride, tantalum nitride or polysilicon, and the material of the relatively low resistance layer is, for example, tungsten, copper, aluminum, aluminum-copper alloy or aluminum-silicon-copper alloy. In this embodiment, the forming method of the electrode 114 includes the following steps: first forming a relatively low resistance material layer on the dielectric layer 104 , and the relatively low resistance material layer covers the variable resistance material layer 112 . Next, a planarization process is performed to remove part of the relatively low resistance material layer to expose the variable resistance material layer 112 . Then, a relatively high resistance material layer is formed on the relatively low resistance material layer and the variable resistance material layer 112 . Afterwards, the relatively low-resistance material layer and the relatively high-resistance material layer are patterned to form the electrode 114 having a double-layer structure.

When operating the above-mentioned resistive memory with a double-layer structure, when the operating current flows into the electrode 114 and before flowing through the variable resistance material layer 112, the operating current mainly flows into the relatively low resistance layer (second portion 114b). Due to the low resistance of the relatively low resistance layer, excessive heat energy is not generated at this time. When the operating current wants to flow through the variable resistance material layer 112, because the upper part of the variable resistance material layer 112 is a relatively high resistance layer (first part 114a) and it has a smaller current flow area, so the upper part of the variable resistance material layer 112 The relatively high resistance layer has a better heating effect, and thus can effectively change the resistance state of the variable resistance material layer 112 .

4A to 4C are the manufacturing flow chart of the resistive memory according to the third embodiment of the present invention, which are cross-sectional views along the B section. In addition, the same components in the third embodiment and the first embodiment will be denoted by the same reference numerals, which will not be further described here.

Firstly, referring to FIG. 4A , strip electrodes 201 are formed on the dielectric substrate 100 . The material of the electrode 201 is, for example, titanium nitride, tantalum nitride, tungsten, copper, aluminum, aluminum-copper alloy or aluminum-silicon-copper alloy. The formation method of the electrode 201 is, for example, first forming a conductive material layer on the dielectric substrate 100, and then patterning the conductive material layer. Then, a dielectric layer 104 is formed on the electrode 201 .

Next, referring to FIG. 4B , part of the dielectric layer 104 is removed to expose part of the electrode 201 . Then, a part of the exposed electrode 201 is removed to form the electrode 202 and the opening 106 . The electrode 202 includes a first portion 202a and a second portion 202b, wherein the second portion 202b is located around the opening 106, and the first portion 202a is located below the second portion 202b. The opening 106 exposes a portion of the first portion 202a. In this embodiment, the materials of the first portion 202 a and the second portion 202 b of the electrode 202 are the same, which means that the electrode 202 has a single-layer structure. In this embodiment, the electrode 202 is the first electrode and serves as the lower electrode of the resistive memory.

In addition, the thickness D ₄ of the electrode 202 (the first portion 202 a ) located below the opening 106 is smaller than the thickness D ₃ of the electrode 202 (including the first portion 202 a and the second portion 202 b ) in other regions. Therefore, when operating the resistive memory of this embodiment, the cross-sectional area of the electrode 202 located below the opening 106 in the vertical current direction is smaller than the cross-sectional area of the electrode 202 in other regions in the vertical current direction. Therefore, the current density of the electrode 202 located under the opening 106 is higher than the current density of the electrode 202 in other regions.

Then, referring to FIG. 4C , a step similar to that of FIG. 2B is performed to form a sidewall dielectric layer 108 on the sidewall of the opening 106 . Then, the variable resistance material is filled into part of the opening 106 to form the variable resistance material layer 112 . In this embodiment, the variable resistance material layer 112 is in contact with the electrode 202 located below the opening 106 . Next, the conductive material is filled into the opening 106 to form the conductive layer 110 . Next, strip-shaped electrodes 214 are formed on the dielectric layer 104 and the variable resistance material layer 112 to complete the fabrication of the resistive memory in this embodiment. The material of the electrode 214 is, for example, titanium nitride, tantalum nitride, tungsten, copper, aluminum, aluminum-copper alloy or aluminum-silicon-copper alloy. The electrode 214 is formed by, for example, firstly forming a conductive material layer on the dielectric substrate 100 and then patterning the conductive material layer. In this embodiment, the electrode 214 is the second electrode and serves as the upper electrode of the resistive memory.

In this embodiment, when the material of the conductive layer 110 is the same as that of the electrode 214 , the conductive layer 110 can be regarded as a protruding portion of the electrode 214 . However, the present invention is not limited thereto. In other embodiments, according to actual application requirements, the electrode 214 may not have the above-mentioned conductive layer 110 , but the variable resistance material layer 112 is formed in the entire opening 106 .

According to the description in the first embodiment, it should be understood that when the operating current flows through the electrode 202 in contact with the variable resistance material layer 112, a better heating effect will be generated compared with other regions, and the variable resistance can be effectively changed. The resistive state of the material layer 112 and thus improve the operating efficiency of the resistive memory.

In this embodiment, the electrode 202 has a single-layer structure, but the invention is not limited thereto.

FIG. 5 is a schematic cross-sectional view of a resistive memory according to a fourth embodiment of the present invention, which is a cross-sectional view along a B-section. In this embodiment, the same elements as in FIG. 4C will be denoted by the same reference numerals. Referring to FIG. 5 , the materials of the first portion 202 a and the second portion 202 b of the electrode 202 are different. That is to say, the electrode 202 has a double-layer structure, wherein the resistance of the material of the first part 202a is higher than that of the material of the second part 202b, which means that the first part 202a is a relatively high resistance layer, while the second part 202b is a relatively low resistance layer. layer. The material of the relatively high resistance layer is, for example, titanium nitride, tantalum nitride or polysilicon, and the material of the relatively low resistance layer is, for example, tungsten, copper, aluminum, aluminum-copper alloy or aluminum-silicon-copper alloy. In this embodiment, the method for forming the electrode 202 includes the following steps: firstly, a relatively high-resistance material layer is formed on the dielectric substrate 100 . Next, a relatively low resistance material layer is formed on the relatively high resistance material layer. Then, the relatively low resistance material layer and the relatively high resistance material layer are patterned. Next, during the process of forming the opening 106 , part of the relatively low-resistance material layer is removed.

When operating the above-mentioned resistive memory with a double-layer structure, when the operating current flows into the electrode 202 and before flowing through the variable resistance material layer 112, the operating current mainly flows into the relatively low resistance layer (second portion 202b). Due to the low resistance of the relatively low resistance layer, excessive heat energy is not generated at this time. When the operating current wants to flow through the variable resistance material layer 112, because the lower part of the variable resistance material layer 112 is a relatively high resistance layer (first part 202a) and it has a smaller current flow area, so the lower part of the variable resistance material layer 112 The relatively high resistance layer has a better heating effect, and thus can effectively change the resistance state of the variable resistance material layer 112 .

6 to 7B are the manufacturing flowchart of the resistive memory according to the fifth embodiment of the present invention, wherein FIG. 7A is a cross-sectional view along the A section, and FIGS. 6 and 7B are the cross-sectional views along the B section. In FIG. 6 to FIG. 7B , the same components as those in the above-mentioned embodiments will be denoted by the same reference numerals, and will not be further described here.

First, please refer to FIG. 6 , after performing the steps described in FIG. 4B , a step similar to that in FIG. 2B is performed to form a sidewall dielectric layer 108 on the sidewall of the opening 106 . Then, the variable resistance material is filled into the opening 106 to form the variable resistance material layer 112 . In this embodiment, since the variable resistance material layer 112 must be in contact with the electrode 202 below it and the electrode above it (formed in a subsequent step), the variable resistance material layer 112 must be formed in the entire opening. 106 in. In this embodiment, the electrode 202 is the first electrode and serves as the lower electrode of the resistive memory.

Next, please refer to FIG. 7A and FIG. 7B at the same time, perform steps similar to those in FIG. 2C to FIG. 2D , remove part of the dielectric layer 104 to expose part of the sidewall dielectric layer 108 . Next, strip-shaped electrodes 714 are formed on the dielectric layer 104 and the variable resistance material layer 112 to complete the fabrication of the resistive memory in this embodiment. In addition, the electrode 714 includes a third portion 714a and a fourth portion 714b, and the electrode 114 can be a single-layer structure or a double-layer structure. In this embodiment, the electrode 714 is the second electrode and serves as the upper electrode of the resistive memory.

In addition, in FIG. 7A and FIG. 7B , although the electrode 714 and the electrode 202 are both shown as a single-layer structure, those with ordinary knowledge in the art should understand based on the foregoing embodiments that they can be adjusted and matched according to actual application requirements. The structure of electrode 714 and electrode 202 .

It is also mentioned that in the resistive memory of the present invention, the operating efficiency can be further improved by adjusting the width of the electrodes. The resistive memory of the first embodiment will be described below as an example.

8A and 8B are schematic diagrams of the operation of the resistive memory according to the first embodiment of the present invention, wherein FIG. 8B is a cross-sectional view along line CC of FIG. 8A . 8A and 8B, the width of the electrode 114 can be designed to be wide enough, so that when the operating current I ₁ flows into the electrode 114 and before reaching the variable resistance material layer 112 of the memory cell to be operated, the operating current I ₁ can be It mainly flows through the parts with lower resistance around the variable resistance material layer 112 of other memory cells (that is, the thicker part of the electrode 114), and does not flow through the parts on the variable resistance material layer 112 of these memory cells. The portion with higher resistance (ie, the portion where the electrode 114 has a smaller thickness). Therefore, until the operating current _I1 reaches the memory cell to be controlled, the operating current _I1 flows to the part with higher resistance on the variable resistance material layer 112 of the memory cell to be operated (that is, the part with a smaller thickness of the electrode 114) And flow through the variable resistance material layer 112 .

9A and 9B are schematic views of another operation of the resistive memory according to the first embodiment of the present invention, wherein FIG. 9B is a cross-sectional view along line DD in FIG. 9A . Please refer to FIG. 9A and FIG. 9B, the width of the electrode 114 can be designed to be narrow enough to force the operating current _I to flow through the higher resistance part of each variable resistance material layer 112 when flowing through each memory cell. (that is, the portion where the electrode 114 has a smaller thickness).

To sum up, in the resistive memory according to each embodiment of the present invention, the part of the electrode located on the variable resistance material layer has a smaller thickness, and thus has a higher resistance. In this way, when the operating current flows through the electrodes on the variable resistance material layer, a better heating effect can be generated, thereby effectively changing the resistance state of the variable resistance material layer, and thus improving the operating efficiency.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (28)

1. a resistance-type memory, is characterized in that, comprising:

First electrode, has Part I and Part II;

Second electrode, configures relative to described first electrode;

Variable resistive material layer, there is sidewall and relative first surface and second surface, the described first surface of wherein said variable resistive material layer is connected with the described Part I of described first electrode, described second surface and described second electrode of described variable resistive material layer are electrically connected, and described Part II around described variable resistive material layer described sidewall and be connected with described Part I;

First dielectric layer, is configured between described first electrode and described second electrode; And

Second dielectric layer, between the described Part II being configured at described variable resistive material layer and described first electrode.

2. resistance-type memory as claimed in claim 1, it is characterized in that, the material of described Part I is different from the material of described Part II, and the resistance of the material of the more described Part II of the resistance of the material of described Part I is high.

3. resistance-type memory as claimed in claim 2, it is characterized in that, the material of described Part I comprises titanium nitride, tantalum nitride or polysilicon, and the material of described Part II comprises tungsten, copper, aluminium, Al-zn-mg-cu alloy or al-si-cu alloy.

4. resistance-type memory as claimed in claim 1, it is characterized in that, the material of described Part I is identical with the material of described Part II, and the material of described first electrode comprises titanium nitride, tantalum nitride, tungsten, copper, aluminium, Al-zn-mg-cu alloy or al-si-cu alloy.

5. resistance-type memory as claimed in claim 1, it is characterized in that, also comprise conductor layer, and described conductor layer connects described variable resistive material layer and described second electrode.

6. resistance-type memory as claimed in claim 1, it is characterized in that, the material of described variable resistive material layer comprises chalcogen compound or transition metal oxide.

7. resistance-type memory as claimed in claim 1, it is characterized in that, described second electrode has Part III and Part IV, the described second surface of described variable resistive material layer is connected with the described Part III of described second electrode, and described Part IV around described variable resistive material layer described sidewall and be connected with described Part III.

8. resistance-type memory as claimed in claim 7, it is characterized in that, between the described Part II that described second dielectric layer is configured at described variable resistive material layer and described first electrode and between the described Part IV being configured at described variable resistive material layer and described second electrode.

9. resistance-type memory as claimed in claim 7, it is characterized in that, the material of described Part III is different from the material of described Part IV, and the resistance of the material of the more described Part IV of the resistance of the material of described Part III is high.

10. resistance-type memory as claimed in claim 9, it is characterized in that, the material of described Part III comprises titanium nitride, tantalum nitride or polysilicon, and the material of described Part IV comprises tungsten, copper, aluminium, Al-zn-mg-cu alloy or al-si-cu alloy.

11. resistance-type memories as claimed in claim 7, it is characterized in that, the material of described Part III is identical with the material of described Part IV, and the material of described second electrode comprises titanium nitride, tantalum nitride, tungsten, copper, aluminium, Al-zn-mg-cu alloy or al-si-cu alloy.

12. 1 kinds of resistance-type memories, is characterized in that, comprising:

First electrode, has the first thickness and the second thickness, and described first thickness is greater than described second thickness;

Second electrode, configures relative to described first electrode;

Memory element, has first surface and second surface, and has between described first electrode of described second thickness and described second electrode; And

Dielectric layer, around described memory element, wherein said dielectric layer becomes copline with the described first surface of described memory element, and described dielectric layer contacts described first electrode with described second thickness with the described first surface of described memory element;

Wherein, described second electrode has the 3rd thickness and the 4th thickness, described 3rd thickness is greater than described 4th thickness, described memory element has between described first electrode of described second thickness and described second electrode with described 4th thickness, and described dielectric layer becomes copline with the described second surface of described memory element, and described dielectric layer contacts described second electrode with described 4th thickness with the described second surface of described memory element.

13. resistance-type memories as claimed in claim 12, it is characterized in that, the material of described first electrode comprises titanium nitride, tantalum nitride, tungsten, copper, aluminium, Al-zn-mg-cu alloy or al-si-cu alloy.

14. resistance-type memories as claimed in claim 12, is characterized in that, also comprise conductor layer, and described conductor layer connects described memory element and described second electrode.

15. resistance-type memories as claimed in claim 12, it is characterized in that, the material of described memory element comprises chalcogen compound or transition metal oxide.

16. resistance-type memories as claimed in claim 12, it is characterized in that, the material of described second electrode comprises titanium nitride, tantalum nitride, tungsten, copper, aluminium, Al-zn-mg-cu alloy or al-si-cu alloy.

The manufacture method of 17. 1 kinds of resistance-type memories, is characterized in that, comprising:

Form the first electrode, described first electrode comprises Part I and Part II;

Form the second electrode relative to described first electrode;

The first dielectric layer is formed between described first electrode and described second electrode;

The second dielectric layer and variable resistive material layer is formed in described first dielectric layer, wherein said variable resistive material layer has sidewall and relative first surface and second surface, described second dielectric layer is around the described sidewall of described variable resistive material layer, the described Part I of described first electrode connects the described first surface of described variable resistive material layer, described second electrode is electrically connected the described second surface of described variable resistive material layer, described Part II around described variable resistive material layer described sidewall and be connected with described Part I, and described second dielectric layer is between the described Part II and described variable resistive material layer of described first electrode.

The manufacture method of 18. resistance-type memories as claimed in claim 17, is characterized in that, comprising:

Form described second electrode;

Described first dielectric layer is formed on described second electrode;

In described first dielectric layer, form perforate, described perforate exposes described second electrode of part;

The sidewall of described perforate is formed described second dielectric layer;

Described variable resistive material layer is formed in described perforate;

Remove described first dielectric layer of part, to expose described second dielectric layer of part; And

Described first electrode is formed on described first dielectric layer and described variable resistive material layer.

The manufacture method of 19. resistance-type memories as claimed in claim 18, is characterized in that, after described second dielectric layer of formation and before inserting described variable resistive material layer, is also included in described perforate and forms conductor layer.

The manufacture method of 20. resistance-type memories as claimed in claim 18, it is characterized in that, the described Part I of described first electrode is relative resistive formation, and the described Part II of described first electrode is rather low resistance layer.

The manufacture method of 21. resistance-type memories as claimed in claim 20, it is characterized in that, the method forming described first electrode on described first dielectric layer and described variable resistive material layer comprises:

Rather low resistance material layer is formed on described first dielectric layer and described variable resistive material layer;

Carry out planarization process, remove part described rather low resistance material layer to the described first surface exposing described second dielectric layer and described variable resistive material layer;

In described rather low resistance material layer with described variable resistive material layer is formed relative high-resistance material layer; And

Rather low resistance material layer described in patterning and described relative high-resistance material layer, to form described first electrode.

The manufacture method of 22. resistance-type memories as claimed in claim 17, is characterized in that, comprising:

Form the first electrode material layer;

Described first dielectric layer is formed on described first electrode material layer;

Remove described first dielectric layer of part and described first electrode material layer of part, to form perforate and described first electrode, wherein, described first electrode material layer around described perforate is described Part II, and described first electrode material layer be positioned at below described Part II is described Part I;

The sidewall of described perforate is formed described second dielectric layer;

Described variable resistive material layer is inserted in described perforate; And

Described second electrode is formed on described first dielectric layer and described variable resistive material layer.

The manufacture method of 23. resistance-type memories as claimed in claim 22, is characterized in that, after inserting described variable resistive material layer and before described second electrode of formation, is also included in described perforate and inserts conductor layer.

The manufacture method of 24. resistance-type memories as claimed in claim 22, it is characterized in that, the described Part I of described first electrode is relative resistive formation, and the described Part II of described first electrode is rather low resistance layer.

The manufacture method of 25. resistance-type memories as claimed in claim 24, is characterized in that, form the method for described perforate and described first electrode, comprising:

Form relative high-resistance material layer;

Rather low resistance material layer is formed on described relative high-resistance material layer;

Rather low resistance material layer described in patterning and described relative high-resistance material layer;

Described first dielectric layer is formed on described rather low resistance material layer; And

Remove described first dielectric layer of part and the described rather low resistance material layer of part.

The manufacture method of 26. resistance-type memories as claimed in claim 22, it is characterized in that, form described second electrode on described first dielectric layer and described variable resistive material layer before, also comprise and remove described first dielectric layer of part, to expose described second dielectric layer of part, wherein said second electrode comprises Part III and Part IV, the described Part III of described second electrode connects the described second surface of described variable resistive material layer, described Part IV around described variable resistive material layer described sidewall and be connected with described Part III, and described second dielectric layer is between the described Part IV and described variable resistive material layer of described second electrode.

The manufacture method of 27. resistance-type memories as claimed in claim 26, it is characterized in that, the described Part III of described second electrode is relative resistive formation, and the described Part IV of described second electrode is rather low resistance layer.

The manufacture method of 28. resistance-type memories as claimed in claim 27, it is characterized in that, the method forming described second electrode on described first dielectric layer and described variable resistive material layer comprises:

Rather low resistance material layer is formed on described first dielectric layer and described variable resistive material layer;

Carry out planarization process, remove part described rather low resistance material layer to the described second surface exposing described second dielectric layer and described variable resistive material layer;

In described rather low resistance material layer with described variable resistive material layer is formed relative high-resistance material layer; And

Rather low resistance material layer described in patterning and described relative high-resistance material layer, to form described second electrode.