CN101783298B - Method for inhibiting growth of high-k gate dielectric/metal gate structure interface layer - Google Patents

Abstract

The invention discloses a method for inhibiting the growth of an interface layer of a high dielectric constant (k) gate dielectric/metal gate structure under high-temperature annealing, which comprises the following steps: growing SiO on silicon substrate₂An interfacial layer; in SiO₂Depositing a high-k gate dielectric layer on the interface layer; depositing a metal gate electrode on the high-k gate dielectric layer; and depositing a polysilicon cap layer on the metal gate electrode. The invention can prevent oxygen molecules in the annealing environment from diffusing to SiO under the condition of high temperature₂The interface of/Si, which in turn reacts with the Si substrate to form SiO₂The purpose of the layer.

Description

Method for suppressing growth of interface layer of high-k gate dielectric/metal gate structure

technical field

The invention relates to the technical field of high-k gate dielectric and metal gate structure in nanometer CMOS technology, in particular to a method for suppressing the growth of an interface layer of a high-dielectric constant (high-k) gate dielectric/metal gate structure under high-temperature annealing.

Background technique

The application of key core technologies of 32/22nm integrated circuit technology is an inevitable trend in the development of integrated circuits, and it is also one of the topics that major international semiconductor companies and research organizations are competing to research and develop. CMOS device gate engineering research centered on "high-k/metal gate" technology is the most representative key core process in 32/22 nanometer technology, and related materials, processes and structures have been extensively studied.

For MOS devices with a high-k/metal gate structure, a very important parameter is the equivalent oxide thickness (Equivalent Oxide Thickness, EOT), and a sufficiently small EOT is a necessary condition for ensuring the scaling of MOS devices and improving performance. Generally, there will be a thin SiO ₂ interface layer (0.5-1 nanometer) between the high-k gate dielectric layer and the silicon substrate. In order to improve the quality of the interface between the high-k gate dielectric and the silicon substrate, the SiO ₂ interface layer is usually grown by high-temperature thermal oxidation. On the other hand, in order to meet the requirements of scaling down the size of MOS devices in 32/22nm technology, we hope that the thickness of the SiO ₂ interface layer with a lower dielectric constant should be as small as possible to achieve the purpose of reducing the EOT of the entire gate structure.

In the CMOS device processing technology, in order to activate the source and drain impurities of the device, it is necessary to perform high temperature annealing treatment at about 900-1050°C. During this process, oxygen in the annealing environment will diffuse into the MOS device with a high-k/metal gate structure due to the high temperature, and pass through the dielectric layer and finally reach the interface between the gate dielectric and the silicon substrate, and react with the silicon substrate SiO ₂ is generated to thicken the SiO ₂ interface layer. This problem will lead to an increase in the EOT of the entire gate structure, and ultimately affect the overall performance of the device.

Contents of the invention

(1) Technical problems to be solved

In view of this, the main purpose of the present invention is to provide a method for suppressing the growth of the interfacial layer of the high-k gate dielectric/metal gate structure under high-temperature annealing, so as to prevent oxygen molecules in the annealing environment from diffusing to SiO under high-temperature conditions. ₂ /Si interface, and then react with the Si substrate to form a SiO ₂ layer.

(2) Technical solution

In order to achieve the above object, the present invention provides a method for suppressing the growth of the interfacial layer of the high-k gate dielectric/metal gate structure under high-temperature annealing, the method comprising:

Growth of a _SiO2 interfacial layer on a silicon substrate;

Depositing a high-k gate dielectric layer on the SiO ₂ interface layer;

Depositing a metal gate electrode on the high-k gate dielectric layer; and

A polysilicon cap layer is deposited on the metal gate electrode.

In the above solution, the thickness of the SiO ₂ interface layer grown on the silicon substrate is 0-1 nm.

In the above scheme, after depositing a polysilicon cap layer on the metal gate electrode, the method further includes: performing high-temperature annealing treatment on the polysilicon cap layer, and then depositing a layer of metallic nickel on the polysilicon cap layer, and The metal nickel layer is heat-treated to form a nickel silicide cap layer.

In the above solution, the high-temperature annealing treatment of the polysilicon cap layer is performed at 900-1050°C, and the heat treatment of the metal nickel layer is performed at 400-600°C.

In the above solution, after depositing a polysilicon cap layer on the metal gate electrode, the method further includes: performing ion implantation on the polysilicon cap layer, followed by high-temperature annealing to activate impurities to form a heavily doped polysilicon cap layer.

In the above solution, the impurity activation through high temperature annealing is carried out at 900-1050°C.

(3) Beneficial effects

The method for suppressing the growth of the interfacial layer of the high-k gate dielectric/metal gate structure under high-temperature annealing provided by the present invention is to deposit a layer of polysilicon cap layer on the metal gate to prevent oxygen in the annealing environment under high-temperature conditions. Molecules diffuse to the SiO ₂ /Si interface, and then react with the Si substrate to form a SiO ₂ layer.

Description of drawings

Fig. 1 is a schematic diagram of growing _SiO on the silicon substrate that has been processed in the previous stage;

Fig. 2 is a schematic diagram of depositing a high-k gate dielectric layer on the _SiO2 interface layer;

3 is a schematic diagram of depositing a metal gate electrode on a high-k gate dielectric layer;

4 is a schematic diagram of depositing a layer of polysilicon film on the metal gate electrode;

5 is a schematic diagram of ion implantation of the polysilicon layer;

6 is a schematic diagram of annealing the doped polysilicon layer at 1000° C.;

FIG. 7 is a schematic diagram of annealing the polysilicon structure at 1000° C.;

Fig. 8 is a schematic diagram of depositing a layer of metal nickel film on the polysilicon layer after the annealing treatment;

FIG. 9 is a schematic diagram of annealing the nickel/polysilicon structure at a temperature of 400-600° C. to form a nickel silicide cap layer.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

The core idea of the present invention is: after the high-k gate dielectric/metal gate structure is formed, a polysilicon cap layer is deposited on the metal gate; the polysilicon cap layer is subjected to high-temperature annealing treatment, and then a layer of Metal nickel, and heat-treat the metal nickel layer to form a nickel silicide cap layer; or, first perform ion implantation on the polysilicon cap layer, and then perform impurity activation through high-temperature annealing to form a heavily doped polysilicon cap layer.

Aiming at the above core idea of the present invention, the following will describe in detail in conjunction with two specific embodiments.

Embodiment one

As shown in Figure 1, a 0.5nm-thick SiO ₂ interface layer is grown on a silicon substrate that has been processed in the previous stage.

As shown in Figure 2, a high-k gate dielectric layer is deposited on the SiO ₂ interface layer.

As shown in FIG. 3 , a metal gate electrode is deposited on the high-k gate dielectric layer.

As shown in Figure 4, a layer of polysilicon film is deposited on the metal gate electrode.

As shown in FIG. 5, ion implantation is performed on this polysilicon layer.

As shown in FIG. 6, the doped polysilicon layer is annealed at 1000°C.

Embodiment two

As shown in Figure 1, a SiO ₂ interface layer with a thickness of 0.5nm is grown on the silicon substrate that has been processed in the early stage.

As shown in Figure 2, a high-k gate dielectric layer is deposited on the SiO ₂ interface layer.

As shown in FIG. 3 , a metal gate electrode is deposited on the high-k dielectric layer.

As shown in FIG. 4 , a layer of paracrystalline silicon thin film is deposited on the metal gate electrode.

As shown in FIG. 7, the polysilicon structure is annealed at 1000°C.

As shown in FIG. 8, a metal nickel film is deposited on the polysilicon layer after the annealing treatment.

As shown in FIG. 9 , at a temperature of 400-600° C., the nickel/polysilicon structure is annealed to form a nickel silicide cap layer.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (2)

1. one kind is suppressed high-k gate dielectric/metal-gate structures method that boundary layer is grown under high annealing, it is characterized in that this method comprises:

SiO grows on silicon substrate ₂Boundary layer;

At SiO ₂Deposition high-k gate dielectric layer on the boundary layer;

Plated metal gate electrode on the high-k gate dielectric layer;

Deposition one deck polycrystalline silicon cap layer on metal gate electrode; And

Under 900～1050 ℃, said polycrystalline silicon cap layer is carried out The high temperature anneal, deposit layer of metal nickel on said polycrystalline silicon cap layer then, and under 400～600 ℃, the metal nickel dam heat-treated and form nickel silicide cap layer; Perhaps said polycrystalline silicon cap layer is carried out ion and inject, carry out impurity activation through 900～1050 ℃ high annealing again, form heavily doped polycrystalline silicon cap layer.

2. the method for inhibition high-k gate dielectric/metal-gate structures according to claim 1 boundary layer growth under high annealing is characterized in that the said SiO that on silicon substrate, grows ₂The thickness range of boundary layer is 0.5～1nm.

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