CN104681435A - Forming method of transistor structure - Google Patents
Forming method of transistor structure Download PDFInfo
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- CN104681435A CN104681435A CN201310611805.5A CN201310611805A CN104681435A CN 104681435 A CN104681435 A CN 104681435A CN 201310611805 A CN201310611805 A CN 201310611805A CN 104681435 A CN104681435 A CN 104681435A
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Abstract
The invention discloses a forming method of a transistor structure. The forming method comprises the following steps of providing a semiconductor substrate; forming an interfacial layer on the semiconductor substrate; forming a high-K gate dielectric layer on the interfacial layer; forming a cap layer on the high-K gate dielectric layer; forming a metal gate on the cap layer; after forming the cap layer, carrying out anaerobic densified treatment on the interfacial layer and the high-K gate dielectric layer. According to the forming method, the interfacial layer is firstly formed on the semiconductor substrate, the high-K gate dielectric layer is formed on the interfacial layer, the cap layer is formed on the high-K gate dielectric layer, and then the anaerobic densified treatment is carried out on the interfacial layer and the high-K gate dielectric layer, owing to formation of the cap layer, the cap layer can protect the high-K gate dielectric layer in an anaerobic densified treatment, so that oxidation of trace amounts of oxygen in the environment on the interfacial layer and the high-K gate dielectric layer can be prevented, and thus shift of threshold voltage of a transistor device which is subsequently formed, and the performance of the transistor is improved.
Description
Technical field
The present invention relates to field of semiconductor technology, especially relate to a kind of formation method of transistor.
Background technology
Along with the fast development of ic manufacturing technology, impel the semiconductor device in integrated circuit, especially Metal-oxide-semicondutor (Metal Oxide Semiconductor, MOS) size of transistor constantly reduces, and meets the miniaturization of integrated circuit development and integrated requirement with this.In the process that MOS transistor scales reduces, receive challenge using silica or silicon oxynitride as the technique of gate dielectric layer.Occur comprising the problems such as leakage current increase and Impurity Diffusion as the transistor that gate dielectric layer is formed using silica or silicon oxynitride, thus affect the threshold voltage of transistor, and then affect the performance of semiconductor device.
For overcoming the above problems, the MOS transistor of high K-metal gates (metal gate) structure is suggested.Adopt high K (dielectric constant) material to replace conventional silica or silicon oxynitride gate dielectric material, while dimensions of semiconductor devices reduces, the generation of leakage current can be reduced, improve the performance of semiconductor device.
But MOS transistor uses the shortcoming of high-K gate dielectric layer to be, high-K gate dielectric layer interface quality is poor, if directly form high-K gate dielectric layer on a semiconductor substrate, the interface of poor quality easily weakens the electric property of the final semiconductor device formed.For this reason, boundary layer (interfacial layer can be set between Semiconductor substrate and high-K gate dielectric layer, IL), boundary layer can not only provide the interface of better quality between Semiconductor substrate and boundary layer, the interface of better quality can also be provided between high-K gate dielectric layer and boundary layer, thus improve the interfacial characteristics between high-K gate dielectric layer and substrate.
Incorporated by reference to reference to figure 1 and Fig. 2, the formation method of existing transistor comprises: S1, provides Semiconductor substrate 100; S2, forms boundary layer 110 on a semiconductor substrate 100; S3, boundary layer 110 is formed high-K gate dielectric layer 120; S4, carries out annealing in process; S5, high-K gate dielectric layer 120 is formed cap layer 130.
Wherein, after formation high-K gate dielectric layer 120, carrying out annealing in process is density in order to increase high-K gate dielectric layer 120, and the trapped charge (charge traps) reduced in boundary layer 110 and high-K gate dielectric layer 120, but described annealing in process causes device threshold voltage drift (Shift) simultaneously.
For this reason, need a kind of formation method of new transistor, to prevent transistor device threshold voltage shift.
Summary of the invention
The problem that the present invention solves provides a kind of formation method of transistor, to prevent device threshold voltage drift, improves the performance of transistor.
For solving the problem, the invention provides a kind of formation method of transistor, comprising:
Semiconductor substrate is provided;
Form boundary layer on the semiconductor substrate;
Described boundary layer forms high-K gate dielectric layer;
Described high-K gate dielectric layer forms cap layer;
Described cap layer forms metal gates;
After formation cap layer, anaerobic densification is carried out to described boundary layer and described high-K gate dielectric layer.
Optionally, described anaerobic densification is laser annealing technique.
Optionally, described laser annealing technique carries out in the atmosphere of inert gas or nitrogen, and the annealing time scope of described laser annealing technique is 0.25 millisecond ~ 1 millisecond, and the annealing region of described laser annealing technique is 600 DEG C ~ 1100 DEG C.
Optionally, described laser annealing technique takes fixed laser hot spot and the mode of mobile Semiconductor substrate is carried out, and described laser facula is that length is 5mm ~ 8mm and width is the rectangle of 125 μm or length is 8mm ~ 12mm and width is the rectangle of 75 μm.
Optionally, after described high-K gate dielectric layer forms described cap layer, and before anaerobic densification is carried out to described boundary layer and described high-K gate dielectric layer, also comprise: on described cap layer, form dummy grid.
Optionally, after described cap layer forms described dummy grid, and before anaerobic densification is carried out to described boundary layer and described high-K gate dielectric layer, also comprise: remove described dummy grid.
Optionally, the material of described boundary layer is silicon dioxide or nitrogenous silicon dioxide, and thickness range is
Optionally, the material of described high-K gate dielectric layer is one or more in hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminium oxide, and thickness range is
Optionally, the material of described cap layer is one or more in titanium nitride, nitrogenize thallium and tungsten nitride, and thickness range is
Optionally, described semiconductor substrate surface has oxide layer, before forming boundary layer on the semiconductor substrate, also comprises step: remove described oxide layer until expose described semiconductor substrate surface.
Compared with prior art, technical scheme of the present invention has the following advantages:
In technical scheme of the present invention; first form boundary layer on a semiconductor substrate; boundary layer forms high-K gate dielectric layer; high-K gate dielectric layer forms cap layer; afterwards; again anaerobic densification is carried out to boundary layer and high-K gate dielectric layer; owing to defining cap layer; cap layer can be protected high-K gate dielectric layer in anaerobic densification process; to prevent in environment the oxygen of trace to the oxidation of boundary layer and high-K gate dielectric layer; thus prevent the transistor device threshold voltage of follow-up formation from drifting about, improve the performance of transistor.
Further, described anaerobic densification adopts laser annealing technique, therefore the processing time is short, and other device outside processing region is not almost affected, thus both ensured that the trapped charge in boundary layer and high-K gate dielectric layer was eliminated, can prevent further again boundary layer in annealing process by environment trace oxygen be oxidized.
Accompanying drawing explanation
Fig. 1 is the formation method flow schematic diagram of existing transistor;
Fig. 2 is the formation method structural representation of existing transistor;
Fig. 3 to Fig. 5 is the formation method structural representation of embodiment of the present invention transistor.
Embodiment
The formation method of existing transistor carries out annealing in process after formation high-K gate dielectric layer, usual employing be rapid thermal annealing (rapid thermal annealing, RTA) treatment process, this is that one is maintained at an elevated temperature for a period of time the thermal anneal process technique of (being generally between 5S to 120S).Now, in the cavity atmosphere of equipment for Heating Processing, owing to having Leakage Gas or gas pure not, can there is oxygen in the gaseous environment in cavity, oxygen easily causes Oxidative demage, particularly to boundary layer to high-K gate dielectric layer and boundary layer in high-temperature atmosphere, oxygen atom easily enters into interface layer surfaces through high-K gate dielectric layer or oxidation is carried out in below, the thickness of boundary layer is increased, and then causes boundary layer property of thin film to worsen, cause threshold voltage of semiconductor device to drift about.In addition, the heat budget of existing quick thermal annealing process is higher, and cost is high and waste energy.
For this reason, the invention provides a kind of formation method of transistor, described formation method first forms boundary layer on a semiconductor substrate, boundary layer forms high-K gate dielectric layer, high-K gate dielectric layer forms cap layer, afterwards, again anaerobic densification is carried out to boundary layer and high-K gate dielectric layer, owing to defining cap layer, cap layer can be protected high-K gate dielectric layer in anaerobic densification process, to prevent in environment the oxygen of trace to the oxidation of boundary layer and high-K gate dielectric layer, thus prevent the transistor device threshold voltage of follow-up formation from drifting about.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
The embodiment of the present invention provides a kind of formation method of transistor, incorporated by reference to reference to figure 3 to Fig. 5.
Please refer to Fig. 3, first the formation method of the present embodiment transistor provides Semiconductor substrate 200.
In the present embodiment, Semiconductor substrate 200 can be silicon substrate, also can be the Semiconductor substrate such as silicon-on-insulator or SiGe.
In the present embodiment, Semiconductor substrate 200 comprises isolation structure 201, to isolate active area (mark).Semiconductor substrate 200 can inject multiple Doped ions, to form corresponding doped region (mark).
Under normal circumstances, when Semiconductor substrate 200 exposes in atmosphere, Semiconductor substrate 200 surface will be oxidized to native oxide (native oxide) and form oxide layer (not shown).Oxide layer is not that the ideal of semiconductor device is formed usually, because usually have in impurity embedded oxide layer, these impurity can destroy the dielectric property of dielectric.Such as, metal impurities can make oxide layer conduct electricity, and destroy the performance of semiconductor device thus.Therefore, the oxide layer on Semiconductor substrate 200 surface need be removed.In the present embodiment, concrete, HF acid solution can be utilized to remove oxide layer, and then by washed with de-ionized water Semiconductor substrate 200, and dry.
Please continue to refer to Fig. 3, form boundary layer 210 on semiconductor substrate 200.
In the present embodiment, the material of boundary layer 210 can be silica or silicon oxynitride.Further, hot growth method (Rapid Thermal Oxidation, RTO), chemically grown method or high-temp in-situ vapor growth method (in-situ steam generation, ISSG) can be adopted to form boundary layer 210 on semiconductor substrate 200.
Hot growth method is utilized to form silica (SiO
2) technique of boundary layer 210 can comprise: utilize smelting furnace, bake the rapid thermal process apparatus such as station, at O
2or H
2o and H
2in gas, substrate is heated, to grow a layer thickness at substrate surface be
arrive
silica.
The technique utilizing hot growth method to form silicon oxynitride (SiON) boundary layer 210 can comprise: utilize smelting furnace, bake the rapid thermal process apparatus such as station, at O
2in gas, substrate is heated, to grow a layer thickness at substrate surface be
arrive
silica, then utilize plasma nitridation process to carry out nitrogen treatment to silica, form silicon oxynitride boundary layer 210.
The thickness range that usual boundary layer 210 allows can be
arrive
between.Boundary layer 210 can not be too thick, otherwise can weaken the superiority of high-K gate dielectric layer as gate dielectric layer.In addition, if boundary layer 210 is too thick, equivalent oxide thickness (Equivalent Oxide Thickness, EOT) can be increased, so that reduce drive current.
According to different device requirement, boundary layer 210 can have different thickness, but it is significant to note that, for a transistor device being provided with boundary layer 210 respective thickness, if the thickness deviation of end interface layer 210 is more than 5% of gross thickness, the penalty of transistor device will be caused.
Please refer to Fig. 4, boundary layer 210 is formed high-K gate dielectric layer 220.
In the present embodiment, the dielectric constant of high-K gate dielectric layer 220 is greater than 8, to reduce the equivalent oxide thickness (EOT) of gate dielectric layer, improves the drive current of transistor.The material of high-K gate dielectric layer 220 can be one or more in hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminium oxide etc.Certainly, high-K gate dielectric layer 220 also can comprise the dielectric material that other dielectric constant is greater than silicon oxide dielectric constant (3.9), such as, can mix some other elements in high-K gate dielectric layer 220, comprise Si, La etc.
In the present embodiment, atomic layer deposition method (Atomic Layer Deposition can be adopted, ALD), metal organic chemical vapor deposition method (Metal-Organic Chemical Vapor Deposition, MOCVD), molecular beam epitaxy (Molecular Beam Epitaxy, MBE), chemical vapour deposition technique (Chemical Vapor Deposition, or physical vaporous deposition (Physical Vapor Deposition CVD), PVD) on boundary layer 210, high-K gate dielectric layer 220 is formed, certainly, other technology well known to those of ordinary skill in the art also can be utilized to form high-K gate dielectric layer 220.
With hafnium oxide (HfO
2) be example, ALD method can be adopted to obtain high-K gate dielectric layer 220, and the equation of reaction is: HfCl
4+ 2H
2o=HfO
2+ 4HCl.Reaction temperature generally can control between 200 DEG C to 450 DEG C, and the Stress control of reaction chamber is between 2Torr to 20Torr, and the thickness range of the high-K gate dielectric layer 220 of generation is passable
arrive
between, specifically can form different thickness according to different device requirement.High-K gate dielectric layer 220 has extraordinary thermal stability and mechanical strength, can obtain less leakage current, and reduce Impurity Diffusion.
Trapped charge can be there is in the boundary layer 210 and high-K gate dielectric layer 220 of above-mentioned steps formation, these trapped charges can cause producing trap voltage, thus the transistor device threshold voltage of follow-up formation is raised, therefore, need to adopt annealing process to eliminate corresponding trapped charge.
But, if now adopt existing method to carry out quick thermal annealing process, the oxygen atom in environment and boundary layer 210 can be caused again to interact, cause boundary layer 210 thickness to increase, cause transistor device threshold voltage shift.As previously described, the thickness that boundary layer 210 is arranged at first can not have too large deviation in the final device formed.When the thickness of boundary layer 210 increases or reduces more than 5%, device performance will be caused influenced.The thickness such as arranging boundary layer 210 is at first
time, if after technique terminates, the gross thickness of boundary layer 210 is increased to
above, will cause transistor device threshold voltage that the corruptions such as drift occur.
For this reason, after the present embodiment forms high-K gate dielectric layer 220 on boundary layer 210, first do not carry out annealing in process.But first form cap layer, please continue to refer to the following content of this specification.
Please refer to Fig. 5, high-K gate dielectric layer 220 is formed cap layer 230.
In the present embodiment, the material of cap layer 230 can be titanium nitride, nitrogenize thallium, tungsten nitride one or more, and the material of cap layer 230 is different from the material of high-K gate dielectric layer 220.
In the present embodiment, the formation process of cap layer 230 can be chemical vapour deposition technique, physical vaporous deposition or atomic layer deposition method.For physical vaporous deposition, the concrete sputtering method that adopts makes titanium and the nitrogen passed in reative cell form titanium nitride, covers on high-K gate dielectric layer 220, forms cap layer 230.
In the present embodiment, cap layer 230 can play the effect of three aspects: the first, and the surface of protection high-K gate dielectric layer 220, makes the surface of high-K gate dielectric layer 220 injury-free in the process of follow-up formation metal gates; The second, as diffusion trapping layer, operationally, charge carrier can not diffuse in high-K gate dielectric layer 220 transistor that subsequent technique is formed, and inhibits the generation of leakage current; 3rd, in the following anaerobic densification process being about to carry out, prevent oxygen from entering boundary layer 210 and high-K gate dielectric layer 220 causes Oxidative demage effect.About the effect of cap layer 230 third aspect, specification is follow-up will be further illustrated.
Please continue to refer to Fig. 5, wafer being specifically as follows to Semiconductor substrate 200() back side cleans.
In the present embodiment, described cleaning step has been that follow-up anaerobic densification is prepared.This is because, usually, formation process and the anaerobic densification of above-mentioned each layer need to carry out in different equipment, if do not cleaned, the impurity that then Semiconductor substrate 200 is brought in above-mentioned each layer forming step process will use follow-up equipment and cause cross pollution, particularly Semiconductor substrate 200 back side (with the one side of surface opposite forming device) rete of being formed, very easily pollutes equipment parts such as (mainly) transmission arms.Therefore the present embodiment cleans Semiconductor substrate 200, to remove described impurity, is particularly used for removing the film that grows in above-mentioned technical process of Semiconductor substrate 200 back side, thus prevents the cross-contamination issue between different platform.In the present embodiment, cleaning the solution that uses is can be the mixed solution of hydrofluoric acid and nitric acid, and cleaning temperature may be selected to be room temperature (about 25 DEG C).
Please continue to refer to Fig. 5, anaerobic densification is carried out to described boundary layer 210 and high-K gate dielectric layer 220.
In the present embodiment, described anaerobic densification is carried out in the atmosphere of inert gas, namely adopts inert gas to carry out anaerobic densification as protective gas.Inert gas can not react with boundary layer 210 and high-K gate dielectric layer 220, therefore the performance of the transistor that subsequent technique is formed can not be affected, and inert gas is monoatomic gas, heat of desorption can not be divided, therefore the effect of thermal annealing can not be affected, the simultaneously nonflammable or blast of inert gas, fail safe is high.Inert gas described in the present embodiment can be specifically argon gas or helium.
It should be noted that, in other embodiments, also can adopt the nitrogen (N that stability is stronger
2) carrying out anaerobic densification as protective gas, nitrogen more easily obtains, thus reduces process costs.
It should be noted that, although the present embodiment selects the atmosphere of inert gas to carry out anaerobic densification, but, because the degree of purity of gas can not reach 100%, and, in processing procedure, the air of device interior possibly cannot be removed, and in addition, may micro-air be had to enter in certain process, therefore, the oxygen of trace can still be there is in the environment in equipment.
In the present embodiment, described anaerobic densification is laser annealing technique, namely adopts laser annealing technique to carry out described anaerobic densification.
In the present embodiment, the laser that described laser annealing technique adopts is provided by carbon dioxide laser generator, carbon dioxide laser generator can produce the laser of continuous wavelength, annealing in process is carried out to the boundary layer 210 in Semiconductor substrate 200 and high-K gate dielectric layer 220, thus make high-K gate dielectric layer 220 densification, make the trapped charge in boundary layer 210 and high-K gate dielectric layer 220 be eliminated simultaneously.
In the operating process of described anaerobic densification, Semiconductor substrate 200 can be placed on above hot travelling table (temperature is generally between 200 DEG C to 500 DEG C), stabilizing carbon dioxide laser generator, to produce fixing laser beam spot, and come to irradiate annealing in process to the scanning of structure in Semiconductor substrate 200 by fast moving work table.
In the present embodiment, the each position of the Semiconductor substrate 200 heat treated time is determined by the width of laser beam spot and the translational speed of workbench, in scanning process, the area only having laser beam spot to irradiate is heated, other region then maintains very low temperature (close to room temperature), does not therefore almost affect other device outside processing region.
In the present embodiment, the size of laser beam spot can have two kinds, the first for length be 5mm ~ 8mm, width is the rectangle laser beam spot of 125 μm, the second is length is 8mm ~ 12mm, and width is the rectangle laser beam spot of 75 μm, can need to select according to the time of densification, the first laser facula is suitable for time longer densification, and the second laser facula is suitable for time shorter densification.
In the present embodiment, the annealing region of described laser annealing technique is 600 DEG C ~ 1100 DEG C, trapped charge in described temperature range inner boundary layer 210 and high-K gate dielectric layer 220 can be eliminated rapidly, therefore, the required thermal annealing time is very short, and each position annealing time only needs 0.25 millisecond ~ 1 millisecond.Because the processing time is only 0.25 millisecond ~ 1 millisecond, therefore the heat budget (thermal budget) of whole thermal process is low, substantially again can not be oxidized boundary layer 210.
In the present embodiment, due to high-K gate dielectric layer 220 being formed with cap layer 230, cap layer 230 can prevent oxygen from entering into boundary layer 210 and high-K gate dielectric layer 220 further, thus prevents the oxygen of trace in environment from causing oxidation to boundary layer 210 and high-K gate dielectric layer 220 further.
After Millisecond laser annealing technique, the lattice structure of high-K gate dielectric layer 220 is adjusted, and therefore compactness and uniformity are all improved, and then improves the performance of semiconductor device.And whole annealing process required time is short, reduces the heat budget of semiconductor device, prevent boundary layer 210 because of annealing process the oxidized phenomenon causing thickness to increase, therefore also just prevent transistor device threshold voltage shift.
In brief, in described laser annealing technique process, both the effect served modified film (namely reduces the trapped charge in boundary layer 210 and high-K gate dielectric layer 220, and make high-K gate dielectric layer 220 densification and homogenizing), again reduce oxygen in environment to the side effect of film (boundary layer 210 and high-K gate dielectric layer 220), therefore the thickness of boundary layer 210 can not change substantially, thus prevents formed transistor device threshold voltage from drifting about.
In the transistor that the present embodiment is formed, high-K gate dielectric layer 220 has compactness and the high advantage of uniformity, and the thickness of boundary layer 210 meets required setting, and therefore threshold voltage does not drift about, and the reliability of transistor is high.
It should be noted that, the present embodiment is after formation cap layer 230, carries out described anaerobic densification immediately.But, in other embodiments of the invention, also after can forming dummy grid on follow-up cap layer, carry out described anaerobic densification again, can also be even after removal dummy grid, and before formation metal gates, then carrying out described anaerobic densification, the present invention is not construed as limiting this.
It should be noted that, the formation method of the present embodiment transistor is follow-up also comprises formation metal gates, to carrying out ion implantation in the Semiconductor substrate of metal gates both sides to form source/drain, the steps such as annealing in process makes the ion diffuse of injection even are carried out to Semiconductor substrate, thus form complete transistor, can with reference to the forming step of existing transistor, the present embodiment no longer describes in detail this.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a formation method for transistor, is characterized in that, comprising:
Semiconductor substrate is provided;
Form boundary layer on the semiconductor substrate;
Described boundary layer forms high-K gate dielectric layer;
Described high-K gate dielectric layer forms cap layer;
Described cap layer forms metal gates;
After formation cap layer, anaerobic densification is carried out to described boundary layer and described high-K gate dielectric layer.
2. form method as claimed in claim 1, it is characterized in that, described anaerobic densification is laser annealing technique.
3. form method as claimed in claim 2, it is characterized in that, described laser annealing technique carries out in the atmosphere of inert gas or nitrogen, the annealing time scope of described laser annealing technique is 0.25 millisecond ~ 1 millisecond, and the annealing region of described laser annealing technique is 600 DEG C ~ 1100 DEG C.
4. form method as claimed in claim 3, it is characterized in that, described laser annealing technique takes fixed laser hot spot and the mode of mobile Semiconductor substrate is carried out, described laser facula be long for 5mm ~ 8mm and wide be the rectangle of 125 μm, or described laser facula be long for 8mm ~ 12mm and wide be the rectangle of 75 μm.
5. form method as claimed in claim 1, it is characterized in that, after described high-K gate dielectric layer forms described cap layer, and before anaerobic densification is carried out to described boundary layer and described high-K gate dielectric layer, also comprise: on described cap layer, form dummy grid.
6. form method as claimed in claim 5, it is characterized in that, after described cap layer forms described dummy grid, and before anaerobic densification is carried out to described boundary layer and described high-K gate dielectric layer, also comprise: remove described dummy grid.
7. form method as claimed in claim 1, it is characterized in that, the material of described boundary layer is silicon dioxide or nitrogenous silicon dioxide, and thickness range is
8. form method as claimed in claim 1, it is characterized in that, the material of described high-K gate dielectric layer is one or more in hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminium oxide, and thickness range is
9. form method as claimed in claim 1, it is characterized in that, the material of described cap layer is one or more in titanium nitride, nitrogenize thallium and tungsten nitride, and thickness range is
10. form method as claimed in claim 1, it is characterized in that, described semiconductor substrate surface has oxide layer, before forming boundary layer on the semiconductor substrate, also comprises step: remove described oxide layer until expose described semiconductor substrate surface.
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| US20060166447A1 (en) * | 2004-09-07 | 2006-07-27 | Doczy Mark L | Method for making a semiconductor device having a high-k gate dielectric |
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Application publication date: 20150603 |