CN101777917B - Pipeline analog-to-digital converter and quick calibration method of capacitance mismatch thereof - Google Patents
Pipeline analog-to-digital converter and quick calibration method of capacitance mismatch thereof Download PDFInfo
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Abstract
The invention relates to a pipeline analog-to-digital converter and a quick calibration method of capacitance mismatch thereof. The quick calibration method is characterized by carrying out inverted order calibration from a level circuit module of the last level. The calibration method of the level circuit module of each level comprises the following steps of: 1. starting calibration: closing the second transfer switch and the fourth transfer switch and cutting off the first transfer switch and the third transfer switch to enable the level circuit modules to work in the calibration state; 2. measuring quantitative results: setting input signals for the level circuit modules, and carrying out analog-to-digital conversion by the level circuit modules following the corresponding level and the back analog-to-digital conversion module of the pipeline analog-to-digital converter to obtain a set of corresponding quantitative results; and 3. measuring quantitative step length: subtracting the corresponding quantitative results to obtain the actual quantitative step length of the level circuit modules and storing the step length in a storage module. Roughly quantitative calibration results are added by the invention, thereby improving the linearity of the transmission function of the pipeline analog-to-digital converter and increasing the significant digit of analog-to-digital conversion.
Description
Technical field
The present invention relates to a kind of analog to digital converter and calibration steps thereof, particularly the quick calibration method of a kind of production line analog-digital converter and capacitance mismatch thereof.
Background technology
See also shown in Figure 1, existing production line analog-digital converter keeps the analog signal sampling of 100 pairs of inputs of module by the sampling that is provided with, some grades of circuit modules 200 and rear analog-to-digital conversion module 300 by series connection carry out analog-to-digital quantification, and the quantized result at different levels that obtain are by numeral dislocation summation module 400 weighting summation output digit signals.
See also shown in Figure 2ly, each grade circuit module 200 is subjected to the non-overlapping clock control of two-phase.When phase place 1, the analog signal sampling of 230 pairs of this grade inputs of level circuit sampling module, 210 pairs of these signals of analog-to-digital conversion module are converted to thick quantized result D
OutWhen phase place 2, D/A converter module 220 changes into thick quantized analog signal again with thick quantized result; Then level circuit sampling module 230 deducts thick quantized analog signal from input signal, and will proceed thick quantification to next stage after the subtraction result amplification.Every one-level level circuit module 200 is all as sampling, slightly quantize, subtract each other amplification as the streamline.The thick quantized result of each grade circuit module 200 also outputs to numeral dislocation summation module 400.
See also switched-capacitor circuit shown in Figure 3, by with analog-to-digital conversion module 210 mating reactions, jointly realized Fig. 2 middle rank circuit module 200 sampling, slightly quantize, subtract each other the process of amplification.When phase place 1,1 switch conduction, 2 switches open circuit, C
S1To C
SNTo input voltage V
InSampling; Analog-to-digital conversion module 210 total N level decision level V
REF1To V
REFN, to input voltage V
InSlightly quantize; When phase place 2,2 switch conductions, 1 switch open circuit is by the thick quantized result decision C of analog-to-digital conversion module 210
S1To C
SNWhat connect is that reference voltage is+V
RStill-V
R, this has realized the function of D/A converter module 220 among Fig. 2.
Please cooperate referring to Fig. 4 and shown in Figure 5, if the electric capacity in the above-mentioned switched-capacitor circuit all is ideal value, be accessed the desirable transfer function of level circuit module 200 as shown in phantom in Figure 4 by charge conservation formula transformation energy.Suppose that at different levels grades of circuit modules 200 all are desirable analog to digital converters, so wherein the analog signal surplus V of every grade of output
OutCarry out the quantized result that analog-to-digital conversion obtains by level circuit module 200 and rear analog-to-digital conversion module 210 after this grade, with the thick quantized result D of this grade
OutWeighting summation obtains the complete transmission function of grade circuit module 200.Ideally, this complete transfer function (V
Out+ D
Out) should be the fixing straight line of a slope as shown in phantom in Figure 5, by each decision level V
REFAdd ideal quantized step-length V
STEP_IDEALBe Δ D
Out=1 weight obtains.
But in actual conditions, there is mismatch in the electric capacity of switched-capacitor circuit, comprises systematic error (parasitic capacitance that has mismatch when domain is realized) and random error (during design the electric capacity of formed objects make not be equal).The mismatch of electric capacity can cause the variation of transfer function gain and the variation (this also is called the digital-to-analogue conversion noise) of zero crossing, so transfer function and the complete transmission function of actual level circuit module 200 are shown in solid line among Fig. 4 and Fig. 5.Because the existence of digital-to-analogue conversion noise is so that desirable Δ D
Out=1 weight is not equal to actual weight, i.e. ideal quantized step-length V
STEP_IDEALAnd be not equal to V
REFThe actual quantization step-length V at place
STEP_REALTherefore in Fig. 4, show as the inconsistent of straight slope, and in Fig. 5 complete transfer function at V
REFGo out to have produced " jump ".
The mismatch of electric capacity can limit the linearity and the number of significant digit of production line analog-digital converter.The matching precision of electric capacity is not less than 0.1% usually, and the precision of not doing the production line analog-digital converter of any calibration is limited in 10 to 12.
Existing calibration steps for capacitance mismatch by adding random perturbation, uses related algorithm to estimate the size of capacitance mismatch, deducts the error that mismatch causes again.But the alignment time of this calibration steps is long, and can be along with the increase of number of significant digit, and the alignment time can prolong with index.
Summary of the invention
The object of the present invention is to provide the quick calibration method of a kind of production line analog-digital converter and capacitance mismatch thereof, can improve the linearity of production line analog-digital converter transfer function, reduce the alignment time of production line analog-digital converter, increase analog-to-digital number of significant digit.
In order to achieve the above object, technical scheme of the present invention provides a kind of production line analog-digital converter, some grades of circuit modules and rear analog-to-digital conversion module by series connection carry out analog-to-digital conversion to analog signal, the as a result weighting summation output digit signals that will be changed by numeral dislocation summation module;
Above-mentioned each grade circuit module comprises cascade analog input port, level circuit sampling module, subtracter block, the gain amplification module that connects successively, the analog-to-digital conversion module that is connected with above-mentioned cascade analog input port also is connected with above-mentioned subtracter block by D/A converter module, it is characterized in that:
Above-mentioned level circuit module also comprises given analog input port, given digital input port, the first to the 4th diverter switch, memory module;
Above-mentioned cascade analog input port first diverter switch of connecting is connected with the positive input terminal of above-mentioned subtracter block by above-mentioned level circuit sampling module;
Above-mentioned cascade analog input port, the first diverter switch also are connected with the negative input end of above-mentioned subtracter block by analog-to-digital conversion module, the 3rd diverter switch, the D/A converter module of connecting successively;
Above-mentioned subtracter block will deduct the thick quantized analog signal of above-mentioned D/A converter module output from the analog signal of above-mentioned level circuit sampling module input, and will be sent to above-mentioned gain amplification module;
Analog signal surplus after above-mentioned gain amplification module output is amplified is to the level circuit module of next stage;
Above-mentioned given analog input port second diverter switch of connecting is connected with above-mentioned level circuit sampling module, analog-to-digital conversion module respectively;
Above-mentioned analog-to-digital conversion module is connected with above-mentioned memory module, exports thick quantized result and controls the thick calibration result that quantizes of above-mentioned memory module output to the numeral dislocation summation module of above-mentioned production line analog-digital converter;
Above-mentioned given digital input port is connected with above-mentioned D/A converter module by the 4th diverter switch.
A kind of quick calibration method of capacitance mismatch of production line analog-digital converter is characterized in that, begins inverted order calibration from afterbody level circuit module, comprises following steps for the calibration of every one-level level circuit module:
The second diverter switch, the 4th diverter switch closure, the first diverter switch, the 3rd diverter switch disconnect, and make a grade circuit module be operated in align mode;
Be the given input signal of level circuit module, carry out analog-to-digital conversion by the level circuit module after this grade and the rear analog-to-digital conversion module of above-mentioned production line analog-digital converter, obtain one group of corresponding quantized result;
Corresponding quantized result is subtracted each other the actual quantization step-length that obtains about the level circuit module, and it is kept in the memory module.
Above-mentioned steps 2 also comprises following steps:
Step 2.1 signal feeding
The simulate given signal of inputting for the given analog input port of level circuit module is decision level, is that the digital given unit signal that its given digital input port is inputted is given quantized result;
The output of this grade of step 2.2 surplus
The simulate given signal of input stage circuit module deducts the thick quantized analog signal that the digital given unit signal obtains through digital-to-analogue conversion behind over-sampling, after amplifying through gain, export the analog signal surplus of this grade level circuit module;
The output of step 2.3 rear class surplus
The analog signal surplus of level circuit module is slightly quantized successively the analog signal surplus of every one-level after obtaining by all grades circuit module after this grade;
The rear analog-to-digital conversion of step 2.4
By the analog signal surplus of afterbody level circuit module output, through after analog-to-digital conversion module carry out analog-to-digital conversion and obtain quantized result;
Above-mentioned steps 2.1 also comprises following steps:
Step 2.1.1 is one group of decision level for the simulate given signal of the given analog input port input of level circuit module, and the digital given unit signal of inputting for its given digital input port is one group of given quantized result i (wherein i increases progressively from 1 to N);
Step 2.1.2 is above-mentioned one group of decision level for the simulate given signal of the given analog input port input of level circuit module, and the digital given unit signal of inputting for its given digital input port is one group of given quantized result i+1 (wherein i increases progressively from 1 to N).
Slightly quantize at every one-level level circuit module in the above-mentioned steps 2.3, also comprise following steps:
The analog signal surplus of the given analog input port input upper level of step 2.3.1 level circuit module obtains thick quantized result through analog-to-digital conversion;
Step 2.3.2 is by thick quantized result
The thick quantification calibration result of corresponding this grade level circuit module in the control output storage array, and be sent to given digital input port;
Step 2.3.3 slightly quantizes calibration result and obtains thick quantized analog signal through digital-to-analogue conversion, and sends to the negative input end of subtracter block;
The analog signal surplus of the upper level of the given analog input port input of step 2.3.4 sends to the positive input terminal of subtracter block through level circuit sampling module;
Step 2.3.5 upper level analog signal surplus deducts thick quantized analog signal, after amplifying through gain, exports the analog signal surplus of this grade;
Above-mentioned steps 2.4 also comprises following steps:
Step 2.4.1 is level circuit module input above-mentioned given signal in step 2.1.1, be that given analog input port is inputted one group of decision level, given digital input port is inputted one group of given quantized result i (wherein i increases progressively from 1 to N), and the one group of quantized result that obtains by the level circuit module after this grade and rear analog-to-digital conversion module successively is the first quantized result;
Step 2.4.2 is level circuit module input above-mentioned given signal in step 2.1.2, be that given analog input port is inputted one group of decision level, for its given digital input port is inputted one group of given quantized result i+1 (wherein i increases progressively from 1 to N), obtain one group of second quantized result by level circuit module and rear analog-to-digital conversion module after this grade successively.
The thick quantification calibration result of above-mentioned every one-level level circuit module output has kept some redundant digits.
The quick calibration method of a kind of production line analog-digital converter provided by the invention and capacitance mismatch thereof, compared with prior art, its advantage is: the present invention has reduced the time of calibration because some grades of circuit modules that arrange are carried out the inverted order calibration;
The present invention outputs to numeral dislocation summation module owing to will slightly quantize calibration result at every one-level level circuit module, what be weighted addition is slightly to quantize the corresponding actual quantization step-length of calibration result, so in level circuit module transfer function, " jump " that the digital-to-analogue conversion noise causes has been eliminated, improve the linearity of production line analog-digital converter transfer function, increased analog-to-digital number of significant digit.
Description of drawings
Fig. 1 is the general structure schematic diagram of prior art production line analog-digital converter;
Fig. 2 is the structural representation of the level circuit module of prior art production line analog-digital converter;
Fig. 3 is the circuit theory diagrams of the level circuit module of prior art production line analog-digital converter;
Fig. 4 is the transfer function schematic diagram of the level circuit module of prior art production line analog-digital converter;
Fig. 5 is the complete transmission function schematic diagram of the level circuit module of prior art production line analog-digital converter;
Fig. 6 is the structural representation of the level circuit module of production line analog-digital converter of the present invention;
Fig. 7 is the transfer function schematic diagram of level circuit module of the present invention;
Fig. 8 is the complete transmission function schematic diagram of level circuit module of the present invention;
Fig. 9 is the general structure schematic diagram of production line analog-digital converter of the present invention;
Figure 10 is the static non linear error schematic diagram before the production line analog-digital converter calibration of the present invention;
Figure 11 is the static non linear error schematic diagram after the production line analog-digital converter calibration of the present invention;
Figure 12 is the kinematic nonlinearity error schematic diagram before the production line analog-digital converter calibration of the present invention;
Figure 13 is the kinematic nonlinearity error schematic diagram after the production line analog-digital converter calibration of the present invention.
Embodiment
Below in conjunction with description of drawings the specific embodiment of the present invention.
See also shown in Figure 9, the quick calibration method of a kind of production line analog-digital converter provided by the invention and capacitance mismatch thereof, relate to a kind of production line analog-digital converter, keep module to the sampling of input analog signal by sampling, some grades of circuit modules 20 and rear analog-to-digital conversion module 30 by series connection carry out analog-to-digital quantification, quantized result at different levels is passed through numeral dislocation summation module 40 weighting summations, and by redundant processing module 50 output digit signals.This production line analog-digital converter improves the some grades of circuit modules 20 that existing production line analog-digital converter is provided with.
See also shown in Figure 6ly, each grade circuit module 20 comprises 3 input ports, 4 diverter switch sw1 to sw4, level circuit sampling module 23, subtracter block 24, gain amplification module 25, analog-to-digital conversion module 21, D/A converter module 22, memory module 26 among the present invention.
Input port comprises cascade analog input port V
InWith given analog input port Forced V
In, given digital input port Forced D
In
Cascade analog input port V
InAfter the first diverter switch sw1 connects, be connected with level circuit sampling module 23, analog-to-digital conversion module 21 respectively; Given analog input port Forced V
InAfter the second diverter switch sw2 connects, also be connected with level circuit sampling module 23, analog-to-digital conversion module 21 respectively.In normal operation, the first diverter switch sw1 is closed, the second diverter switch sw2 disconnects, with the simulation primary signal of upper level level circuit module 20 outputs by cascade analog input port V
InBe transferred to a grade circuit sampling module 23, analog-to-digital conversion module 21.Under align mode, the second diverter switch sw2 is closed, the first diverter switch sw1 disconnects the simulate given signal by given analog input port Forced V
InBe transferred to a grade circuit sampling module 23, analog-to-digital conversion module 21.
Analog-to-digital conversion module 21 is flash type (Flash) analog to digital converters.Analog-to-digital conversion module 21 will simulate primary signal from the higher level of input port input or the simulate given signal converts thick quantized result D at the corresponding levels to
Out, and send to memory module 26; Analog-to-digital conversion module 21 also can be by the 3rd diverter switch sw3 control of series connection, with the thick quantized result D after the conversion
OutSend to D/A converter module 22.
Given digital input port Forced D
InThe 4th diverter switch sw4 by series connection is connected with D/A converter module 22.By the 3rd diverter switch sw3, the 4th diverter switch sw4 control, select the at the corresponding levels thick quantized result D after the D/A converter module 22 input analog-to-digital conversion
Out, or by given digital input port Forced D
InThe given signal of input digit.Thick quantized analog signal after D/A converter module 22 will be changed sends to the negative input port of subtracter block 24.
Input and the cascade analog input port V of level circuit sampling module 23
In, given analog input port Forced V
InConnect, simulation primary signal or the simulate given signal of the upper level of input are sampled by the first diverter switch sw1, the second diverter switch sw2 control, and send to the positive input terminal of subtracter block 24.
Subtracter block 24 will deduct from the signal of level circuit sampling module 23 outputs the thick quantized analog signal of D/A converter module 22 outputs, and by after 25 amplifications of gain amplification module, obtain analog signal surplus V
OutBe sent to next stage level circuit module 20.
The quick calibration method of a kind of production line analog-digital converter provided by the invention and capacitance mismatch thereof, owing to there not being switched-capacitor circuit, rear analog-to-digital conversion module 30 does not need the calibration capacitance mismatch, since the calibration of N level level circuit inverted order, comprises following steps:
The second diverter switch sw2, the 4th diverter switch sw4 closure, the first diverter switch sw1, the 3rd diverter switch sw3 disconnect, and make grade circuit module 20 be operated in align mode;
Step 2.1 signal feeding
(following j successively decreases from N to 1)
The interval changes simulate given signal, the digital given unit signal that is input to j level level circuit module 20, and is as shown in table 1 below.Be the given analog input port Forced V of j level level circuit module 20
InThe simulate given signal of input is decision level V
REF1To V
REFN, be its given digital input port Forced D
InThe digital given unit signal of input is given quantized result 1 to N+1.
Step 2.1.1 makes Forced V to j level level circuit module 20 input decision level, given quantized result
In=V
REF (i), Forced D
In=i (wherein i increases progressively from 1 to N);
Step 2.1.2 makes ForcedV to j level level circuit module 20 input decision level, given quantized result
In=V
REF (i), Forced D
In=i+1 (wherein i increases progressively from 1 to N);
| DL | Forced V in | Forced D in |
| DL STEP1A | V REF1 | 1 |
| DL STEP1B | V REF1 | 2 |
| DL STEP2A | V REF2 | 2 |
| DL STEP2B | V REF2 | 3 |
| …… | …… | …… |
| DL STEP(N-1)A | V REF(N-1) | N-1 |
| D LSTEP(N-1)B | V REF(N-1) | N |
| DL STEPNA | V REFN | N |
| DL STEPNB | V REFN | N+1 |
The given input signal of table 1 grade circuit module and output quantization result's the table of comparisons;
Step 2.2 surplus output at the corresponding levels
The given digital input port Forced D of step 2.2.1 j level level circuit module 20
InThe digital given unit signal of input is converted to thick quantized analog signal through D/A converter module 22, and sends to the negative input end of subtracter block 24;
The given analog input port Forced V of step 2.2.2 j level level circuit module 20
InThe simulate given signal of input sends to the positive input terminal of subtracter block 24 through level circuit sampling module 23;
Step 2.2.3 simulate given signal deducts thick quantized analog signal, after amplifying through gain, and outputting analog signal surplus V
Out (j)
The output of step 2.3 rear class surplus
Slightly quantized to N level level circuit module 20 by the j+1 level successively, all comprise following steps for every one-level level circuit module 20 wherein:
The given analog input port of step 2.3.1 Forced V
InThe analog signal surplus of input upper level obtains thick quantized result D through analog-to-digital conversion
Out
Step 2.3.2 is by thick quantized result D
OutThe thick quantification calibration result ROM (D of j+1 level level circuit module 20 in the control output storage array
Out)
(j+1), and be sent to given digital input port Forced D
In
Step 2.3.3 slightly quantizes calibration result ROM (D
Out)
(j+1)Obtain thick quantized analog signal through digital-to-analogue conversion, and send to the negative input end of subtracter block 24;
The given analog input port of step 2.3.4 Forced V
InThe analog signal surplus V of the upper level of input
Out (j)Send to the positive input terminal of subtracter block 24 through level circuit sampling module 23;
Step 2.3.5 upper level analog signal surplus deducts thick quantized analog signal, after amplifying through gain, and outputting analog signal surplus V
Out (j+1)
The rear analog-to-digital conversion of step 2.4
By the analog signal surplus V of j+1 level to 20 outputs of N level level circuit module
Out, through after analog-to-digital conversion module 30 carry out analog-to-digital conversion and obtain quantized result DL;
Among step 2.4.1 such as the step 2.1.1, to j level level circuit module 20 input ForcedV
In=V
REF (i), Forced D
In=i carries out analog-to-digital conversion by the level circuit module 20 (namely from j+1 level level circuit module 20 to N level level circuit module 20) after at the corresponding levels and rear analog-to-digital conversion module 30 successively and obtains one group of first quantized result DL
STEP (i) A
Among step 2.4.2 such as the step 2.1.2, to j level level circuit module 20 input Forced V
In=V
REF (i), Forced D
In=i+1 carries out analog-to-digital conversion by the level circuit module 20 (namely from j+1 level level circuit module 20 to N level level circuit module 20) after at the corresponding levels and rear analog-to-digital conversion module 30 successively and obtains one group of second quantized result DL
STEP (i) B
With the first corresponding quantized result DL
STEP (i) AWith the second quantized result DL
STEP (i) BSubtract each other the one group of actual quantization step-length V that obtains about j level level circuit module 20
STEP_REAL (i), i.e. V
STEP_REAL (i)=DL
STEP (i) A-DL
STEP (i) B, and it is kept in the memory module 26, during for the level circuit module 20 of calibration prime and normal operation.
In above-mentioned steps 2.3.2, when j level level circuit module 20 is calibrated, owing to the level circuit module 20 (namely from j+1 level level circuit module 20 to N level level circuit module 20) after it was carried out calibration, suppose that a level circuit module 20 afterwards at the corresponding levels all is desirable analog to digital converter, therefore need to get thick quantification calibration result ROM (D
Out) be input to given digital input port Forced D
In, guarantee the calibration effect of level circuit module 20 at the corresponding levels.
Because the non-ideal factor that exists in the production line analog-digital converter, grade circuit module 20 after can affecting after analog-to-digital conversion module 30 and the corresponding levels is as the hypothesis of ideal mode number converter, so the thick quantification calibration result of every one-level level circuit module 20 outputs has kept some redundant digits to guarantee to calibrate effect.
The numeral dislocation summation module of production line analog-digital converter is with the thick quantification calibration result ROM (D of every one-level level circuit module 20 outputs
Out) and the quantized result DL of the rear analog-to-digital conversion module 30 output addition that misplaces, and after having omitted redundant digit, the analog-to-digital conversion result of viewing pipeline analog to digital converter.
As the step 2.2 of above-mentioned align mode in the level circuit module 20 before the corresponding levels is calibrated or during in normal operating conditions, as shown in table 2 below, level circuit module 20 is by thick quantized result D
OutControl is from the corresponding thick quantification calibration result ROM (D of memory module 26 outputs
Out); If the thick quantized result D of level circuit module 20
Out=1, then read ROM (1)=0 as the thick calibration result that quantizes from memory module 26; If thick quantized result D
Out=2, then read ROM (2)=V
STEP_REAL1As thick quantification calibration result; The like, if the D of this level
Out=N+1 then reads ROM (N+1)=V
STEP_REAL1+ V
STEP_REAL2+ ... V
STEP_REALNAs thick quantification calibration result output.
| D out | ROM(D out) |
| 1 | 0 |
| 2 | V STEP_REAL1 |
| 3 | V STEP_REAL1+V STEP_REAL2 |
| …… | …… |
| N+1 | V STEP_REAL1+V STEP_REAL2+…V STEP_REALN |
The thick quantized result of table 2 grade circuit module and the thick table of comparisons that quantizes calibration result;
Please cooperate referring to Fig. 6, Fig. 7 and shown in Figure 8, be in normal operating conditions at production line analog-digital converter, during i.e. the first diverter switch sw1, the 3rd diverter switch sw3 closure, the second diverter switch sw2, the 4th diverter switch sw4 disconnection, the simulation primary signal is carried out analog-to-digital conversion by at different levels grades of circuit modules 20 and rear analog-to-digital conversion module 30 successively; Because every one-level level circuit module 20 all will slightly quantize calibration result ROM (D
Out) rather than thick quantized result D
OutOutput to numeral dislocation summation module, so what be weighted addition is slightly to quantize calibration result ROM (D
Out) corresponding actual quantization step-length V
STEP_REAL, rather than thick quantized result D
OutCorresponding ideal quantized step-length V
STEP_IDEALSo in level circuit module 20 transfer functions, " jump " that the digital-to-analogue conversion noise causes has been eliminated, the linearity of the complete transmission function of production line analog-digital converter can not be affected.
See also shown in Figure 9, below take the production line analog-digital converter of 16 outputs as example, by software MATLAB emulation, illustrate that the present invention is for the calibration effect of capacitance mismatch in the production line analog-digital converter.
Setting production line analog-digital converter has 6 level circuit modules 20, wherein first three grade circuit module 20 each be 17 grades of quantized result, gain is 8, exports 5 bit digital value; Each is 9 grades of quantized result for rear three level circuit modules 20, and gain is 4, exports 4 bit digital value; Rear analog-to-digital conversion module 30 is 33 grades of quantized result, exports 6 bit digital value.The output figure place of each grade circuit obtains 20 bit digital value after through the dislocation addition, during calibration and normal operation all be to use 20, but finally export 16 bit digital value, omit last 4 redundant digits.In the emulation, except capacitance mismatch, some other non-ideal factor such as comparator imbalance, amplifier finite gain are all taken into account, and the result after the viewing pipeline analog to digital converter is not calibrated and calibrated simultaneously as a comparison.
Please cooperate referring to Figure 10 to shown in Figure 13, be respectively static non linear error and the kinematic nonlinearity error after production line analog-digital converter is not calibrated and calibrated, and is summarized in the following table 3.Wherein Figure 10 and Figure 11 are the static non linear errors of production line analog-digital converter, and maximum DNL (DNL) and maximum INL (integral nonlinearity) are 3.20LSB and 2921LSB before the calibration, exist to lose code and nonmonotonicity; Maximum DNL (DNL) and maximum INL (integral nonlinearity) reduce to 0.14LSB and 0.31LSB after the calibration, eliminate and lose code and bonding tonality.
Figure 12 and Figure 13 are the kinematic nonlinearity errors of production line analog-digital converter, it is the sinusoidal wave spectrum analysis through output after production line analog-digital converter quantizes after production line analog-digital converter before the calibration and the calibration of a unifrequency, 1st represents fundamental signal among the figure, 2nd, 3rd ... the distortion of expression high-order harmonic wave.The SFDR ratio of maximum harmonic distortion (signal with) was 55.24dB before calibration, became 115.5dB after the calibration, had improved approximately 60dB; From 8.3 bit recoveries to the inviscid flow pipeline analog-to-digital converter 16 of the ENOB (number of significant digit) that the SINAD ratio of harmonic distortion and noise (signal with) characterizes.Significantly improving on the Static and dynamic performance suffices to show that calibration steps of the present invention is for the validity of capacitance mismatch.
| Original output | Calibration output | |
| DNL (DNL)/LSB | 3.20 | 0.14 |
| INL (integral nonlinearity)/LSB | 2921 | 0.31 |
| The FFT SINAD/dB ratio of harmonic distortion and noise (signal with) | 51.90 | 98.98 |
| FFT ENOB (number of significant digit)/bit | 8.32 | 15.98 |
| FFT SNR (signal to noise ratio)/dB | 58.59 | 98.07 |
| The FFT SFDR/dB ratio of maximum harmonic distortion (signal with) | 55.24 | 115.5 |
Table 3 is calibration front and back error comparison sheets of production line analog-digital converter of the present invention;
It is (16+16+16+8+8+8) * 2=144 ≈ 2^7 that the production line analog-digital converter required time of calibration counts, on average get 2^10 time to eliminate the impact of thermal noise at each point in addition, overall or only need approximately 2^17 cycle, far below existing calibration steps need to 2^27 cycle.And along with the increase of number of significant digit, the alignment time of the present invention is linear growth, far below the exponential growth of existing calibration steps.
Although content of the present invention has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple modification of the present invention with to substitute all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (7)
1. production line analog-digital converter, some grades of circuit modules (20) and rear analog-to-digital conversion module (30) by series connection carry out analog-to-digital conversion to analog signal, by the numeral as a result weighting summation output digit signals that summation module (40) will change that misplaces;
Described each grade circuit module (20) comprises cascade analog input port, level circuit sampling module (23), subtracter block (24), the gain amplification module (25) that connects successively, the analog-to-digital conversion module (21) that is connected with described cascade analog input port also is connected with described subtracter block by D/A converter module (22), it is characterized in that:
Described level circuit module (20) also comprises given analog input port, given digital input port, the first to the 4th diverter switch, memory module (26)
Described cascade analog input port first diverter switch of connecting is connected with the positive input terminal of described subtracter block (24) by described level circuit sampling module (23);
Described cascade analog input port, the first diverter switch also are connected with the negative input end of described subtracter block (24) by analog-to-digital conversion module (21), the 3rd diverter switch, the D/A converter module (22) of connecting successively;
Described subtracter block (24) will deduct the thick quantized analog signal of described D/A converter module (22) output from the analog signal of described level circuit sampling module (23) input, and will be sent to described gain amplification module (25);
Analog signal surplus after described gain amplification module (25) output is amplified is to the level circuit module (20) of next stage;
Described given analog input port second diverter switch of connecting is connected with described level circuit sampling module (23), analog-to-digital conversion module (21) respectively;
Described analog-to-digital conversion module (21) is connected with described memory module (26), exports thick quantized result and controls the thick calibration result that quantizes of described memory module (26) output to the numeral dislocation summation module (40) of described production line analog-digital converter;
Described given digital input port is connected with described D/A converter module (22) by the 4th diverter switch.
2. quick calibration method that is used for the capacitance mismatch of production line analog-digital converter as claimed in claim 1, it is characterized in that, from the calibration of afterbody level circuit module (20) beginning inverted order, comprise following steps for the calibration of every one-level level circuit module (20):
Step 1 calibration is opened
The second diverter switch, the 4th diverter switch closure, the first diverter switch, the 3rd diverter switch disconnect, and make a grade circuit module (20) be operated in align mode;
Step 2 quantized result is measured
Be the given input signal of level circuit module (20), carry out analog-to-digital conversion by the level circuit module (20) after this grade and the rear analog-to-digital conversion module (30) of described production line analog-digital converter, obtain one group of corresponding quantized result;
Step 3 quantization step is measured
Corresponding quantized result is subtracted each other the actual quantization step-length that obtains about level circuit module (20), and it is kept in the memory module (26).
3. the quick calibration method of the capacitance mismatch of production line analog-digital converter as claimed in claim 2 is characterized in that, described step 2 also comprises following steps:
Step 2.1 signal feeding
The simulate given signal of inputting for the given analog input port of level circuit module (20) is decision level, is that the digital given unit signal that its given digital input port is inputted is given quantized result;
The output of this grade of step 2.2 surplus
The simulate given signal of input stage circuit module (20) deducts the thick quantized analog signal that the digital given unit signal obtains through digital-to-analogue conversion behind over-sampling, after amplifying through gain, export the analog signal surplus of this grade level circuit module (20);
The output of step 2.3 rear class surplus
The analog signal surplus of level circuit module (20) is slightly quantized successively the analog signal surplus of every one-level after obtaining by all grades circuit module (20) after this grade;
The rear analog-to-digital conversion of step 2.4
By the analog signal surplus of afterbody level circuit module (20) output, through after analog-to-digital conversion module (30) carry out analog-to-digital conversion and obtain quantized result.
4. the quick calibration method of the capacitance mismatch of production line analog-digital converter as claimed in claim 3 is characterized in that, described step 2.1 also comprises following steps:
Step 2.1.1 is one group of decision level for the simulate given signal of the given analog input port input of level circuit module (20), and the digital given unit signal of inputting for its given digital input port is one group of given quantized result i, and wherein i increases progressively from 1 to N;
Step 2.1.2 is above-mentioned one group of decision level for the simulate given signal of the given analog input port input of level circuit module (20), the digital given unit signal of inputting for its given digital input port is one group of given quantized result i+1, and wherein i increases progressively from 1 to N.
5. the quick calibration method of the capacitance mismatch of production line analog-digital converter as claimed in claim 3 is characterized in that, slightly quantizes at every one-level level circuit module (20) in the described step 2.3, also comprises following steps:
The analog signal surplus of the given analog input port input upper level of step 2.3.1 level circuit module (20) obtains thick quantized result through analog-to-digital conversion;
Step 2.3.2 exports the thick quantification calibration result of this grade level circuit module (20) corresponding in the storage array by thick quantized result control, and is sent to given digital input port;
Step 2.3.3 slightly quantizes calibration result and obtains thick quantized analog signal through digital-to-analogue conversion, and sends to the negative input end of subtracter block (24);
The analog signal surplus of the upper level of the given analog input port input of step 2.3.4 sends to the positive input terminal of subtracter block (24) through level circuit sampling module (23);
Step 2.3.5 upper level analog signal surplus deducts thick quantized analog signal, after amplifying through gain, exports the analog signal surplus of this grade.
6. the quick calibration method of the capacitance mismatch of production line analog-digital converter as claimed in claim 4 is characterized in that, described step 2.4 also comprises following steps:
Step 2.4.1 is that level circuit module (20) input is at given signal described in the step 2.1.1, be that given analog input port is inputted one group of decision level, given digital input port is inputted one group of given quantized result i, wherein, i increases progressively from 1 to N, and the one group of quantized result that obtains by the level circuit module (20) after this grade and rear analog-to-digital conversion module (30) successively is the first quantized result;
Step 2.4.2 is that level circuit module (20) input is at given signal described in the step 2.1.2, be that given analog input port is inputted one group of decision level, for its given digital input port is inputted one group of given quantized result i+1, wherein, i increases progressively from 1 to N, obtains one group of second quantized result by level circuit module (20) and rear analog-to-digital conversion module (30) after this grade successively.
7. the quick calibration method of production line analog-digital converter as claimed in claim 5 and capacitance mismatch thereof is characterized in that, the thick quantification calibration result of described every one-level level circuit module (20) output has kept some redundant digits.
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