CN116455395B - Successive approximation type analog-to-digital converter circuit, analog-to-digital converter, and electronic apparatus - Google Patents

Abstract

The invention provides a pipelined successive approximation type analog-to-digital converter circuit, an analog-to-digital converter and electronic equipment, and relates to the technical field of integrated circuits, comprising: the coarse quantization SAR module is used for performing approximation quantization on the fully-differential input voltage obtained by sampling to obtain a coarse quantization result, generating two paths of output currents corresponding to the fully-differential input voltage, and outputting the two paths of output currents to the residual quantization SAR module; the residual quantization SAR module is used for performing successive approximation quantization on the residual voltage to obtain a residual quantization result. The invention reduces the problem that the sampling speed cannot be raised because the quantization of the full bit is required to be carried out in the same quantization period in the traditional high-precision SAR-ADC. The problem that error codes and comparison misjudgment are caused by incomplete signal establishment is solved; the problem of overhigh power consumption caused by overlarge capacitance value of the capacitors in the capacitor array in the traditional high-precision SAR-ADC is solved, and meanwhile, the probability of precision reduction caused by process production mismatch is reduced due to the reduction of the number of the capacitors.

Description

Successive approximation analog-to-digital conversion circuits, analog-to-digital converters and electronic equipment

Technical field

The invention relates to the technical field of integrated circuits, in particular to a pipeline-type successive approximation analog-to-digital conversion circuit, an analog-to-digital converter and electronic equipment.

Background technique

Currently, traditional high-precision SAR-ADCs need to quantize all bits within the same quantization cycle. Due to the small time margin of a single comparison cycle, the signal is incompletely established, resulting in bit errors, comparison misjudgments, and the failure to increase the sampling speed.

Moreover, in medium and high-speed SAR-ADCs, due to problems such as signal establishment accuracy, bandwidth, noise, and too large capacitance values in the capacitor array, their power consumption is high, and at the same time, the accuracy is reduced due to process mismatch. Probability.

Contents of the invention

In view of the above problems, the present invention proposes a pipelined successive approximation analog-to-digital conversion circuit, an analog-to-digital converter and an electronic device.

Embodiments of the present invention provide a pipelined successive approximation analog-to-digital conversion circuit. The successive approximation analog-to-digital conversion circuit includes: a coarse quantization SAR module and a residual quantization SAR module;

In the coarse quantization stage, the coarse quantization SAR module is used to approximate and quantize the sampled fully differential input voltage, obtain a coarse quantization result, and generate two output currents corresponding to the fully differential input voltage, and output them to the Residual quantization SAR module;

The residual quantization SAR module includes: a residual quantization capacitor array, a residual quantization logic unit and a comparator;

In the residual quantization stage, the residual quantized capacitor array is used to integrate the two output currents to obtain two residual quantized integrated voltages and output them to the comparator, and is used to quantize the capacitor array switch according to the residual In the case of on-off, successive approximation quantization is performed to obtain the residual quantization result;

The comparator is used to compare the magnitudes of two residual quantization integrated voltages, and output a first result signal to the residual quantization logic unit;

The residual quantization logic unit is configured to generate a residual quantization control signal according to the first result signal, and then control the on/off of the residual quantization capacitor array switch;

Wherein, in the current coarse quantization cycle, the coarse quantization SAR module completes the coarse quantization of the fully differential input voltage, and at the same time, the residual quantization SAR module completes the residual quantization of the residual voltage of the previous coarse quantization cycle. quantification;

The capacitance of the integrating capacitor in the coarse quantization SAR module is much smaller than the capacitance of the capacitor in the residual quantization capacitor array.

Optionally, the coarse quantization SAR module includes: a capacitive fully differential SAR ADC structure, a voltage-to-current amplification unit, a coarse quantization logic unit, a judgment latch unit, and a coarse quantization integration unit;

In the coarse quantization stage, the capacitive fully differential SAR ADC structure is used to integrate the fully differential input voltage to obtain the positive input terminal voltage and the negative input terminal voltage, and output them to the voltage-to-current amplification unit respectively. The positive and negative input terminals are used to perform successive approximation quantization according to the on-off status of the capacitor array switch in the capacitive fully differential SAR ADC structure to obtain the coarse quantization result;

The voltage-to-current amplification unit is used to convert and amplify the positive input terminal voltage and the negative input terminal voltage into corresponding two output currents, and output them to the coarse quantization integration unit and the residual quantization SAR module;

The coarse quantization integration unit is used to integrate the two output currents to obtain two integrated voltages and output them to the judgment latch unit;

The judgment latch unit is used to compare the magnitudes of two coarse quantization integrated voltages and output a second result signal to the coarse quantization logic unit;

The coarse quantization logic unit is used to generate a coarse quantization control signal according to the second result signal, and then control the on and off of the capacitor array switch in the capacitive fully differential SAR ADC structure.

Optionally, the residual quantization capacitor array includes: a first half unit and a second half unit;

The first half unit receives a first output current among two output currents, and the second half unit receives a second output current among two output currents;

The first half unit includes: a first residual quantization capacitor array, a second residual quantization capacitor array, a first switch, a second switch, a third switch, a fourth switch, and a first reset switch;

The first end of the first switch receives the first output current, and the second end is connected to the second end of the first reset switch, the upper plate of the first residual quantization capacitor array, and the second The upper plate of the residual quantization capacitor array and the positive input end of the comparator are connected respectively;

The first end of the first reset switch is connected to the lower plate of the first residual quantization capacitor array and grounded;

The lower plate of the second residual quantization capacitor array is connected to the second end of the second switch, the second end of the third switch, and the second end of the fourth switch respectively;

The first terminal of the second switch and the first terminal of the fourth switch are both grounded;

The first end of the third switch is connected to the output end of the reference voltage selection module.

Optionally, the second half unit includes: a third residual quantization capacitor array, a fourth residual quantization capacitor array, a fifth switch, a sixth switch, a seventh switch, an eighth switch, and a second reset switch;

The first end of the fifth switch receives the second output current, and the second end is connected to the first end of the second reset switch, the upper plate of the third residual quantization capacitor array, and the fourth The upper plate of the residual quantization capacitor array and the negative input terminal of the comparator are connected respectively;

The second end of the second reset switch is connected to the lower plate of the third residual quantization capacitor array and grounded;

The lower plate of the fourth residual quantization capacitor array is connected to the first end of the sixth switch, the first end of the seventh switch, and the first end of the eighth switch respectively;

The second terminal of the fifth switch and the first terminal of the eighth switch are both grounded;

The second terminal of the seventh switch is connected to the output terminal of the reference voltage selection module;

The output terminal of the comparator is connected to the residual quantization logic unit.

Optionally, the first residual quantization capacitor array and the third residual quantization capacitor array both include: 2 ^nk unit capacitors;

The second residual quantization capacitor array and the fourth residual quantization capacitor array both include: 2 ^k unit capacitors, and n>k;

The sum of the number of unit capacitors in the first residual quantized capacitor array and the number of unit capacitors in the second residual quantized capacitor array is: 2 ⁿ unit capacitors;

The sum of the number of unit capacitors in the third residual quantized capacitor array and the number of unit capacitors in the fourth residual quantized capacitor array is: 2 ⁿ unit capacitors.

Optionally, the reference voltage selection module is used to select any voltage from 2 ^L reference voltages and output it to the first end of the third switch and the second end of the seventh switch;

The expression for any voltage V _DAC is:

In the above formula, V _ref represents the reference voltage.

Optionally, the first switch, the second switch, the fifth switch, and the sixth switch are closed or opened at the same time;

The first reset switch and the second reset switch are closed or opened at the same time;

The third switch and the eighth switch are closed or opened at the same time;

The fourth switch and the seventh switch are closed or opened at the same time;

Wherein, the residual quantification stage includes: an integration stage and a quantization stage;

In the coarse quantization stage, the first switch is turned off;

During the integration phase, the first switch is closed;

When the first switch is closed, the first reset switch is also closed. After resetting all unit capacitances in the residual quantization capacitor array, the first reset switch is opened;

In the quantization stage, if the first output current is greater than the second output current, the fourth switch is closed and the third switch is opened;

In the quantization stage, if the first output current is less than the second output current, the third switch is closed and the fourth switch is opened.

Optionally, after the first output current and the second output current are integrated over time t ₁ , the integrated voltages VA _and V _B are respectively obtained, then:

In the above formula, G _m represents the voltage-to-current amplification coefficient, and C _u2 represents the capacitance of the unit capacitor;

If V _A >V _B and the residual quantization is L-bit, then in the quantization stage, before the first comparison of successive approximation quantization, any voltage V _DAC selects the middle level of the reference voltage ,Right now:

In the above formula, V _ref represents the reference voltage;

When performing the first comparison, the integrated voltage V _A remains unchanged, and the voltage value of the integrated voltage V _B increases. Then compare the magnitude relationship between the integrated voltages V _A and V _B again. If V _A >V _B at this time, then any voltage V _DAC becomes:

If V _A <V _B at this time, then any voltage V _DAC becomes:

By analogy, after L times of comparison, the L-bit residual quantization result is obtained.

An embodiment of the present invention provides an analog-to-digital converter. The analog-to-digital converter includes: a pipelined successive approximation analog-to-digital conversion circuit as described in any one of the above items.

An embodiment of the present invention also provides an electronic device, the electronic device including: a comparator;

The comparator includes: a pipelined successive approximation analog-to-digital conversion circuit as described in any one of the above items.

The pipelined successive approximation analog-to-digital conversion circuit provided by the present invention includes: a coarse quantization SAR module and a residual quantization SAR module; in the coarse quantization stage, the coarse quantization SAR module is used to approximate and quantize the sampled fully differential input voltage. , obtain the coarse quantization result, and generate two output currents corresponding to the fully differential input voltage, and output them to the residual quantization SAR module.

The residual quantization SAR module includes: residual quantization capacitor array, residual quantization logic unit and comparator; in the residual quantization stage, the residual quantization capacitor array is used to integrate the two output currents to obtain two residual quantization integrals The voltage is output to the comparator, and is used to perform successive approximation quantization based on the on-off status of the residual quantization capacitor array switch to obtain the residual quantization result.

The comparator is used to compare the magnitude of the two residual quantization integrated voltages, and output the first result signal to the residual quantization logic unit; the residual quantization logic unit is used to generate a residual quantization control signal according to the first result signal, Then it controls the on and off of the residual quantization capacitor array switch; among them, in the current coarse quantization cycle, the coarse quantization SAR module completes the coarse quantization of the fully differential input voltage, and at the same time, the residual quantization SAR module completes the coarse quantization of the previous coarse quantization cycle. Residual quantization of residual voltage; the capacitance of the integration capacitor in the coarse quantization SAR module is much smaller than the capacitance of the capacitor in the residual quantization capacitor array.

The pipelined successive approximation analog-to-digital conversion circuit proposed by the present invention reduces the problem that the sampling speed cannot be increased in the traditional high-precision SAR-ADC due to the need to perform full-bit quantization within the same quantization cycle. And the use of pipelines, Gm sharing and other methods reduce the power consumption problems caused by this part. The pipeline working method reduces the problems of small single comparison cycle time margin and incomplete signal establishment leading to bit errors and comparison misjudgments. ; Using the method of residual quantification, it reduces the problem of excessive power consumption caused by too large capacitance values in the capacitor array in traditional high-precision SAR-ADC. At the same time, the reduction in the number of capacitors reduces the problem of process production errors. The accuracy reduction probability caused by mismatching has high practicality.

Description of the drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are for the purpose of illustrating preferred embodiments only and are not to be construed as limiting the invention. Also throughout the drawings, the same reference characters are used to designate the same components. In the attached picture:

Figure 1 is a schematic diagram of the overall structure of a pipelined successive approximation analog-to-digital conversion circuit according to an embodiment of the present invention;

Figure 2 is a schematic structural diagram of a coarse quantized SAR module in an embodiment of the present invention;

Figure 3 is a coarse quantization timing diagram in the embodiment of the present invention;

Figure 4 is a schematic diagram of changes in voltages V _X and V _Y during the coarse SAR process in the embodiment of the present invention;

Figure 5 is a schematic structural diagram of the residual quantization SAR module in the embodiment of the present invention;

Figure 6 is a schematic diagram of changes in voltages V _A and V _B during the residual quantization successive approximation process in the embodiment of the present invention;

FIG. 7 is an overall timing diagram of the successive approximation analog-to-digital conversion circuit during residual quantization in the embodiment of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more obvious and understandable, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention. They are only some embodiments of the present invention, not all embodiments, and are not used to limit the present invention.

The pipelined successive approximation analog-to-digital conversion circuit proposed by the present invention can be used in analog-to-digital converter systems and other systems suitable for comparators, and is especially suitable for medium- and high-precision ADC comparators. The proposed pipelined successive approximation analog-to-digital conversion circuit includes: a coarse quantization SAR module and a residual quantization SAR module.

In the coarse quantization stage, the coarse quantization SAR module is used to approximate and quantize the sampled fully differential input voltage to obtain the coarse quantization result, and generate two output currents corresponding to the fully differential input voltage, and output them to the residual quantization SAR module.

The residual quantization SAR module includes: residual quantization capacitor array, residual quantization logic unit and comparator; in the residual quantization stage, the residual quantization capacitor array is used to integrate the two output currents to obtain two residual quantization integrals The voltage is output to the comparator, and is used to perform successive approximation quantization based on the on-off status of the residual quantization capacitor array switch to obtain the residual quantization result.

The comparator is used to compare the magnitude of the two residual quantization integrated voltages, and output the first result signal to the residual quantization logic unit; the residual quantization logic unit is used to generate a residual quantization control signal according to the first result signal, Then the on and off of the residual quantization capacitor array switch is controlled.

Among them, in the current coarse quantization cycle, the coarse quantization SAR module completes the coarse quantization of the fully differential input voltage, and at the same time, the residual quantization SAR module completes the residual quantization of the residual voltage of the previous coarse quantization cycle; the coarse quantization SAR module The capacitance value of the medium integration capacitor is much smaller than the capacitance value in the residual quantization capacitor array, so that the capacitance value in the coarse quantization SAR module does not affect the capacitance weight during residual quantization.

In order to better explain and illustrate the pipelined successive approximation analog-to-digital conversion circuit of the present invention, reference is made to FIG. 1 , which shows a schematic diagram of the overall structure of the pipelined successive approximation analog-to-digital conversion circuit according to an embodiment of the present invention. The coarse quantization SAR module in Figure 1 includes: capacitive fully differential SAR-ADC structure, voltage-to-current amplification unit, coarse quantization logic unit, judgment latch unit and coarse quantization integration unit. In this coarse quantization SAR module, the specific structure of the capacitive fully differential SAR-ADC structure, coarse quantization logic unit, and judgment latch unit is basically the same as the structure of the currently known SAR-ADC. An additional voltage-to-current amplification unit and a coarse quantization integration unit are added.

In a better implementation, refer to the schematic structural diagram of the coarse quantization SAR module shown in Figure 2. In Figure 2, Gm is used to represent the voltage-to-current amplification unit. The coarse quantization integration unit includes: two reset switches RST ₁ on the right side of Gm , RST ₂ and the structure of two integrating capacitors C ₁ and C ₂ .

The capacitive fully differential SAR-ADC structure includes: M-bit fully differential SAR-ADC. The lower plate of each bit capacitor is connected to 3 switches (represented by SH ₁ and SH ₄ in Figure 2), which receive fully differential inputs respectively. Voltages V _INN , V _INP , reference voltage V _RH and ground. The unit capacitance size in the capacitor array is _Cu1 , the total capacitance size is 2 ^M _Cu1 , and the bottom plate sampling technology is used. The upper plate of the capacitor array receives the common mode voltage V _CM through switches SH ₂ and SH ₃ , and at the same time, the upper plate of the capacitor array is connected to the two input terminals of the Gm module.

In the coarse quantization stage, the capacitive fully differential SAR-ADC structure is used to integrate the fully differential input voltages V _{INN and} V _INP to obtain the positive input _terminal voltage V The positive and negative input terminals of the current amplification unit are used to perform successive approximation quantization based on the on-off status of the capacitor array switch in the capacitive fully differential SAR-ADC structure to obtain a coarse quantization result.

The coarse quantization stage is divided into a sampling stage and a coarse quantization stage. In the sampling phase, switches SH ₁ , SH ₂ , SH ₃ , SH ₄ , reset switches RST ₁ and RST ₂ are closed, the lower plates of the capacitor array are connected to the voltages V _INP and V _INN respectively, and the upper plates of the capacitor array are connected to the common mode voltage V _CM , the upper plates of the integrating capacitors C ₁ and C ₂ are grounded and reset to 0.

In the quantization stage, the switches SH ₁ , SH ₂ , SH ₃ , SH ₄ , and the reset switches RST ₁ and RST ₂ are turned off, and the voltages V _INP and V _INN are sampled to the lower plate of the capacitor. At this time, the capacitor array connected to the positive input terminal of Gm The upper plate voltage is V _CM and the lower plate voltage is V _INP , then the charge sampled at this time Q ₊ = (V _CM -V _INP )2 ^M C _u1 .

In SAR logic, for the first time, the lower plate of the 2 ^M-1 C _u1 capacitor is connected to the ground, and the lower plates of the remaining capacitors are connected to the reference voltage V _RH . Due to the conservation of charge, the Gm positive input terminal voltage _V :

2 ^M-1 (V _x -0)C _u1 +2 ^M-1 (V _x -V _RH )C _u1 ＝Q ₊ ＝(V _CM -V _INP )2 ^M C _u1

Then we can get:

In the same way, the upper plate voltage of the capacitor array connected to the negative input terminal of Gm during the sampling phase is V _CM and the lower plate voltage is V _INN , then the charge sampled at this time Q _{_} = (V _CM -V _INN )2 ^M C _u1 . In SAR logic, for the first time, the lower plate of the 2 ^M-1 C _u1 capacitor is connected to the reference voltage V _RH , and the lower plates of the remaining capacitors are connected to the ground. Due to charge conservation, the Gm negative input terminal voltage V _Y has a relationship:

2 ^M-1 (V _Y -0)C _u1 +2 ^M-1 (V _Y -VTH)C _u1 ＝Q _- ＝(V _CM -V _INN )2 ^M C _u1

Then we can get:

When the two formulas V _X and V _Y are combined, we can get:

_VX - _VY ＝ _VINN - _VINP

If the fully differential input voltage V _INP > V _INN , then V _Y > V _X . The voltage-to-current amplification unit is used to convert and amplify the positive input terminal voltage and the negative input terminal voltage into corresponding two output currents, and output them to the coarse quantization integration unit and the residual quantization SAR module.

That is _, the Gm module amplifies the _voltage and current of _the voltages _V The coarse quantization integration unit is used to integrate the two output currents to obtain two integrated voltages V _A and V _B and output them to the judgment latch unit. The judgment latch unit is used to compare the magnitudes of the two coarse quantization integrated voltages _VA and V _B , and output the second result signal to the coarse quantization logic unit (represented by SAR logic 1 in Figure 2).

The coarse quantization logic unit is used to generate a coarse quantization control signal according to the second result signal, and then control the on and off of the capacitor array switches SH ₁ , SH ₂ , SH ₃ , and SH ₄ in the capacitive fully differential SAR ADC structure. If V _{INP > V INN} , then _{V Y > V} The lower plate of the 2 ^M-1 C _u1 capacitor is connected to ground, the lower plate of the 2 ^M-2 C _u1 capacitor is connected to V _RH , and the lower plates of the remaining capacitors are connected to ground. The weight of the positive input terminal of Gm is that the lower plate of the 2 ^M-1 _Cu1 capacitor is connected to V _RH , the lower plate of the 2 ^M-2 Cu1 capacitor is connected to ground, and the lower plates of the remaining capacitors are connected to V _RH .

If V _INP < V _INN , the lower plate of the 2 ^M-1 C _u1 capacitor remains unchanged. The lower plate of the 2 ^M-2 C _u1 capacitor operates as above (when V _INP > V _INN ), and the second step is performed. Compare and quantize once, and then repeat the above process to complete M-bit coarse quantization. The coarse quantization timing diagram is shown in Figure 3, in which the high level indicates that the switch is closed. The schematic diagram of the _changes in voltage _V The V _X and V _Y voltages, the abscissa is time t, and V _DD represents the power supply voltage. It can be known that the V _X and V _Y voltages gradually approach the common mode voltage V _CM , but there is still a residual voltage, which is processed by the residual quantization SAR module.

In a better implementation, referring to the structural diagram of the residual quantization SAR module shown in Figure 5, the residual quantization logic unit is represented by SAR logic 2, the comparator is represented by CMP, and the remaining part is the residual quantization capacitor array. . In order to better understand the process of residual quantization, Figure 5 illustrates the overall structure diagram of residual quantization.

The residual quantization capacitor array includes: a first half unit and a second half unit; the first half unit receives the first output current of the two output currents, and the second half unit receives the second output current of the two output currents.

The first half unit includes: the first residual quantization capacitor array (the capacitor array connected in parallel with the first reset switch RST ₃ , represented by 2 ^nk C _U2 ), the second residual quantization capacitor array (the capacitor array connected in parallel with the first reset switch RST ₃ capacitor array, represented by 2 ^k C _U2 ), the first switch SH ₅ , the second switch SH ₇ , the third switch φ ₁ , the fourth switch φ ₃ , and the first reset switch RST ₃ .

The first terminal of the first switch _SH5 receives the first output current, and the second terminal is connected with the second terminal of the first reset switch _RST3 , the upper plate of the first residual quantization capacitor array, and the second terminal of the second residual quantization capacitor array. The upper plate and the positive input terminal of the comparator CMP are connected respectively.

The first end of the first reset switch RST ₃ is connected to the lower plate of the first residual quantization capacitor array and grounded; the lower plate of the second residual quantization capacitor array is connected to the second end and the second end of the second switch SH ₇ The second end of the third switch _φ1 and the second end of the fourth switch _φ3 are connected respectively; the first end of the second switch _SH7 and the first end of the fourth switch _φ3 are both grounded; the third end of the third switch _φ1 One end is connected to the output end of the reference voltage selection module (not shown in Figure 5).

The second half unit includes: the third residual quantization capacitor array (the capacitor array connected in parallel with the second reset switch RST ₄ , represented by 2 ^nk C _U2 ), the fourth residual quantization capacitor array (the capacitor array connected in parallel with the second reset switch RST ₄ capacitor array, represented by 2 ^k C _U2 ), the fifth switch SH ₆ , the sixth switch SH ₈ , the seventh switch φ ₂ , the eighth switch φ ₄ , and the second reset switch RST ₄ .

The first end of the fifth switch SH ₆ receives the second output current, and the second end is connected to the first end of the second reset switch RST ₄ , the upper plate of the third residual quantization capacitor array, and the fourth residual quantization capacitor array. The upper plate and the negative input terminal of the comparator CMP are connected respectively.

The second end of the second reset switch RST ₄ is connected to the lower plate of the third residual quantization capacitor array and grounded; the lower plate of the fourth residual quantization capacitor array is connected to the first end and the first end of the sixth switch SH ₈ The first end of the seventh switch φ ₂ and the first end of the eighth switch φ ₄ are connected respectively; the second end of the fifth switch SH ₆ and the first end of the eighth switch φ ₄ are both grounded; the first end of the seventh switch φ ₂ The two terminals are connected to the output terminal of the reference voltage selection module; the output terminal of the comparator CMP is connected to the residual quantization logic unit SAR logic 2.

The first residual quantization capacitor array and the third residual quantization capacitor array both include: 2 ^nk unit capacitors; the second residual quantization capacitor array and the fourth residual quantization capacitor array both include: 2 ^k unit capacitors, and n >k; the sum of the number of unit capacitors in the first residual quantized capacitor array and the number of unit capacitors in the second residual quantized capacitor array is: 2 ⁿ unit capacitors; the units in the third residual quantized capacitor array The sum of the number of capacitors and the number of unit capacitors in the fourth residual quantized capacitor array is: 2 ⁿ unit capacitances.

For the reference voltage selection module, it is used to select any voltage from 2 ^L reference voltages and output it to the first end of the third switch and the second end of the seventh switch; the expression of any voltage V _DAC is:

In the above formula, V _ref represents the reference voltage.

The relationships between each switch are as follows:

The first switch SH ₅ , the second switch SH ₇ , the fifth switch SH ₆ , and the sixth switch SH ₈ are closed or opened at the same time; the first reset switch RST ₃ and the second reset switch RST ₄ are closed or opened at the same time; The third switch φ ₁ and the eighth switch φ ₄ are closed or opened at the same time; the fourth switch φ ₃ and the seventh switch φ ₂ are closed or opened at the same time.

Among them, the residual quantization stage also includes: an integration stage and a quantization stage; in the coarse quantization stage, the first switch is turned off, and it is naturally understandable that the second switch, the fifth switch, and the sixth switch are also turned off.

In the integration stage in the residual quantization stage, the first switch SH ₅ is closed. It is naturally understandable that the second switch SH ₇ , the fifth switch SH ₆ , and the sixth switch SH ₈ are also closed.

When the first switch SH ₅ is closed, the first reset switch RST ₃ and the second reset switch RST ₄ are also closed. After all unit capacitances in the residual quantization capacitor array are reset, the first reset switch RST ₃ and the second reset switch RST 4 are closed. Reset switch RST ₄ opens immediately.

In the quantization stage of the residual quantization stage, if the first output current is greater than the second output current, the fourth switch φ ₃ is closed and the third switch φ ₁ is opened. It is naturally understandable that the seventh switch φ ₂ is closed, The eighth switch φ ₄ is turned off.

In the quantization stage of the residual quantization stage, if the first output current is less than the second output current, the third switch φ ₁ is closed and the fourth switch φ ₃ is opened. It is naturally understandable that the eighth switch φ ₄ is closed, The seventh switch φ ₂ is turned off.

When the first switch SH ₅ and the fifth switch SH ₆ are closed, the capacitor with a capacitance of 2 ⁿ C _u2 is indirectly connected to the output end of the Gm module. The capacitor 2 ⁿ C _u2 is much larger than the integrating capacitor C _{1 and} C in the coarse SAR module. The capacitance value of C ₂ , so that the capacitance values of C ₁ and C ₂ do not affect the capacitance weight in residual quantization.

For the capacitor array in the residual quantization SAR module, among the 2 ⁿ C _u2 unit capacitors, the lower plate of 2 ^nk C _u2 unit capacitors is always connected to ground, and the lower plate of 2 ^k unit capacitors is connected to V _DAC or ground, and is SAR logic 2 controls the closing or opening of each switch SH ₅ , SH ₆ , SH ₇ , SH ₈ , RST ₃ , RST ₄ , φ ₁ , φ ₂ , φ ₃ , and φ ₄ .

After the coarse quantization stage, all switching states of the capacitor array in the coarse quantization SAR module are determined. At this time, there is a residual voltage ΔV ₁ =V _X -V _Y at the input end of the Gm module. After voltage and current amplification, at 2 ⁿ Integration is performed on C _u2 unit capacitor. At this time, the upper plate of the capacitor 2 ⁿ C _u2 is connected to the Gm output terminal and the lower plate is connected to the ground.

After the first output current and the second output current are integrated over time t ₁ , the integrated voltages V _A and V _B are respectively obtained, then:

In the above formula, G _m represents the voltage-to-current amplification factor, and C _u2 represents the capacitance of the unit capacitor.

If V _A >V _B at this time, the residual quantization is L-bit, then any voltage V _DAC selects the middle voltage of the reference voltage before the first comparison of the successive approximation quantization in the quantization stage of the residual quantization stage. flat, that is:

In the above formula, V _ref represents the reference voltage.

When performing the first comparison, the integrated voltage V _A remains unchanged, and the voltage value of the integrated voltage V _B increases. Then compare the magnitude relationship between the integrated voltages V _A and V _B again. If V _A >V _B is still at this time, then any voltage V _DAC becomes:

If V _A <V _B at this time, then any voltage V _DAC becomes:

Taking the L bit as 8bit as an example, if V _A > V _B , the voltage V _DAC selects one-half of the reference voltage. When performing the first comparison, the integrated voltage V _A remains unchanged, and the voltage value of the integrated voltage V _B increases by four. three-thirds of the reference voltage. When performing the second comparison, if V _A >V _B , the integrated voltage V _A remains unchanged, and the voltage value of the integrated voltage V _B increases by seven-eighths of the reference voltage. By analogy, after L times of comparison, the L-bit residual quantization result is obtained. Finally, the analog-to-digital conversion of M+L bit is completed.

The schematic diagram of the changes of voltages _VA and _VB during the residual quantization successive approximation process is shown in Figure 6. In Figure 6, the voltages _VA and _VB are compared six times as an example. Combined with the overall timing diagram of the successive approximation analog-to-digital conversion circuit during residual quantization shown in Figure 7, we can more clearly understand the capacitor array switch SH ₁ in the coarse quantization SAR module, the reset switch RST ₁ , and the third switch in the residual quantization SAR module. A switch SH ₅ , the on-off status of the first reset switch RST ₃ , and the process of successive approximation quantization.

In an embodiment of the present invention, based on the above-mentioned pipelined successive approximation analog-to-digital conversion circuit, an analog-to-digital converter is also proposed. The analog-to-digital converter includes: a pipelined successive approximation analogue as described in any of the above items. digital conversion circuit.

In the embodiment of the present invention, based on the above-mentioned pipelined successive approximation analog-to-digital conversion circuit, an electronic device is also proposed. The electronic device includes: a comparator; the comparator includes: the pipelined type as described in any one of the above Successive approximation analog-to-digital conversion circuit.

To sum up, the pipelined successive approximation analog-to-digital conversion circuit of the present invention includes: a coarse quantization SAR module and a residual quantization SAR module; in the coarse quantization stage, the coarse quantization SAR module is used to sample the fully differential input The voltage is approximated and quantized to obtain a coarse quantization result, and two output currents corresponding to the fully differential input voltage are generated and output to the residual quantization SAR module.

The residual quantization SAR module includes: residual quantization capacitor array, residual quantization logic unit and comparator; in the residual quantization stage, the residual quantization capacitor array is used to integrate the two output currents to obtain two residual quantization integrals The voltage is output to the comparator, and is used to perform successive approximation quantization based on the on-off status of the residual quantization capacitor array switch to obtain the residual quantization result.

The comparator is used to compare the magnitude of the two residual quantization integrated voltages, and output the first result signal to the residual quantization logic unit; the residual quantization logic unit is used to generate a residual quantization control signal according to the first result signal, Then it controls the on and off of the residual quantization capacitor array switch; among them, in the current coarse quantization cycle, the coarse quantization SAR module completes the coarse quantization of the fully differential input voltage, and at the same time, the residual quantization SAR module completes the coarse quantization of the previous coarse quantization cycle. Residual quantization of residual voltage; the capacitance of the integration capacitor in the coarse quantization SAR module is much smaller than the capacitance of the capacitor in the residual quantization capacitor array.

The pipelined successive approximation analog-to-digital conversion circuit proposed by the present invention reduces the problem that the sampling speed cannot be increased in the traditional high-precision SAR-ADC due to the need to perform full-bit quantization within the same quantization cycle. And the use of pipelines, Gm sharing and other methods reduce the power consumption problems caused by this part. The pipeline working method reduces the problems of small single comparison cycle time margin and incomplete signal establishment leading to bit errors and comparison misjudgments. ; Using the method of residual quantification, it reduces the problem of excessive power consumption caused by too large capacitance values in the capacitor array in traditional high-precision SAR-ADC. At the same time, the reduction in the number of capacitors reduces the problem of process production errors. The accuracy reduction probability caused by mismatching has high practicality.

Although preferred embodiments of the embodiments of the present invention have been described, those skilled in the art will be able to make additional changes and modifications to these embodiments once the basic inventive concepts are apparent. Therefore, it is intended that the appended claims be construed to include the preferred embodiments and all changes and modifications that fall within the scope of embodiments of the invention.

Finally, it should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or any such actual relationship or sequence between operations. Furthermore, the terms "comprises," "comprises," or any other variation thereof are intended to cover a non-exclusive inclusion such that a process, method, article, or end device that includes a list of elements includes not only those elements but also elements not expressly listed or other elements inherent to such process, method, article or terminal equipment. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, method, article or terminal device including the stated element.

The embodiments of the present invention have been described above in conjunction with the accompanying drawings. However, the present invention is not limited to the above-mentioned specific implementations. The above-mentioned specific implementations are only illustrative and not restrictive. Those of ordinary skill in the art will Under the inspiration of the present invention, many forms can be made without departing from the spirit of the present invention and the scope protected by the claims, and these all fall within the protection of the present invention.

Claims (10)

1. A pipelined successive approximation analog-to-digital conversion circuit, the successive approximation analog-to-digital conversion circuit comprising: a coarse quantization SAR module and a residual quantization SAR module;

in a coarse quantization stage, the coarse quantization SAR module is used for performing approximation quantization on the fully-differential input voltage obtained by sampling to obtain a coarse quantization result, generating two paths of output currents corresponding to the fully-differential input voltage, and outputting the two paths of output currents to the residual quantization SAR module;

the residual quantization SAR module comprises: a residual quantization capacitor array, a residual quantization logic unit, and a comparator;

in the residual quantization stage, the residual quantization capacitor array is used for integrating two paths of output currents to obtain two residual quantization integrated voltages and outputting the two residual quantization integrated voltages to the comparator, and performing successive approximation quantization according to the on-off condition of a residual quantization capacitor array switch to obtain a residual quantization result;

the comparator is used for comparing the magnitudes of two residual quantized integral voltages and outputting a first result signal to the residual quantized logic unit;

the residual quantization logic unit is used for generating a residual quantization control signal according to the first result signal so as to control the on-off of the residual quantization capacitor array switch;

the coarse quantization SAR module completes coarse quantization of the fully-differential input voltage in the current coarse quantization period, and simultaneously completes residual quantization of residual voltage in the previous coarse quantization period;

the capacitance value of the integrating capacitor in the coarse quantization SAR module is far smaller than that of the capacitor in the residual quantization capacitor array.

2. The successive approximation analog-to-digital conversion circuit of claim 1, wherein the coarse quantization SAR module comprises: the device comprises a capacitive full-differential SAR ADC structure, a voltage-to-current amplifying unit, a coarse quantization logic unit, a judgment latch unit and a coarse quantization integration unit;

in the coarse quantization stage, the capacitive full-differential SAR ADC structure is configured to integrate the full-differential input voltage to obtain a positive input end voltage and a negative input end voltage, and output the positive input end voltage and the negative input end voltage to the positive input end and the negative input end of the voltage-to-current amplifying unit, respectively, and perform successive approximation quantization according to the on-off condition of a capacitive array switch in the capacitive full-differential SAR ADC structure, so as to obtain the coarse quantization result;

the voltage-to-current amplifying unit is used for converting and amplifying the positive input end voltage and the negative input end voltage into two paths of corresponding output currents and outputting the two paths of corresponding output currents to the coarse quantization integrating unit and the residual quantization SAR module;

the coarse quantization integration unit is used for integrating the two paths of output currents to obtain two integrated voltages and outputting the two integrated voltages to the judgment latch unit;

the judgment latch unit is used for comparing the magnitudes of the two coarse quantization integral voltages and outputting a second result signal to the coarse quantization logic unit;

and the coarse quantization logic unit is used for generating a coarse quantization control signal according to the second result signal so as to control the on-off of a capacitor array switch in the capacitor type full-differential SAR ADC structure.

3. The successive approximation analog-to-digital conversion circuit of claim 1, wherein the residual quantization capacitor array comprises: a first half unit and a second half unit;

the first half unit receives a first output current of the two paths of output currents, and the second half unit receives a second output current of the two paths of output currents;

the first half unit includes: the first residual quantization capacitor array, the second residual quantization capacitor array, the first switch, the second switch, the third switch, the fourth switch and the first reset switch;

the first end of the first switch receives the first output current, and the second end of the first switch is respectively connected with the second end of the first reset switch, the upper polar plate of the first residual quantized capacitor array, the upper polar plate of the second residual quantized capacitor array and the positive input end of the comparator;

the first end of the first reset switch is connected with the lower polar plate of the first residual error quantization capacitor array and grounded;

the lower polar plate of the second residual error quantification capacitor array is respectively connected with the second end of the second switch, the second end of the third switch and the second end of the fourth switch;

the first end of the second switch and the first end of the fourth switch are grounded;

the first end of the third switch is connected with the output end of the reference voltage selection module.

4. A successive approximation analog-to-digital conversion circuit as claimed in claim 3, wherein the second half unit comprises: a third residual quantization capacitor array, a fourth residual quantization capacitor array, a fifth switch, a sixth switch, a seventh switch, an eighth switch, and a second reset switch;

the first end of the fifth switch receives the second output current, and the second end of the fifth switch is respectively connected with the first end of the second reset switch, the upper polar plate of the third residual quantized capacitor array, the upper polar plate of the fourth residual quantized capacitor array and the negative input end of the comparator;

the second end of the second reset switch is connected with the lower polar plate of the third residual error quantization capacitor array and grounded;

the lower polar plate of the fourth residual quantization capacitor array is respectively connected with the first end of the sixth switch, the first end of the seventh switch and the first end of the eighth switch;

the second end of the fifth switch and the first end of the eighth switch are grounded;

the second end of the seventh switch is connected with the output end of the reference voltage selection module;

and the output end of the comparator is connected with the residual error quantization logic unit.

5. The successive approximation analog-to-digital conversion circuit of claim 4, wherein the first residual quantization capacitor array and the third residual quantization capacitor array each comprise: 2 ^n-k A unit capacitance;

the second residual quantization capacitor array and the fourth residual quantization capacitor array each include: 2 ^k A number of unit capacitors, n > k;

the sum of the number of the unit capacitors in the first residual quantized capacitor array and the number of the unit capacitors in the second residual quantized capacitor array is as follows: 2 ⁿ A unit capacitance;

the sum of the number of the unit capacitors in the third residual quantization capacitor array and the number of the unit capacitors in the fourth residual quantization capacitor array is as follows: 2 ⁿ A unit capacitance.

6. The successive approximation analog-to-digital conversion circuit of claim 4, wherein the reference voltage selection module is configured to select from 2 ^L Selecting any one of the reference voltages and outputting the selected reference voltage to a first end of the third switch and a second end of the seventh switch;

said arbitrary voltage V _DAC The expression of (2) is:

in the above, V _ref Representing the reference voltage.

7. The successive approximation analog-to-digital conversion circuit according to claim 4, wherein the first switch, the second switch, the fifth switch, and the sixth switch are simultaneously closed or simultaneously opened;

the first reset switch and the second reset switch are simultaneously closed or simultaneously opened;

the third switch and the eighth switch are simultaneously closed or simultaneously opened;

the fourth switch and the seventh switch are simultaneously closed or simultaneously opened;

wherein the residual quantization stage comprises: an integration stage and a quantization stage;

during the coarse quantization phase, the first switch is open;

during the integration phase, the first switch is closed;

the first reset switch is closed when the first switch is closed, and is opened after all unit capacitors in the residual quantized capacitor array are reset;

in the quantization stage, if the first output current is greater than the second output current, the fourth switch is closed, and the third switch is opened;

in the quantization stage, if the first output current is smaller than the second output current, the third switch is closed, and the fourth switch is opened.

8. The successive approximation analog-to-digital conversion circuit of claim 6, wherein the first output current and the second output current each pass through t ₁ After time integration, the integrated voltage V is obtained _A 、V _B The following steps are:

in the above, G _m Representing the voltage-to-current amplification factor, C _u2 Representing the capacitance value of the unit capacitor;

if V _A >V _B The residual is quantized to L-bit, and then in the quantization stage, any voltage V is obtained before the first comparison of successive approximation quantization _DAC Selecting an intermediate level of the reference voltage, namely:

in the above, V _ref Representing the reference voltage;

for the first comparison, the voltage V is integrated _A Unchanged, integral voltage V _B Rise of voltage value of (2)Then again compare the integrated voltage V _A 、V _B If V is the magnitude relation of _A >V _B Then any voltage V _DAC The process is as follows:

if at this time V _A ＜V _B Then any voltage V _DAC The process is as follows:

and by analogy, L times of comparison are carried out, and an L-bit residual error quantization result is obtained.

9. An analog-to-digital converter, the analog-to-digital converter comprising: a pipelined successive approximation analog-to-digital conversion circuit as claimed in any one of claims 1 to 8.

10. An electronic device, the electronic device comprising: a comparator;

the comparator includes: a pipelined successive approximation analog-to-digital conversion circuit as claimed in any one of claims 1 to 8.