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CN101777543A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN101777543A
CN101777543A CN201010002026A CN201010002026A CN101777543A CN 101777543 A CN101777543 A CN 101777543A CN 201010002026 A CN201010002026 A CN 201010002026A CN 201010002026 A CN201010002026 A CN 201010002026A CN 101777543 A CN101777543 A CN 101777543A
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semiconductor device
insulating layer
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白木诚一
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NEC Corp
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Abstract

本发明提供一种半导体器件。该半导体器件包括：导电部，所述导电部形成在半导体芯片上；以及凸块电极，所述凸块电极直接或间接形成在导电部上。导电部包括狭缝部，所述狭缝部具有的厚度比导电部的其它部分更薄。凸块电极在狭缝部上方具有与狭缝部相对应的凹陷部。

Description

半导体器件
技术领域
本发明涉及一种半导体器件及其制造方法，更具体而言，涉及一种具有凸块电极结构的半导体器件及其制造方法。
背景技术
近年来，半导体器件的结合焊盘部已经变得越来越窄并且越来越小。另一方面，结合焊盘的数目已经增加。随着这些改变，当对凸块电极的表面执行芯片测试时，更频繁地出现探测卡针的偏移现象。当出现探测卡针的偏移现象时，在某些情况下，针时常与除了凸块电极之外的图案相接触。结果，半导体器件的表面出现损伤，从而导致产品故障。
图1是传统半导体器件的焊盘结构的截面图。凸块电极7的面上的Al层结合焊盘1的表面是平坦的，并且因此凸块电极7的表面也几乎是平坦的。在位于Al层结合焊盘1的左端和右端的凸块电极7的表面上，实际存在小的阶梯。然而，这些阶梯之间的距离大致为数十微米，并且因此凸块电极7的表面的形状不陡峭并且基本上是平坦的。由此带来的结果是，当探测卡针出现偏移时，针滑离凸块电极7并且因此从其偏移，并且与除了凸块电极7之外的图案的一部分相接触，使得图案受损。
结合以上说明，日本专利申请公布(JP 2003-347351A：第一传统示例)公开了与半导体器件相关的发明。第一传统示例的半导体器件包括半导体衬底、布线层、突出层(projected layer)和导电层。这里，半导体衬底具有半导体元件部。布线层形成在半导体衬底的主表面上。在预定的焊盘区域上，设置有在布线层上选择性地形成的至少一个突出层。导电层覆盖焊盘区中突出层的暴露表面和布线层的暴露表面的不平坦表面。
发明内容
本发明的目的在于在凸块电极上设置不平坦部，以防止探测卡针的偏移。
在本发明的一个方面，一种半导体器件包括：导电部，所述导电部形成在半导体芯片上；以及凸块电极，所述凸块电极直接或间接形成在导电部上。导电部包括狭缝部，所述狭缝部具有的厚度比导电部中的其它部分更薄。凸块电极在狭缝部上方具有与狭缝部相对应的凹陷部。
在本发明的另一个方面，一种制造半导体器件的方法包括：在半导体芯片上形成导电部，所述导电部包括狭缝部，所述狭缝部具有的厚度比导电部的其它部分更薄；以及在导电部上形成凸块电极，使得在狭缝部上方形成与狭缝部相对应的凹陷部。
在凸块电极7的表面上形成不平坦部。凸块电极7的表面上的凹陷部可以防止探测卡针的偏移。在本发明中，狭缝部2被事先设置在Al层结合焊盘1中，并且HDP(高密度等离子体)层间绝缘膜4和SiON膜5或SiN膜5形成在Al层结合焊盘上，并且凸块电极7进一步形成在Al层结合焊盘上。这时，在狭缝部2上方的每一层处都形成了不平坦部。
附图说明
图1是根据传统技术的半导体器件的焊盘结构的截面图；
图2是根据传统技术的Al层结合焊盘的平面图；
图3是根据传统技术在HDP层间氧化物膜上形成HDP层间绝缘层并且形成SiON膜或SiN膜之后的焊盘结构的截面图；
图4是根据传统技术在形成覆盖开口6之后的焊盘结构的截面图；
图5是根据本发明的第一实施例的半导体器件的Al层结合焊盘1的平面图；
图6是在形成HDP层间绝缘层和SiON膜或SiN膜之后的根据本发明第一实施例的半导体器件的截面图；
图7是在形成覆盖开口之后的根据本发明第一实施例的半导体器件的截面图；
图8是在形成凸块电极之后的根据本发明第一实施例的半导体器件的截面图；
图9是根据本发明第二实施例的半导体器件的Al层结合焊盘的示例的平面图；
图10是根据本发明第二实施例的半导体器件的Al层结合焊盘的另一个示例的平面图；
图11是根据本发明第二实施例的半导体器件的截面图；
图12是根据本发明第三实施例的Al层结合焊盘的平面图；
图13是根据本发明第三实施例的半导体器件的截面图；以及
图14是根据本发明第四实施例的多个Al层结合焊盘的平面图。
具体实施方式
下文中，将参照附图来描述根据本发明的半导体器件。
这里，在说明根据本发明第一实施例的半导体之前，将描述制造半导体器件的传统方法。
图2是传统方法中的Al层结合焊盘1的平面图。Al层结合焊盘1具有平坦表面。图3是传统方法中的焊盘结构的截面图。在Al层结合焊盘1上形成高密度等离子体(HDP)层间绝缘膜4，并且在HDP层间绝缘膜4上形成SiON膜5或SiN膜5。图4是传统技术中的在形成覆盖开口6之后的焊盘结构的截面图。为了形成覆盖开口6，通过覆盖PR(光致抗蚀剂)步骤，蚀刻Al层结合焊盘1上的HDP层间绝缘膜4和HDP层间绝缘膜4上的SiON膜5或SiN膜5。在形成覆盖开口6之后，在Al层结合焊盘1上形成凸块电极7，由此提供了上述图1所示的结果。即，在凸块电极7下面的Al层结合焊盘1的表面是平坦的，并且因此凸块电极7的表面也几乎是平坦的。在Al层结合焊盘1的左端和右端，凸块电极7的表面上都呈现小的阶梯部。然而，这两个阶梯部之间的距离大致是数十微米，并且凸块电极7的表面是平滑的，并且基本上是平坦的，使得探测卡针容易滑动。
[第一实施例]
图5是根据本发明第一实施例的半导体器件的Al层结合焊盘1的平面图。应该注意的是，Al层结合焊盘1可以是由除了铝之外的材料形成的导电部。Al层结合焊盘1设置有狭缝部2。应该注意的是，虽然狭缝部2不是必须穿透Al层结合焊盘1，但是在该示例中，狭缝部2在Al层结合焊盘1的厚度方向上穿透Al层结合焊盘1。即，狭缝部2可以是距离Al层结合焊盘1的表面具有足够深度的凹陷部。此外，狭缝部2的形状不限于矩形，并且可以自由设计，只要使狭缝部2位于Al层结合焊盘1的区域内部即可。为了形成Al层结合焊盘1，可以从最开始形成除了狭缝部2之外的部分。可替选地，在形成了包括狭缝部2的整个区域之后，可以去除狭缝部2。
图6是在Al层结合焊盘1上形成HDP层间绝缘膜4、并随后在HDP层间绝缘膜4上形成SiON膜5或SiN膜5之后的根据本发明第一实施例的半导体器件的截面图。在狭缝部2上方的HDP层间绝缘膜4和SiON膜5或SiN膜5的表面上形成与狭缝部2的形状相对应的不平坦部。
应该注意的是，Al层结合焊盘1和HDP层间绝缘膜4可以不必直接彼此接触。例如，在Al层结合焊盘1和HDP层间绝缘膜4之间可以存在另一个组件。类似地，HDP层间绝缘膜4和SiON膜5或SiN膜5可以不必彼此直接接触。在HDP层间绝缘膜4与SiON膜5或SiN膜5之间可以存在另一个组件。
图7是在形成覆盖开口6之后的根据本发明第一实施例的半导体器件的截面图。为了形成覆盖开口6，通过覆盖PR步骤，蚀刻Al层结合焊盘1上的HDP层间绝缘膜4以及HDP层间绝缘膜4上的SiON膜5或SiN膜5。形成覆盖开口6的方法不限于蚀刻。覆盖开口6可以通过另一种方法形成。在这种情况下，优选地，覆盖开口6不在狭缝部2上方延伸。
图8是在形成凸块电极7之后的根据本发明第一实施例的半导体器件的截面图。凸块电极7的表面形状具有示出下层形状的不平坦部。即，在狭缝部2上方的凸块电极7的表面上形成与狭缝部2的形状相对应的不平坦部。优选地，狭缝部2的宽度大致为几微米。应该注意的是，可以根据狭缝部2的宽度、Al层结合焊盘1的宽度、凸块电极7的宽度等，调节凸块电极7的表面上的不平坦部。
以此方式在凸块电极7的表面上形成的不平坦部，可以用作阻止探测卡针的停止部。由此带来的结果是，即使在针滑动时，也可以防止对除了凸块电极之外的图案的损坏。
[第二实施例]
图9是根据本发明第二实施例的半导体器件的Al层结合焊盘1的平面图。狭缝部2设置在Al层结合焊盘1的整个外围部中，以在中间部和周围边缘部之间至少具有连接部。这允许在凸块电极7周围形成不平坦部。因此，当探测卡针向下放置于凸块电极7的中间部上时，即使针在凸块电极7上滑动，也绝不会移动出凸块电极7的周围边缘部。
图10是根据本发明第二实施例的半导体器件的Al层结合焊盘1的另一个示例的平面图。该示例与图9的不同之处在于，狭缝部2被划分成多个狭缝子部2-1，由此即使当狭缝子部2-1穿透Al层结合焊盘1时，Al层结合焊盘1的周围边缘部和中间部也成为一体。这使得可以避免在形成Al层结合焊盘1的步骤中遭遇到技术困难。应该注意的是，如果两个狭缝子部2-1之间的距离足够小于探测卡针的直径，则针绝不会移动出Al层结合焊盘1的周围边缘部。
图11是根据本发明的第二实施例的半导体器件的截面图。第二实施例与图8所示的第一实施例的不同之处在于，虽然实际在凸块电极7的周围边缘部中形成凹陷部，但是在凸块电极7的两端存在凹陷部。因此，无论探测卡针在凸块电极7的表面上沿着哪个方向移动，周围边缘部都用作停止部。
其他特征与第一实施例的特征相同，因此从说明书中省略。
[第三实施例]
图12是根据本发明的第三实施例的半导体器件的Al层结合焊盘1的平面图。在该Al层结合焊盘1中，设置了两个平行的狭缝子部2-2。使用Al层结合焊盘1，如在第一实施例中一样，形成HDP层间绝缘膜4和SiON膜5或SiN膜5，并且形成覆盖开口6，然后形成凸块电极7。
图13是根据本发明的第三实施例的半导体器件的截面图。根据狭缝子部2-2的数目，凸块电极7的表面上不平坦部的数目是复数。由于不平坦部的数目是多个，因此停止部对探测卡针的作用被加强。即，即使在探测卡针穿破第一凹陷部的情况下，第二凹陷部也再次用作停止部。
其他特征与第一实施例的其他特征相同，因此从说明中省略。
[第四实施例]
图14是根据本发明第四实施例的多个Al层结合焊盘的平面图。这里，在一个半导体芯片3上，形成多个Al层结合焊盘1，每个Al层结合焊盘1包括狭缝部2。多个Al层结合焊盘1被设计成满足：多个狭缝部2被布置在位于半导体芯片3外围的顶部、底部、左部和右部。通常，探测卡针从半导体的内部探测到外部。因此，根据本实施例，即使当针移动时，多个狭缝部2中的每个都用作停止部，进一步改进了本发明提供的效果。
以上已经描述了本发明的多个实施例，并且可以在技术上一致的范围内将各个实施例的特征自由组合在一起。

Claims (14)

1.一种半导体器件，包括：
导电部，所述导电部形成在所述半导体芯片上；以及
凸块电极，所述凸块电极直接或间接形成在所述导电部上，
其中，所述导电部包括：
狭缝部，所述狭缝部具有比所述导电部的其它部分更薄的厚度，
其中，所述凸块电极在所述狭缝部上方具有与所述狭缝部相对应的凹陷部。
2.根据权利要求1所述的半导体器件，还包括：
绝缘层，所述绝缘层形成在所述狭缝部与所述凸块电极之间。
3.根据权利要求2所述的半导体器件，其中，所述绝缘层包括：
HDP层间绝缘层，所述HDP层间绝缘层形成在所述导电部上；以及
SiN膜或SiON膜，所述SiN膜或SiON膜形成在所述HDP绝缘膜上。
4.根据权利要求1至3中任一项所述的半导体器件，其中，所述狭缝部在所述导电部的厚度方向上穿透所述导电部。
5.根据权利要求1至3中任一项所述的半导体器件，其中，所述狭缝部包括：
在所述导电部的所述厚度方向上的凹陷部。
6.根据权利要求1至3中任一项所述的半导体器件，其中，所述导电部包括多个狭缝子部，
所述凸块电极包括与所述多个狭缝子部相对应的多个所述凹陷部。
7.根据权利要求6所述的半导体器件，其中，所述多个狭缝子部被布置成在所述导电部中彼此平行，以及
所述多个凹陷部被布置成在所述凸块电极中彼此平行。
8.根据权利要求6所述的半导体器件，其中，所述多个狭缝子部被分布式地布置在所述导电部的周围部分中，以及
所述多个凹陷部被分布式地布置在所述凸块电极的周围部分中。
9.根据权利要求1至3中任一项所述的半导体器件，还包括：多个所述凸块电极。
10.一种制造半导体器件的方法，包括：
在半导体芯片上形成导电部，所述导电部包括狭缝部，所述狭缝部具有比所述导电部的其它部分更薄的厚度；以及
在所述导电部上形成凸块电极，使得在所述狭缝部上方与所述狭缝部相对应地形成凹陷部。
11.根据权利要求10所述的方法，还包括：
在所述导电部上形成绝缘层；以及
去除所述绝缘层的一部分，以形成覆盖开口，
其中，所述形成绝缘层包括：
形成所述绝缘层，以在所述狭缝部上方留下与所述狭缝部相对应的凹陷部，
其中，所述去除包括：
去除所述绝缘层的一部分，以留下所述绝缘层的所述凹陷部。
12.根据权利要求11所述的方法，其中，所述形成绝缘层包括：
在所述导电部上，形成HDP层间绝缘层；以及
在所述HDP层间绝缘层上，形成SiON膜或SiN膜。
13.根据权利要求10至12中任一项所述的方法，其中，所述形成导电部包括：形成除了所述狭缝部之外的所述导电部。
14.根据权利要求10至12中任一项所述的方法，其中，所述形成导电部包括：
形成除了所述狭缝部之外的所述导电部；
在导电部形成区域的整个区域上形成所述导电部；以及
从所述导电部中去除所述导电部的与所述狭缝部相对应的部分。
CN201010002026A 2009-01-08 2010-01-07 半导体器件 Pending CN101777543A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681469A (zh) * 2012-08-31 2014-03-26 爱思开海力士有限公司 半导体器件及其形成方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9984987B2 (en) 2016-08-05 2018-05-29 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1197290A (zh) * 1997-04-21 1998-10-28 冲电气工业株式会社 半导体器件
CN1518060A (zh) * 2003-01-15 2004-08-04 ������������ʽ���� 金属元件、半导体器件、电子器件和电子设备及其制法
CN1655349A (zh) * 2004-02-10 2005-08-17 松下电器产业株式会社 半导体器件及其制造方法
CN1949503A (zh) * 2005-10-14 2007-04-18 恩益禧电子股份有限公司 半导体器件及其制造方法
US20080157359A1 (en) * 2006-12-27 2008-07-03 Sharp Kabushiki Kaisha Crack-resistant solder joint, electronic component such as circuit substrate having the solder joint, semiconductor device, and manufacturing method of electronic component

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003347351A (ja) * 2002-05-29 2003-12-05 Mitsubishi Electric Corp 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1197290A (zh) * 1997-04-21 1998-10-28 冲电气工业株式会社 半导体器件
CN1518060A (zh) * 2003-01-15 2004-08-04 ������������ʽ���� 金属元件、半导体器件、电子器件和电子设备及其制法
CN1655349A (zh) * 2004-02-10 2005-08-17 松下电器产业株式会社 半导体器件及其制造方法
CN1949503A (zh) * 2005-10-14 2007-04-18 恩益禧电子股份有限公司 半导体器件及其制造方法
US20080157359A1 (en) * 2006-12-27 2008-07-03 Sharp Kabushiki Kaisha Crack-resistant solder joint, electronic component such as circuit substrate having the solder joint, semiconductor device, and manufacturing method of electronic component

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681469A (zh) * 2012-08-31 2014-03-26 爱思开海力士有限公司 半导体器件及其形成方法

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