CN101762796B - Magnetic field detector - Google Patents
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- CN101762796B CN101762796B CN 200810044169 CN200810044169A CN101762796B CN 101762796 B CN101762796 B CN 101762796B CN 200810044169 CN200810044169 CN 200810044169 CN 200810044169 A CN200810044169 A CN 200810044169A CN 101762796 B CN101762796 B CN 101762796B
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Abstract
The invention discloses a magnetic field detector comprising a Hall disc which is used for detecting induced voltage generated by a magnetic field, the induced voltage is sent to a computing amplifier CPAI through a first-stage modulator, and then the amplified induced voltage is inputted to a low-pass filter LF1 through a second-stage modulator by the CPAI to eliminate the offset voltage influence of the CPAI and finally is inputted to a comparer COMP1 to be compared with the output voltage of a temperature and voltage self-compensating circuit so that the final output voltage is obtained. The invention not also increases the reliability of the circuit, but also lowers the complicate degree of the circuit and reduces the cost.
Description
Technical field
The present invention relates to the SIC (semiconductor integrated circuit) field, relate in particular to a kind of magnetic field detector.
Background technology
In modern industry, the field of using switch type magnetic field detecting device and linear magnetic field detecting device is more and more.Mainly be automotive electronics and consumer electronics field, various application scenarios have different requirements to the precision of magnetic field detector with reliability.
In the prior art, magnetic field detector has the following disadvantages: the first since for detection of the Primary Component of magnetic field intensity suddenly the resistance of ear dish can be subjected to the impact of temperature and voltage, thereby the error of whole system is strengthened.Second, high-end linear magnetic field detecting device can be in chip integrated very complicated multistage temperature-compensation circuit eliminate the temperature error of whole system, complicated circuit design can cause the cost of chip significantly to rise, thereby can only be applied on the relatively more expensive platform, has limited the scope of using.The 3rd: the fairly simple switch type magnetic field detecting device of circuit structure then seldom compensates for the consideration of chip cost, so that most switch type magnetic field detecting device can only be used on more less demanding low-grade platforms.
And, as shown in Figure 8, the circuit more complicated of Hall disc and offset compensation circuit and first order modulator in the prior art.
The linear magnetic field detecting device is on the high side, and common switch type magnetic field detector performance is not fully up to expectations, so that much need to use the industrial product of magnetic field detector to be difficult to choice, has affected the expansion of magnetic field detector to more industrial circle.
Summary of the invention
Technical matters to be solved by this invention provides a kind of magnetic field detector, can reduce the impact that is subjected to temperature and voltage of Hall disc, reduces the error of whole system, also can eliminate the temperature error of system simultaneously.
For solving the problems of the technologies described above, the technical scheme of magnetic field detector of the present invention is, comprise Hall disc, Hall disc detects the induced voltage of magnetic field generation and delivers among the operational amplifier CPA1 by first order modulator, induced voltage after CPA1 will amplify is eliminated the offset voltage impact of CPA1 by second level modulator and low-pass filter LF1, and obtain needing voltage relatively by the switched-capacitor circuit among the low-pass filter LF1, the output voltage that is input at last comparator C OMP1 neutral temperature and voltage self-compensation circuit compares and obtains final output.
That described Hall disc is connected with the offset compensation circuit as a further improvement on the present invention.
As another kind of further improvement of the present invention be, described temperature and voltage self-compensation circuit are comprised of the divider resistance ladder, between VDD and GND, comprise successively R10, R20, R30, R40, wherein R10 and R40 are the N trap resistance with the identical implantation concentration of Hall disc, R20 and R30 are polysilicon resistance, and resistance R 10 and R40 be close suddenly ear dish on domain, thereby so that the implantation concentration with Huo Erpan is identical when carrying out Implantation, and obtain and the suddenly duplicate temperature of ear dish and voltage characteristic.
The output of temperature of the present invention and voltage self-compensation circuit can change along with the variation of temperature and voltage, thereby the electrical resistance temperature of Hall disc HP1 and the impact of change in voltage have been eliminated, and utilizing increases electric capacity to operational amplifier CPA1 improvement phase compensation, increased the stability of CPA1, in addition, by second level modulator and low-pass filter LF1 are merged into one group of switching capacity voltage, thereby in the offset voltage of eliminating operational amplifier CPA1, obtain the input of COMP1, and, the present invention by with controlling suddenly that the clock of ear dish offset compensation circuit controls that first order modulator comes so that first order modulator can merge with ear dish offset compensation circuit suddenly, reduced the complexity of circuit, Cost reduction.
Description of drawings
The present invention is further detailed explanation below in conjunction with drawings and Examples:
Fig. 1 is magnetic field detector structural representation of the present invention;
Fig. 2 is Hall disc structural representation among the present invention; (what originally write is the end points connection diagram)
Fig. 3 is Hall disc and clock signal connection diagram among the present invention;
Fig. 4 is operational amplifier structural representation among the present invention;
Fig. 5 is temperature and voltage self-compensation circuit figure;
Fig. 6 is modulator and low-pass filter circuit figure among the present invention;
Fig. 7 is the sequential chart of each control signal among the present invention;
Fig. 8 is Hall disc in the prior art, offset compensation circuit and first order modulator circuit figure;
Fig. 9 is that the present invention controls first order modulator circuit figure with control offset compensation circuit clock.
Reference numeral is that the offset compensation circuit module is 1 among the figure, and the Hall disc module is 2, and first order modulator is 3, and operational amplifier CPA1 is 4, and second level modulator is 5, and low-pass filter is 6, and comparator C OMP1 is 7, and temperature and voltage supplementary circuitry are 8.
Embodiment
As shown in Figure 1, magnetic field detector of the present invention comprises following part:
As shown in Figure 2, in the present invention, Hall disc is a kind of N trap of special implantation concentration, and four ends of Hall disc replace in twos.And, as shown in Figure 3, the HPA end of described Hall disc meets VDD, meets VIN by clock control signal CK2 by clock control signal CK1, the HPB end of Hall disc meets VDD, meets VIP by clock control signal CK1 by clock control signal CK2, the HPC end of Hall disc meets GND, meets VIP by clock control signal CK2 by clock control signal CK1, the HPD end of Hall disc meets GND, meets VIN by clock control signal CK1 by clock control signal CK2, the single spin-echo of clock control signal CK1 and CK2.
The single spin-echo of clock control signal CK1 and CK2.At CK1 constantly, HPA end and the HPC end of HP1 add VDD and GND, this moment, HPB end and HPD end induced Hall voltage, at CK2 constantly, HPB end and the HPD end of HP1 add VDD and GND, this moment, HPC end and HPA end induced Hall voltage, and alternately the mode of output can be with HP1 because the offset voltage that process deviation causes drops to minimum in twos by this four ends.
Also adopted improved phase compensating method for operational amplifier CPA1 among the present invention, as shown in Figure 4, operational amplifier CPA1 comprises that two identical operational amplifier A MP1 and AMP2 amplify AINP and AINN respectively, the input termination AINP of operational amplifier A MP1, output terminal is VOP, 2 liang of resistance R terminate between the output terminal VOP and feedback end of operational amplifier A MP1, capacitor C 1 and resistance R 2 also are connected between operational amplifier A MP1 output terminal VOP and the feedback end, resistance R 1 one ends are connected with the feedback end of operational amplifier A MP1, the other end is connected with resistance R 1 ', resistance R 2 ' is connected with the other end of resistance R 1 ', the input termination AINN of operational amplifier A MP2, output terminal is VON, resistance R 2 ' is between its feedback end and output terminal VON, capacitor C 2 is connected with resistance R 2 ', is connected in parallel between the feedback end and output terminal of operational amplifier A MP2.
And, in the present invention, C1=C2=1pF, the gain of CPA1 is (R2+R1)/R1.Adopt two the same operational amplifier A MP1 and AMP2 respectively VINP and VINN to be amplified, C1 and C2 are exactly the building-out capacitor that adds after improving, usually the building-out capacitor of operational amplifier can be added between the input and output of the operational amplifier second level, but can charge to building-out capacitor when larger because operational amplifier when work second level input and output voltage is poor, make the operational amplifier Speed Reduction so excessive building-out capacitor can cause discharging and recharging overlong time.And two operational amplifier each other loads of another operational amplifier in work cause circuit oscillation so that the phase margin of operational amplifier descends, the electric capacity that the present invention adds a 1pF at output terminal and the feedback input end of each operational amplifier, so not only improved the phase margin of operational amplifier but also owing to the poor very little problem that discharges and recharges that do not exist of electric capacity both end voltage, also just can not affect the speed of operational amplifier.
In addition, the present invention also compensates temperature and the voltage characteristic of Hall disc resistance by temperature and voltage compensating circuit.Generally, when magnetic field intensity during greater than working point (operating point, be called for short BOP), the output of chip will become low level by high level, when magnetic field intensity during less than release value BRP (releasepoint, be called for short BRP), magnetic field intensity will become high level from low level.As shown in Figure 5, temperature and voltage self-compensation circuit are exactly a divider resistance ladder that adopts dissimilar resistance to form, because Hall disc HP1 is the N trap of a special implantation concentration, so the resistance of Hall disc HP1 can change with the variation with temperature and VDD, when temperature was spent to 125 from-40 degree, the resistance of Hall disc HP1 also had-30% to 50% variation.For example when temperature for-40 when spending, the resistance decreasing of Hall disc HP1, induced voltage increases, if this moment VL-VC and the value of VC-VH constant, the output of magnetic field intensity detecting device when also not reaching BOP and BRP will be overturn.With should high temperature the time, magnetic field intensity be greater than BOP and during less than BRP the output of detecting device just can overturn, so just caused two values of BOP and BRP accurate not.In Fig. 5, R10 and R40 are N trap resistance, and R20 and R30 are polysilicon resistance.Among the present invention R10 and R40 changed into the N trap resistance with the identical implantation concentration of Hall disc HP1, and make these two resistance as far as possible near Hall disc HP1 at domain, the resistance of R10 and R40 also can have along with the variation of temperature and voltage the variation with HP1 resistance same ratio like this, like this can be so that the absolute value of VL-VC and VC-VH increases when low temperature reduce during at high temperature, just offset the variation of the hall sensing voltage that the HP1 resistance variations causes, thus make the value of BOP and BRP become more stable accurately.In like manner, HP1 electrical resistance VDD changes and the impact that changes also can change to offset with VDD with R10 and R40.Namely temperature during with change in voltage because the variation of the resistance value of R10 and R40 and the variation ratio of ear dish resistance value is identical suddenly, thereby the absolute value of VL-VC and VH-VC also produces variation in proportion, thereby balanced out the impact of temperature and change in voltage generation.
Shown in Fig. 6,7, in the present invention, modulator and low-pass filter LF1 merge into one group of switched-capacitor circuit, and this group switched-capacitor circuit can be finished simultaneously the elimination of CPA1 offset voltage and the comparator C OMP1 function of input voltage is provided.
The voltage that has added a VOS at the input end of CPA1 represents the offset voltage voltage of CPA1, and the gain of establishing CPA1 is A, and COMP1 initially is output as low level, is the moment of high level at CP1, C3, and the quantity of electric charge Q3 on C4 and the C5 positive plate, Q4 and Q5 are respectively:
Q3＝A(VIP-VIN+VOS)C；Q4＝0；Q5＝2(VL-VC)C
When CP2 is high level, Q3, Q5 is constant, Q4 becomes A (VIP-VIN-VOS) C, this moment C3, the total charge dosage on C4 and the C5 is:
Q3+Q4+Q5=2A (VIP-VIN) C+2 (VL-VC) C formula (1)
By formula (1) as seen, just just can eliminate the offset voltage of CPA1 after the electric charge addition on three electric capacity.When the STRB signal was high level, although the voltage on the positive plate of three electric capacity has all become VX, because principle of charge conservation, total electric weight did not change, and can get:
(VX-VC) (C3+C4+C5)=4 (VX-VC) C=Q3+Q4+Q5 formula (2)
Can be got by formula (2) and formula (1):
VX-VC=[A (VIP-VIN)+(VL-VC)]/2 formulas (3)
The principle of work of comparator C OMP1 is exactly that COMP1 is output as high level when VX-VC＞O, and when VX-VC＜O, COMP1 is output as low level.
A (VIP-VIN) amplifies the induced voltage of A after doubly through CPA1, because VL-VC is negative value, so A (VIP-VIN) must greater than | VL-VC| just can make VX-VC＞O, also just can make the output of COMP1 become height, the output of magnetic field detector could be low by hypermutation, this magnetic field intensity constantly is exactly BOP, with should magnetic field by by force to a little less than when reducing, the output that A (VIP-VIN) is less than magnetic field detector after this negative value of VC-VH could be uprised by low, and the magnetic field intensity of this moment is exactly BRP.Can find out, switched-capacitor circuit is sampled to the output of CPA1 and the output of temperature and voltage self-compensation circuit respectively at CP1 and two moment of CP2, constantly carries out the value that VX-VC is eliminated the offset voltage of CPA1 and obtain simultaneously in the electric charge computing at STRB.
As shown in Figure 9, in the present invention with the clock control first order modulator of controlling the offset compensation circuit.Because first order modulator 1 is mainly used to the output of HP1 is sampled, so the sampling clock CP1 of control first order modulator 1 and CP2 can replace with clock CK1 and the CK2 of control offset compensation circuit, thereby further one group of switch in the offset compensation circuit and first order modulator 1 can be carried out multiplexing, in the situation that do not affect the complexity that the subsequent conditioning circuit sequential has reduced circuit.
The present invention by the R10 in temperature and the voltage self-compensation circuit and R40 are used N trap resistance and on the domain and Hall disc HP1 as far as possible near after, R10, the temperature of R40 and HP1 is basically consistent with voltage characteristic, can produce to the variation of HP1 electrical resistance temperature and voltage good compensating action.In addition, two-stage modulator and low-pass filter also can well be eliminated the voltage imbalance of the CPA1 of operational amplifier.Building-out capacitor newly-increased among the CPA1 also can be so that CPA1 has better phase margin and stability.
Claims (6)
1. magnetic field detector, it is characterized in that, comprise Hall disc, Hall disc detects the induced voltage of magnetic field generation and delivers in the operational amplifier (CPA1) by first order modulator, induced voltage after operational amplifier (CPA1) will amplify is eliminated the offset voltage impact of operational amplifier (CPA1) by second level modulator and low-pass filter (LF1), and obtain needing voltage relatively by the switched-capacitor circuit in the low-pass filter (LF1), the output voltage that is input at last comparer (COMP1) neutral temperature and voltage self-compensation circuit compares and obtains final output;
Described temperature and voltage self-compensation circuit are comprised of the divider resistance ladder, between power supply (VDD) and ground (GND), comprise successively the first resistance (R10), the second resistance (R20), the 3rd resistance (R30), the 4th resistance (R40), wherein the first resistance (R10) and the 4th resistance (R40) are the N trap resistance with the identical implantation concentration of Hall disc, the second resistance (R20) and the 3rd resistance (R30) are polysilicon resistance, and the first resistance (R10) and the 4th resistance (R40) is close suddenly ear dish on domain, thereby so that the implantation concentration with Huo Erpan is identical when carrying out Implantation, and obtain and the suddenly duplicate temperature of ear dish and voltage characteristic;
Second level modulator and low-pass filter (LF1) are merged into one group of switched-capacitor circuit, merge the switched-capacitor circuit that forms provides comparer (COMP1) in the offset voltage of eliminating operational amplifier (CPA1) input voltage; Merging the switched-capacitor circuit that forms comprises: the 3rd electric capacity (C3), the 4th electric capacity (C4) and the 5th electric capacity (C5), the capacitance of described the 3rd electric capacity (C3) and described the 4th electric capacity (C4) is equal, and the capacitance of described the 5th electric capacity (C5) is the twice of the capacitance of described the 3rd electric capacity (C3);
The positive plate of described the 3rd electric capacity (C3) is by the in-phase output end (VOP) of the first switch concatenation operation amplifier (CPA1); The negative plate of described the 3rd electric capacity (C3) is by the reversed-phase output (VON) of second switch concatenation operation amplifier (CPA1); The negative plate of described the 3rd electric capacity (C3) connects the first reference voltage (VC) by the 3rd switch; The positive plate of described the 3rd electric capacity (C3) connects the in-phase input end of comparer (COMP1) by the 4th switch;
The positive plate of described the 4th electric capacity (C4) is by the reversed-phase output (VON) of the 5th switch concatenation operation amplifier (CPA1); The negative plate of described the 4th electric capacity (C4) is by the in-phase output end (VOP) of the 6th switch concatenation operation amplifier (CPA1); The negative plate of described the 4th electric capacity (C4) closes by minion and connects the first reference voltage (VC); The positive plate of described the 4th electric capacity (C4) connects the in-phase input end of comparer (COMP1) by the 8th switch;
The positive plate of described the 5th electric capacity (C5) connects the second reference voltage (VH) by the 9th switch; The positive plate of described the 5th electric capacity (C5) connects the 3rd reference voltage (VL) by the tenth switch; The negative plate of described the 5th electric capacity (C5) connects the first reference voltage (VC); The positive plate of described the 5th electric capacity (C5) connects the in-phase input end of comparer (COMP1) by the 11 switch;
Described the first switch and described second switch are all controlled by the first clock signal (CP1); Described the 5th switch and described the 6th switch are all controlled by second clock signal (CP2); Described the 3rd switch, described the 4th switch, described minion pass, described the 8th switch and the 11 switch are all controlled by the 3rd clock signal (STRB); Described the 9th switch by the output signal (DOUT) of comparer (COMP1) and the first clock signal (CP1) and signal controlling; Described the tenth switch by the non-signal of the output signal (DOUT) of comparer (COMP1) and the first clock signal (CP1) and signal controlling;
Described the first reference voltage (VC) is by the tie point place output of described the second resistance (R20) and described the 3rd resistance (R30) of described temperature and voltage self-compensation circuit; Described the second reference voltage (VH) is by the tie point place output of described the first resistance (R10) and described second resistance (R20) of described temperature and voltage self-compensation circuit; Described the 3rd reference voltage (VL) is by the tie point place output of described the 3rd resistance (R30) and described the 4th resistance (R40) of described temperature and voltage self-compensation circuit.
2. magnetic field detector according to claim 1 is characterized in that, described Hall disc is connected with the offset compensation circuit.
3. magnetic field detector according to claim 2, it is characterized in that, four ends of described Hall disc replace in twos, take the first end (HPA) of described Hall disc and the 3rd end (HPC) as one group, the second end (HPB) and the 4th end (HPD) of described Hall disc are one group, and described offset compensation circuit makes two groups of terminals alternately respond to Hall voltage.
4. magnetic field detector according to claim 3 is characterized in that: described offset compensation circuit comprises that twelvemo pass, the 13 switch, the 14 switch, the 15 switch, sixteenmo close, the tenth minion is closed, eighteenmo closes and the 19 switch;
The first end of described Hall disc (HPA) closes the inverting input (VIN) that connects power supply (VDD), connects described first order modulator by the 19 switch by twelvemo;
Second end (HPB) of described Hall disc closes and connects power supply (VDD), closes by sixteenmo the in-phase input end (VIP) that connects described first order modulator by twelvemo;
The 3rd end (HPC) of described Hall disc closes the in-phase input end (VIP) that connects described first order modulator by the 14 switch ground connection (GND), by the tenth minion;
The 4th end (HPD) of described Hall disc closes the inverting input (VIN) that connects described first order modulator by the 15 switch ground connection (GND), by the tenth minion;
Described twelvemo pass, the 14 switch, sixteenmo close and eighteenmo closes by the first clock control signal (CK1) control, and described the 13 switch, the 15 switch, the tenth minion are closed and the 19 switch is controlled by second clock control signal (CK2); The single spin-echo of described the first clock control signal (CK1) and described second clock control signal (CK2), it is the high moment at described the first clock control signal (CK1), the first end of described Hall disc (HPA) connects power supply (VDD), the 3rd end (HPC) ground connection (GND), the second end (HPB) and the 4th end (HPD) are as the output terminal of induced voltage; It is the high moment in described second clock control signal (CK2), second end (HPB) of described Hall disc connects power supply (VDD), the 4th end (HPD) ground connection (GND), first end (HPA) and the 3rd end (HPC) are as the output terminal of induced voltage.
5. magnetic field detector according to claim 1, it is characterized in that, operational amplifier (CPA1) comprises that two identical the first operational amplifiers (AMP1) and the second operational amplifier (AMP2) amplify the first input signal (AINP) and the second input signal (AINN) respectively;
Input termination first input signal (AINP) of the first operational amplifier (AMP1), output terminal are in-phase output end (VOP); The 5th resistance (R2) two terminates between the in-phase output end (VOP) and feedback end of the first operational amplifier (AMP1); The first electric capacity (C1) and the 5th resistance (R2) also are connected between the in-phase output end (VOP) and feedback end of the first operational amplifier (AMP1); The 6th resistance (R1) end is connected with the feedback end of the first operational amplifier (AMP1), and the other end and the 7th resistance (R1 ') be connected; The other end of the 8th resistance (R2 ') and the 7th resistance (R1 ') is connected;
Input termination second input signal (AINN) of the second operational amplifier (AMP2), output terminal is reversed-phase output (VON), the 8th resistance (R2 ') be connected between the feedback end and reversed-phase output (VON) of the second operational amplifier (AMP2), the second electric capacity (C2) and the 8th resistance (R2 ') be connected, be connected in parallel between the feedback end and output terminal of the second operational amplifier (AMP2).
6. magnetic field detector according to claim 2 is characterized in that, with the clock control first order modulator of control offset compensation circuit.
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