CN101706635B - Pixel arrays, polymer stabilized alignment liquid crystal display panels, and optoelectronic devices - Google Patents
Pixel arrays, polymer stabilized alignment liquid crystal display panels, and optoelectronic devices Download PDFInfo
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- 229920000642 polymer Polymers 0.000 title claims abstract description 25
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 24
- 230000005693 optoelectronics Effects 0.000 title claims abstract description 9
- 238000003491 array Methods 0.000 title 1
- 239000003990 capacitor Substances 0.000 claims abstract description 39
- 230000008878 coupling Effects 0.000 claims abstract description 23
- 238000010168 coupling process Methods 0.000 claims abstract description 23
- 238000005859 coupling reaction Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims description 35
- 239000010409 thin film Substances 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 6
- 230000002459 sustained effect Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 101150037603 cst-1 gene Proteins 0.000 description 2
- 239000000178 monomer Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Abstract
本发明公开了一种像素阵列、聚合物稳定配向液晶显示面板以及光电装置，该像素阵列包括多条第一扫描线、多条第二扫描线、多条数据线、多个子像素与多条共通线。各第二扫描线位于二相邻的第一扫描线之间。各子像素包括第一开关、第二开关、第一像素电极、第二像素电极与第三开关。第一开关以及第二开关与同一条第一扫描线以及同一条数据线电性连接。第一像素电极与第一开关电性连接。第二像素电极与第二开关电性连接，且第一、第二像素电极分别位于第一扫描线两对侧。第三开关具有一电容耦合部，电容耦合部延伸至相邻子像素中的第一像素电极下方，并与相邻子像素中的共通线形成一电压调整电容。
The invention discloses a pixel array, a polymer stabilized alignment liquid crystal display panel and an optoelectronic device. The pixel array includes a plurality of first scanning lines, a plurality of second scanning lines, a plurality of data lines, a plurality of sub-pixels and a plurality of common Wire. Each second scan line is located between two adjacent first scan lines. Each sub-pixel includes a first switch, a second switch, a first pixel electrode, a second pixel electrode and a third switch. The first switch and the second switch are electrically connected to the same first scan line and the same data line. The first pixel electrode is electrically connected to the first switch. The second pixel electrode is electrically connected to the second switch, and the first and second pixel electrodes are respectively located on opposite sides of the first scan line. The third switch has a capacitive coupling portion, the capacitive coupling portion extends below the first pixel electrode in the adjacent sub-pixels, and forms a voltage adjustment capacitor with the common line in the adjacent sub-pixels.
Description
Technical Field
The present invention relates to a Polymer stabilized alignment Liquid Crystal Display (LCD) panel, and more particularly, to a pixel array design in a Polymer stabilized alignment LCD panel.
Background
With the trend of large-scale lcd, the wide viewing angle technology of lcd panels must be continuously improved and broken through in order to overcome the viewing angle problem under large-scale display. Among them, polymer-stabilized alignment liquid crystal display panels having unique pixel electrode patterns have been widely used in various electronic products. Since the polymer sustained alignment lcd panel still faces the color shift problem (colorwashout), in the prior art, each sub-pixel in the polymer sustained alignment lcd panel is designed to have a layout of a main display region (main display region) and a sub-display region (sub-display region), and the main display region and the sub-display region in the same sub-pixel have different cross voltages respectively by using a proper circuit design and a proper driving method, so as to improve the color shift problem.
Disclosure of Invention
The present invention provides a pixel array, a polymer-stabilized alignment liquid crystal display panel and an electro-optical device, which have good display quality.
The invention provides a pixel array which comprises a plurality of first scanning lines, a plurality of second scanning lines, a plurality of data lines, a plurality of sub-pixels and a plurality of common lines connected with one another. Each second scanning line is respectively positioned between two adjacent first scanning lines. The data lines are interlaced with the first scanning lines and the second scanning lines, and the second scanning lines and the data lines define a plurality of sub-pixel regions. The sub-pixels are arranged in the sub-pixel regions, each sub-pixel is electrically connected with one of the first scanning lines, one of the second scanning lines and one of the data lines, and each sub-pixel comprises a first switch, a second switch, a first pixel electrode, a second pixel electrode and a third switch. The first switch and the second switch are electrically connected with the same first scanning line and the same data line. The first pixel electrode is electrically connected with the first switch. The second pixel electrode is electrically connected with the second switch, and the first pixel electrode and the second pixel electrode are respectively positioned at two opposite sides of the first scanning line. The third switch is electrically connected with the second scanning line and the second pixel electrode, and is provided with a capacitive coupling part which is not electrically connected with the second scanning line and the second pixel electrode, and the capacitive coupling part extends to the lower part of the first pixel electrode in the adjacent sub-pixel and is coupled with the common line in the adjacent sub-pixel to form a voltage adjusting capacitor. In addition, the common line is positioned below the first pixel electrode and the second pixel electrode.
In an embodiment of the invention, an extending direction of the first scan line is substantially parallel to an extending direction of the second scan line.
In an embodiment of the invention, the sub-pixels are arranged in a plurality of rows, and the sub-pixels arranged in the same row are electrically connected to the same first scan line and the same second scan line. In addition, the first scanning line and the second scanning line which are electrically connected with the same row of sub-pixels are electrically insulated with each other.
In an embodiment of the invention, the sub-pixels are arranged in a plurality of rows, the capacitive coupling portion in the nth row of sub-pixels extends to a position below the first pixel electrode in the (n +1) th row of sub-pixels, and n is a positive integer. For example, the second scan line is located between the second pixel electrode in the nth column of sub-pixels and the first pixel electrode in the (n +1) th column of sub-pixels.
In an embodiment of the invention, each of the first switches is a first thin film transistor, and the first thin film transistor has a first gate electrically connected to one of the first scan lines, a first source electrically connected to one of the data lines, and a first drain electrically connected to the first pixel electrode.
In an embodiment of the invention, each of the second switches is a second thin film transistor, and the second thin film transistor has a second gate electrically connected to one of the first scan lines, a second source electrically connected to one of the data lines, and a second drain electrically connected to the second pixel electrode.
In an embodiment of the invention, each of the third switches is a third tft, and the third tft has a third gate electrically connected to one of the second scan lines, a third source electrically connected to the second pixel electrode, and the capacitive coupling portion.
In an embodiment of the invention, the third source electrode is directly connected to the second pixel electrode.
In an embodiment of the invention, an extending direction of the common line is substantially parallel to an extending direction of the first scan line.
In an embodiment of the invention, the pixel array may further include a color filter layer covering the first scan line, the second scan line, the data line, the sub-pixels and the common on-line. In a preferred embodiment, each sub-pixel further includes a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is located below the color filter layer and electrically connected with the first pixel electrode, and the first capacitor electrode and one of the common lines form a first storage capacitor. The second capacitor electrode is located below the color filter layer and electrically connected with the second pixel electrode, and the second capacitor electrode and one of the common lines form a second storage capacitor.
In an embodiment of the invention, the first pixel electrode and the second pixel electrode extend to above the first scan line and/or the second scan line.
In an embodiment of the invention, each of the first pixel electrodes has a plurality of groups of first slits to define a plurality of first display regions, and each of the second pixel electrodes has a plurality of groups of second slits to define a plurality of second display regions.
In an embodiment of the invention, each of the sub-pixels and the adjacent sub-pixels are located in the same Column (Column).
The present invention further provides a pixel array, which includes a plurality of first scan lines, a plurality of data lines crossing the first scan lines, a plurality of sub-pixels, and a plurality of common lines, wherein each sub-pixel is electrically connected to one of the first scan lines and one of the data lines, and each sub-pixel includes a pixel electrode and a switch electrically connected to the pixel electrode, wherein the switch has a capacitive coupling portion, and the capacitive coupling portion and the common line in the adjacent sub-pixel form a voltage adjusting capacitor.
The invention further provides a polymer stable alignment liquid crystal display panel, which comprises a first substrate, a second substrate, a polymer stable alignment layer and a liquid crystal layer. The first substrate is provided with the pixel array, the second substrate is arranged above the first substrate, and the two polymer stable alignment layers are respectively arranged on the first substrate and the second substrate. In addition, the liquid crystal layer is arranged between the polymer stable alignment layers.
In an embodiment of the invention, the polymer-stabilized alignment liquid crystal display panel further includes two alignment layers respectively disposed between the first substrate and the polymer-stabilized alignment layer corresponding to the first substrate and between the second substrate and the polymer-stabilized alignment layer corresponding to the second substrate.
The invention also provides an optoelectronic device comprising the pixel array or the polymer stable alignment liquid crystal display panel.
In view of the above, in the pixel array of the invention, the capacitive coupling portion extends to a position below the first pixel electrode in the adjacent sub-pixel, and couples with the common line in the adjacent sub-pixel to form a voltage adjustment capacitor, so that the pixel array of the invention has a higher aperture ratio.
Drawings
FIG. 1 is a circuit diagram of a pixel array according to an embodiment of the invention;
FIG. 2 is a schematic top view of a pixel array according to an embodiment of the invention;
FIG. 3 is a cross-sectional view taken along section A-A' of FIG. 2;
FIG. 4 is a schematic diagram of a polymer stabilized alignment liquid crystal display panel according to an embodiment of the present invention;
fig. 5 is a schematic diagram of an optoelectronic device according to an embodiment of the present invention.
Wherein, the reference numbers:
100: pixel array 110 (i): a first scanning line
120 (i): second scanning line 130 (j): data line
140: the sub-pixel 150: common line
160: color filter layer R: sub-pixel region
SW 1: first switch G1: a first grid electrode
S1: first source D1: a first drain electrode
SW 2: second switch G2: second grid
S2: second source D2: second drain electrode
SW 3: third switch G3: third grid
S3: third source P1: a first pixel electrode
SL 1: first slit DM 1: first display field
P2: second pixel electrode SL 2: second slit
DM 2: second display area C: capacitive coupling part
CCS: voltage adjustment capacitor Cst 1: first storage capacitor
Cst 2: second storage capacitor E1: first capacitor electrode
E2: second capacitance electrode 200: polymer stable alignment liquid crystal display panel
210: first substrate 220: second substrate
230. 240: two-polymer stable alignment layer 250: liquid crystal layer
300: optoelectronic device
Detailed Description
Fig. 1 is a circuit diagram of a pixel array according to an embodiment of the invention, and fig. 2 is a top view of the pixel array according to the embodiment of the invention. Referring to fig. 1 and 2, the pixel array 100 of the present embodiment includes a plurality of first scan lines 110(i), a plurality of second scan lines 120(i), a plurality of data lines 130(j), a plurality of sub-pixels 140, and a plurality of common lines 150, wherein the common lines 150 are connected to each other, for example, where i and j are natural numbers (1, 2, 3, …, n +1 …). The sub-pixels 140 are arranged in a plurality of rows, and in detail, the first scan line 110(i) and the second scan line 120(i) are electrically connected to the sub-pixels 140 arranged in the ith row, and the data line 130(j) is electrically connected to the sub-pixels 140 arranged in the jth column. In addition, the first scan line 110(i) and the second scan line 120(i) electrically connected to the sub-pixels 140 of the ith row are electrically insulated from each other.
In the present embodiment, the extending directions of the first scan line 110(i), the second scan line 120(i) and the common line 150 are substantially parallel, and the extending direction of the data line 130(j) is perpendicular to the extending direction of the first scan line 110 (i).
Each of the second scan lines 120(i) is located between two adjacent first scan lines 110 (i). For example, the second scan line 120(n) connected to the sub-pixels 140 arranged in the nth row is located between the first scan line 110(n) and the first scan line 110(n + 1). In addition, the data line 130(j) intersects with the first scan line 110(i) and the second scan line 120(i), and the second scan line 120(i) and the data line 130(j) define a plurality of sub-pixel regions R. The sub-pixels 140 are disposed in the sub-pixel region R, and the sub-pixels 140 arranged in the ith row and the jth column are electrically connected to the first scan line 110(i), the second scan line 120(i), and the data line 130 (j).
As shown in fig. 1 and 2, the sub-pixel 140 arranged in the ith row and the jth column includes a first switch SW1, a second switch SW2, a first pixel electrode P1, a second pixel electrode P2, and a third switch SW 3. The first switch SW1 and the second switch SW2 are electrically connected to the same first scan line 110(i) and the same data line 130 (j). The first pixel electrode P1 is electrically connected to the first switch SW1, the second pixel electrode P2 is electrically connected to the second switch SW2, and the first pixel electrode P1 and the second pixel electrode P2 are respectively located at two opposite sides of the first scan line 110 (i). The third switch SW3 is electrically connected to the second scan line 120(i) and the second pixel electrode P2, the third switch SW3 has a capacitive coupling portion C that is not electrically connected to the second scan line 120(i) and the second pixel electrode P2, and the capacitive coupling portion C extends to the lower side of the first pixel electrode P1 in the adjacent sub-pixel 140 and forms a voltage adjusting capacitor CCS with the common line 150 in the adjacent sub-pixel 140 in the same column (for example, connected to the same data line 130 (j)). Specifically, the capacitive coupling portion C in the nth column of sub-pixels 140 extends to a position below the first pixel electrode P1 in the (n +1) th column of sub-pixels 140, and couples with the common line 150 in the (n +1) th column of sub-pixels 140 as a voltage adjustment capacitor CCS. In addition, the common line 150 is positioned under the first pixel electrode P1 and the second pixel electrode P2.
In a preferred embodiment, the first switch SW1 is a first tft having a first gate G1 electrically connected to the first scan line 110(i), a first source S1 electrically connected to the data line 130(j), and a first drain D1 electrically connected to the first pixel electrode P1. The second switch SW2 is a second tft having a second gate G2 electrically connected to the first scan line 110(i), a second source S2 electrically connected to the data line 130(j), and a second drain D2 electrically connected to the second pixel electrode P2. The third switch SW3 is a third tft having a third gate G3 electrically connected to the second scan line 120(i), a third source S3 electrically connected to the second pixel electrode P2, and the capacitive coupling portion C. Here, the capacitive coupling portion C is a drain of the third thin film transistor.
It is noted that the sub-pixel 140 of the present embodiment can be applied to a polymer stabilized alignment liquid crystal display panel. In detail, the first pixel electrodes P1 respectively have a plurality of groups of first slits SL1 to respectively define a plurality of first display areas DM1, and each of the second pixel electrodes P2 respectively has a plurality of groups of second slits SL2 to respectively define a plurality of second display areas DM 2. The plurality of first display regions DM1 and the plurality of second display regions DM2 may enable the sub-pixel 140 to have a wide viewing angle characteristic. In fig. 2, the first pixel electrode P1 has 4 sets of first slits SL1, so the first pixel electrode P1 is divided into 4 first display regions DM1, and the second pixel electrode P2 also has 4 sets of second slits SL2, so the second pixel electrode P2 is divided into 4 second display regions DM 2. In other words, the sub-pixel 140 has 8 display areas in total, which is helpful to improve the color shift problem, however, the design of the first pixel electrode P1 or the second pixel electrode P2 can be adjusted to have more display areas according to the user's requirement, and the invention is not limited thereto.
In addition to the pixel electrode design shown in fig. 2, other patterns of the first pixel electrode P1 and the second pixel electrode P2 can be used, and the invention is not limited to the patterns of the first pixel electrode P1 and the second pixel electrode P2.
Fig. 3 is a schematic cross-sectional view taken along the line a-a' in fig. 2. Referring to fig. 2 and 3, in a preferred embodiment of the invention, the pixel array 100 may be integrated with a conventional color filter on array (COA) process. When the color filter layer 160 is formed under the first pixel electrode P1 and the second pixel electrode P2 and covers the first scan line 110(i), the second scan line 120(i), the data line 130(j), the sub-pixel 140 and the common line 150, the capacitive coupling portion C and the common line 150 are located under the color filter layer 160, so that the fabrication of the color filter layer 160 does not cause difficulty in fabricating the voltage regulating capacitor CCS.
Each sub-pixel 140 may further include a first capacitor electrode E1 and a second capacitor electrode E2. The first capacitor electrode E1 is located below the color filter layer 160 and electrically connected to the first pixel electrode P1, and the first capacitor electrode E1 and one of the common lines 150 form a first storage capacitor Cst1, where the common line 150 is, for example, a cross. The second capacitor electrode E2 is located below the color filter layer 160 and electrically connected to the second pixel electrode P2, and the second capacitor electrode E2 and one of the common lines 150 form a second storage capacitor Cst2, where the common line 150 is, for example, a cross. As shown in fig. 2 and 3, the first capacitor electrode E1 is electrically connected, for example directly connected, to the first drain D1, the second capacitor electrode E2 is electrically connected, for example directly connected, to the second drain D2, and the third source S3 can also be electrically connected to the second pixel electrode P2 via the second capacitor electrode E2. In addition, in the embodiment, the third source S3 is not limited to be electrically connected to the second pixel electrode P2 through the second capacitor electrode E2, and the third source S3 may also be electrically connected to the second pixel electrode P2 through a contact window (not shown).
As can be seen from fig. 3, the first pixel electrode P1 and the second pixel electrode P2 of the present embodiment can selectively extend above the first scan line 110(i) and/or the second scan line 120(i), and the parasitic capacitance between the pixel electrodes P1 and P2 and the first scan line 110(i) and the parasitic capacitance between the pixel electrodes P1 and P2 and the second scan line 120(i) can be greatly reduced because the color filter layer 160 has a large thickness.
FIG. 4 is a schematic diagram of a polymer sustained alignment LCD panel according to an embodiment of the invention. Referring to fig. 4, the polymer stabilized alignment lcd panel 200 of the present embodiment includes a first substrate 210, a second substrate 220, two polymer stabilized alignment layers 230 and 240, and a liquid crystal layer 250. The first substrate 210 has the pixel array 100 of the first embodiment or the second embodiment, the second substrate 220 is disposed above the first substrate 210, and the two polymer stable alignment layers 230 and 240 are disposed on the first substrate 210 and the second substrate 220, respectively. In addition, the liquid crystal layer 250 is disposed between the two polymer stable alignment layers 230 and 240. It is noted that the liquid crystal layer 250 is fabricated by using a liquid crystal material containing monomers capable of being polymerized by an energy source, and when the energy source (e.g., ultraviolet light) is applied to the liquid crystal layer 250, the monomers capable of being polymerized by the energy source are polymerized on the surfaces of the first substrate 210 and the second substrate 220, respectively, to form the two polymer-stabilized alignment layers 230, 240. In addition, the polymer-stabilized alignment liquid crystal display panel 200 of the present embodiment may further include two auxiliary alignment layers (not shown), but not limited to, disposed between the first substrate 210 and the polymer-stabilized alignment layer 230 corresponding to the first substrate 210 and disposed between the second substrate 220 and the polymer-stabilized alignment layer 240 corresponding to the second substrate 220, respectively, where the two auxiliary alignment layers are formed of polyimide, for example.
Fig. 5 is a schematic diagram of an optoelectronic device according to an embodiment of the present invention. Referring to fig. 5, the present embodiment also provides an optoelectronic device 300, which includes the pixel array 100 of the previous embodiment or the polymer sustained alignment lcd panel 200 of fig. 3. The types of the aforementioned optoelectronic devices are, for example, portable products (such as mobile phones, video cameras, notebook computers, game machines, watches, music players, email transceivers, map navigators, digital photos, or the like), audio/video products (such as audio/video projectors or the like), screens, televisions, billboards, panels in projectors, and the like.
In view of the above, in the pixel array of the invention, the capacitive coupling portion extends to a position below the first pixel electrode in the adjacent sub-pixel, and couples with the common line in the adjacent sub-pixel to form a voltage adjustment capacitor, so that the pixel array of the invention has a higher aperture ratio. In addition, some of the pixel array designs disclosed in the embodiments of the present invention are compatible with the current COA process, and can achieve a higher pixel aperture ratio.
The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (11)
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| CN105580065B (en) * | 2013-09-26 | 2018-06-26 | 夏普株式会社 | Display panel and the display device for having the display panel |
| CN104503157B (en) * | 2014-12-16 | 2017-11-28 | 深圳市华星光电技术有限公司 | Dot structure and the liquid crystal display with the dot structure |
| US9935130B2 (en) | 2014-12-16 | 2018-04-03 | Shenzhen China Star Optoelectronics Technology Co., Ltd | Pixel structure and liquid crystal display comprising the pixel structure |
| CN106773413A (en) * | 2017-01-03 | 2017-05-31 | 深圳市华星光电技术有限公司 | A kind of array base palte and display device |
| CN107561790A (en) * | 2017-09-19 | 2018-01-09 | 惠科股份有限公司 | Array substrate and display panel thereof |
| CN107450240B (en) * | 2017-09-19 | 2020-06-16 | 惠科股份有限公司 | Array substrate and display panel thereof |
| CN110568688B (en) * | 2018-12-05 | 2022-02-18 | 友达光电股份有限公司 | Display panel |
| CN111381406B (en) * | 2018-12-29 | 2023-02-03 | 咸阳彩虹光电科技有限公司 | Pixel unit, pixel array and liquid crystal panel thereof |
| CN113589602B (en) | 2021-07-20 | 2022-08-23 | Tcl华星光电技术有限公司 | Display panel and display terminal |
| TWI790799B (en) | 2021-11-01 | 2023-01-21 | 友達光電股份有限公司 | Display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1591138A (en) * | 2003-07-31 | 2005-03-09 | 奇美电子股份有限公司 | Film transistor liquid crystal display panel, its array substrate and mfg. method |
| CN1690817A (en) * | 2004-04-19 | 2005-11-02 | 统宝光电股份有限公司 | LCD device |
| CN101303500A (en) * | 2008-07-08 | 2008-11-12 | 友达光电股份有限公司 | Liquid crystal display panel and manufacturing method thereof |
| CN101354512A (en) * | 2007-07-24 | 2009-01-28 | 三星电子株式会社 | Liquid crystal display and its driving method |
| CN101504503A (en) * | 2009-04-10 | 2009-08-12 | 友达光电股份有限公司 | Pixel array, liquid crystal display panel and photoelectric device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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-
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1591138A (en) * | 2003-07-31 | 2005-03-09 | 奇美电子股份有限公司 | Film transistor liquid crystal display panel, its array substrate and mfg. method |
| CN1690817A (en) * | 2004-04-19 | 2005-11-02 | 统宝光电股份有限公司 | LCD device |
| CN101354512A (en) * | 2007-07-24 | 2009-01-28 | 三星电子株式会社 | Liquid crystal display and its driving method |
| CN101303500A (en) * | 2008-07-08 | 2008-11-12 | 友达光电股份有限公司 | Liquid crystal display panel and manufacturing method thereof |
| CN101504503A (en) * | 2009-04-10 | 2009-08-12 | 友达光电股份有限公司 | Pixel array, liquid crystal display panel and photoelectric device |
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