CN101674071B - Physical layer interface circuit - Google Patents
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- CN101674071B CN101674071B CN2008100437785A CN200810043778A CN101674071B CN 101674071 B CN101674071 B CN 101674071B CN 2008100437785 A CN2008100437785 A CN 2008100437785A CN 200810043778 A CN200810043778 A CN 200810043778A CN 101674071 B CN101674071 B CN 101674071B
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Abstract
The invention discloses a physical layer interface circuit. Two voltage-controlled current sources with same current directions and opposite polarities are connected into an output driving stage of each data transmitter; and through the comparative level differences between a common-mode intermediate level of DP and DM differential signals of signal output ends of two data transmitters and the intermediate level of a supply voltage, the compensating current output by each voltage-controlled current source is controlled, and the transient level of output signals of the data transmitters is adjusted correspondingly until a pair of DP and DM differential signals output by the two data transistors of the physical layer interface circuit is in full symmetry. The physical layer interface circuit can inhibit the nonlinear distortions of the output signals and make up the output waveform distortions caused by the mismatch of processes, temperatures, voltages and loads, device parasitism and the like.
Description
Technical field
The present invention relates to the semiconductor integrated circuit technology, particularly a kind of physical layer interface circuit.
Background technology
Along with the continuous development of IC industry, the client is more and more higher to the requirement of electronic product, like this, in order to reach than high rate of finished products and good performance to be arranged, requires the product also can works fine under exacting terms relatively; For example, in technology, temperature, voltage, load do not match and device parasitism or the like condition effect under, can produce nonlinear distortion, reach the requirement of USB standard, PHY (PHYSICAL LAYER physical layer) Design of Interface Circuit difficulty is increasing.
Common PHY (physical layer) interface circuit comprises two data transmitters, exports a pair of differential signal of DP (DataPlus data positive pole), DM (Data Minus data negative pole) respectively.A kind of data transmitter as shown in Figure 1, input signal is adjusted to the appropriate signal form through the output signal controlled stage with signal, by out drive stage signal is exported then; Out drive stage is the push-pull type cmos amplifier, comprises PMOS pipe, NMOS pipe up and down, and PMOS pipe, the drain electrode of NMOS pipe link to each other with signal output part up and down.In real work,, can make the signal of output signal controlled stage output produce deviation because the output signal controlled stage is subjected to the influence of factors vary such as bias current, process deviation and parasitic capacitance; When driving output through out drive stage at last,, thereby produce nonlinear distortion because departing from of electrostatic discharge protective circuit influence and technology can cause PMOS up and down different with the NMOS driving force; On the other hand, the load difference of two difference output stages of regulation (two data transmitters) in the USB standard (in order to the different transmission mode of control USB) can produce deviation to a certain degree equally.Many-sided factor stack causes this interface circuit to be bound to occur in various degree deviation.
For the requirement of satisfying standard that guarantees that physical layer interface circuit can be good, and reduce its dependence to technology and external environment condition, current major technology has: adopt good a reference source to provide biasing for physical layer circuit; Adopt complicated compensating circuit or the like method.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of physical layer interface circuit, and this circuit can suppress the output signal nonlinear distortion, remedies not matching and output waveform distortion that reason such as device parasitism causes owing to technology, temperature, voltage, load.
For solving the problems of the technologies described above, physical layer interface circuit of the present invention, comprise two data transmitters, these two data transmitter output DP, the a pair of differential signal of DM, each data transmitter comprises the output signal controlled stage, out drive stage, input signal is adjusted the back through the output signal controlled stage and by out drive stage signal is exported, out drive stage is the push-pull type cmos amplifier, comprise the PMOS pipe, following NMOS pipe, last PMOS pipe, the drain electrode of following NMOS pipe connects signal output part, it is characterized in that, also comprise four voltage-controlled current sources, each data transmitter out drive stage is the PMOS pipe up and down, between the source-drain electrode of NMOS pipe respectively cross-over connection voltage-controlled current source is arranged, two voltage-controlled current source current opposite in direction of each data transmitter, one flows to signal output part, another flow-out signal output, and two voltage controlled current source polarity of each data transmitter are opposite, between two PMOS pipe source-drain electrodes in the out drive stage of two data transmitters two of cross-over connection the voltage-controlled current source sense of current is identical and polarity is identical, between two NMOS pipe source-drain electrode two of cross-over connection the voltage-controlled current source sense of current is identical and polarity is identical; Get the DP of the signal output part of two data transmitters, the common mode intermediate level of DM differential signal, get the intermediate level of physical layer interface circuit supply voltage, get this differential signal common mode intermediate level with the comparative level difference of the intermediate level of this supply voltage control voltage as four voltage-controlled current sources, when differential signal common mode intermediate level is higher than the intermediate level of this supply voltage, in two voltage-controlled current sources of each data transmitter, the output current that the sense of current flows to the voltage-controlled current source of signal output part reduces, the output current of the voltage-controlled current source of sense of current flow-out signal output increases, when differential signal common mode intermediate level is lower than the intermediate level of this supply voltage, in two voltage-controlled current sources of each data transmitter, the output current that the sense of current flows to the voltage-controlled current source of signal output part increases, and the output current of the voltage-controlled current source of sense of current flow-out signal output reduces.
Can comprise an operational amplifier, the intermediate level of described differential signal common mode intermediate level, supply voltage connects two inputs of described operational amplifier respectively, and the output level of described operational amplifier is as the control voltage of described four voltage-controlled current sources.
Physical layer interface circuit of the present invention, in the out drive stage of each data transmitter, insert two identical and opposite polarity voltage-controlled current sources of the sense of current, DP, the DM differential signal common mode intermediate level of the signal output part by two data transmitters are poor with the comparative level of the intermediate level of this supply voltage, control the size of the offset current of each voltage-controlled current source output, the corresponding height of regulating the output signal transient level of data transmitter, symmetrical fully until a pair of differential signal of DP, DM of two data transmitter outputs of physical layer interface circuit.Physical layer interface circuit of the present invention utilizes common-mode feedback to suppress the output signal nonlinear distortion, the variation of the relative power supply intermediate level of common mode electrical level that the output waveform asymmetric distortion is caused, convert bias level control output driving current to, can remove the output distortion that various unfavorable factors cause effectively, make the differential signal of physical layer interface circuit output have good symmetry, thereby guarantee the purpose of the intact transmission signals of physical layer phy interface circuit energy.This physical layer interface circuit can be applied in a flexible way in the Waveform Control of multiple physical layer interface circuit is adjusted.
Description of drawings
Below in conjunction with the drawings and the specific embodiments the present invention is described in further detail.
Fig. 1 is common physical layer interface one data transmitter circuit diagram;
Fig. 2 is physical layer interface circuit one an execution mode circuit diagram of the present invention;
Fig. 3 is the data transmitter circuit diagram of physical layer interface circuit one execution mode of the present invention.
Embodiment
Physical layer interface circuit one execution mode of the present invention as shown in Figure 2, comprise two data transmitters, also comprise an operational amplifier, these two data transmitter output DP (Data Plus data positive pole), a pair of differential signal of DM (Data Minus data negative pole).Data transmitter comprises output signal controlled stage, out drive stage as shown in Figure 3, and input signal is adjusted to the appropriate signal form through the output signal controlled stage with signal, by out drive stage signal is exported then; Out drive stage is the push-pull type cmos amplifier, comprise PMOS pipe up and down, the NMOS pipe, PMOS manages up and down, the drain electrode of NMOS pipe connects signal output part, PMOS manages up and down, between the source-drain electrode of NMOS pipe respectively cross-over connection voltage-controlled current source is arranged, these two voltage-controlled current source current opposite in direction, one flows to signal output part, another flow-out signal output, and these two voltage controlled current source polarity are opposite, polarity is size of current the changing in the opposite direction with control voltage of two voltage-controlled current sources on the contrary, between two PMOS pipe source-drain electrodes in the out drive stage of two data transmitters of physical layer interface circuit two of cross-over connection the voltage-controlled current source sense of current is identical and polarity is identical, between two NMOS pipe source-drain electrode two of cross-over connection the voltage-controlled current source sense of current is identical and polarity is identical, the size of current of identical i.e. two voltage-controlled current sources of polarity is identical with the change direction of control voltage; Two substitutional resistances of signal output part serial connection at two data transmitters, export the common mode intermediate level of differential signal as physical layer interface circuit with the level of these two interconnected ends of substitutional resistance, two of cross-over connection substitutional resistances between physical layer interface circuit power supply and ground, with the level of described two interconnected ends of substitutional resistance intermediate level as the physical layer interface circuit supply voltage, the intermediate level of this differential signal common mode intermediate level and this supply voltage connects described operational amplifier input, the output of described operational amplifier is connected respectively to two data transmitters, receive four voltage-controlled current sources of two data transmitters, control voltage as voltage-controlled current source, adjust the voltage-controlled current source electric current of the out drive stage of two data transmitters, when differential signal common mode intermediate level is higher than the intermediate level of this supply voltage, the output level of operational amplifier is offset to a direction than stable state, the output current that the Control current direction flows to the voltage-controlled current source of signal output part reduces, the output current of the voltage-controlled current source of sense of current flow-out signal output increases, when differential signal common mode intermediate level is lower than the intermediate level of this supply voltage, the output level of operational amplifier is offset to another direction than stable state, the output current that the Control current direction flows to the voltage-controlled current source of signal output part increases, the output current of the voltage-controlled current source of sense of current flow-out signal output reduces, until the DP of output, the a pair of differential signal of DM is symmetry fully.The gain of adjusting operational amplifier and the size of voltage-controlled current source operating current can be adjusted the sensitivity of feedback.
Be connected across the pipe of PMOS up and down of a data transmitter out drive stage, two voltage-controlled current sources between the source-drain electrode of NMOS pipe are current opposite in direction, opposite polarity voltage-controlled current source, DP when the output of physical layer interface circuit two data transmitters, DM differential signal waveform is not subjected to various factors influence and when normally exporting, the A level (differential signal common mode intermediate level) of ordering equals the level (intermediate level of supply voltage) that B is ordered as shown in Figure 2, the stabilizing output level of operational amplifier, two additional voltage-controlled current sources of one data transmitter provide a small amount of offset current of equity up and down to the output of out drive stage, and this moment, out drive stage was normally exported; Not matching when physical layer interface circuit is subjected to technology, (two data transmitters are subjected to technogenic influence to make circuit incomplete same, cause electrology characteristic that certain difference is arranged), applied load is inequality, and (for example USB regulation and stipulation interface circuit is in different following times of transfer mode, DP, the load of DM end is variant, also can cause the driving force difference of two out drive stages), and during parasitic factor affecting such as inequality, in various degree asymmetric can appear in the differential signal of two data transmitters output, the A level point of this moment is not equal to the B level point, A, B is different, and incoming level can cause that the operational amplifier output level changes, be that output level stable state relatively before is to wherein some direction skews, control one of them increasing current compensation of two voltage-controlled current sources of each data transmitter, and another one reduces current compensation, the corresponding height of regulating the output signal transient level of data transmitter, DP until two data transmitter outputs of physical layer interface circuit, the a pair of differential signal of DM is symmetry fully, thereby make the A level point equal the B level point, recover stable state.For example, when differential signal common mode intermediate level is higher, the A level point is higher than the B level point, cause that the operational amplifier output level increases, under the control of the operational amplifier output level that increases, in two voltage-controlled current sources of one data transmitter, the sense of current is that the voltage-controlled current source output current that flows to signal output part reduces, the sense of current is that the voltage-controlled current source output current of flow-out signal output increases, the sense of current of another data transmitter is the voltage-controlled current source output current increase of flow-out signal output simultaneously, the sense of current reduces for the voltage-controlled current source output current that flows into signal output part, thereby reduced the level of the differential signal common mode intermediate level of physical layer interface circuit output, the level that A is ordered equals the B level point, recovers stable state.In like manner as can be known when differential signal common mode intermediate level is on the low side, the A level point is lower than the B level point, cause that the operational amplifier output level reduces, under the control of the operational amplifier output level that reduces, in two voltage-controlled current sources of one data transmitter, the sense of current is that the voltage-controlled current source output current that flows to signal output part increases, the sense of current is that the voltage-controlled current source output current of flow-out signal output reduces, the sense of current of another data transmitter of while is that the voltage-controlled current source output current of flow-out signal output reduces, the sense of current increases for the voltage-controlled current source output current that flows into signal output part, thereby increased the level of the differential signal common mode intermediate level of physical layer interface circuit output, the level that A is ordered equals the B level point, recovers stable state.The method of getting common mode electrical level and voltage median among the present invention is not limited only to method described in the literary composition, also has such as using band gap reference to produce a stable reference voltage, perhaps carries out dividing potential drop or the like method by some active devices.
One specific embodiment, based on the USB1.1PHY interface chip connected mode of SONOS0.13um CMOS technology as shown in Figure 2, two onesize resistance of serial connection on physical layer circuit output difference path, intermediate level is delivered to operational amplifier one input, the intermediate level of another input termination supply voltage of operational amplifier can realize by two same resistance that are connected in series power supply ground equally.The output of operational amplifier feeds back to two data transmitter inside of physical layer circuit, the electric current fan-out capability of the out drive stage of control data conveyer, thus reaching the purpose of adjusting signal output waveform, connected mode is as shown in Figure 3.During work, utilize resistance string to get the common mode intermediate level of physical layer circuit output differential signal, the common input operational amplifier of the intermediate level of this level and supply voltage, the output of operational amplifier is used for adjusting the pipe of PMOS up and down of the out drive stage of two data transmitters, the voltage-controlled current source electric current of NMOS pipe, and the size of regulating the gain of operational amplifier and voltage-controlled current source operating current can be adjusted the sensitivity of feedback.When output waveform is not subjected to various factors influence and when normally exporting, the A level of ordering equals the level that B is ordered as shown in Figure 1, OPA exports stable level, two transmitters are not done any adjustment, when the output appearance is asymmetric, the level that A is ordered is not equal to the level that B is ordered, OPA output can change the output current of corresponding transmitter is regulated, the level of ordering until A equals the level that B is ordered, so just guarantee the strict symmetry of output signal of USB1.1PHY interface circuit, made it to technology, temperature, voltage, the resistivity of load and parasitism or the like influence is more powerful.When the output waveform distortion that causes for various reasons, this kind structure can effectively be corrected distortion, thereby guarantees that the USB internal signal can normally transmit in good condition.
Physical layer interface circuit of the present invention, in the out drive stage of each data transmitter, insert two identical and opposite polarity voltage-controlled current sources of the sense of current, DP, the DM differential signal common mode intermediate level of the signal output part by two data transmitters are poor with the comparative level of the intermediate level of this supply voltage, control the size of the offset current of each voltage-controlled current source output, the corresponding height of regulating the output signal transient level of data transmitter, symmetrical fully until a pair of differential signal of DP, DM of two data transmitter outputs of physical layer interface circuit.Physical layer interface circuit of the present invention utilizes common-mode feedback to suppress the output signal nonlinear distortion, the variation of the relative power supply intermediate level of common mode electrical level that the output waveform asymmetric distortion is caused, convert bias level control output driving current to, can remove the output distortion that various unfavorable factors cause effectively, make the differential signal of physical layer interface circuit output have good symmetry, thereby guarantee the purpose of the intact transmission signals of physical layer interface circuit energy.This physical layer interface circuit can be applied in a flexible way in the Waveform Control of multiple physical layer interface circuit is adjusted.
Claims (4)
1. physical layer interface circuit, comprise two data transmitters, these two data transmitter output DP, the a pair of differential signal of DM, each data transmitter comprises the output signal controlled stage, out drive stage, input signal is adjusted the back through the output signal controlled stage and by out drive stage signal is exported, out drive stage is the push-pull type cmos amplifier, comprise the PMOS pipe, following NMOS pipe, last PMOS pipe, the drain electrode of following NMOS pipe connects signal output part, it is characterized in that, also comprise four voltage-controlled current sources, PMOS pipe on each data transmitter out drive stage, between the source-drain electrode of following NMOS pipe respectively cross-over connection voltage-controlled current source is arranged, two voltage-controlled current source current opposite in direction of each data transmitter, one flows to signal output part, another flow-out signal output, and two voltage controlled current source polarity of each data transmitter are opposite, between two PMOS pipe source-drain electrodes in the out drive stage of two data transmitters two of cross-over connection the voltage-controlled current source sense of current is identical and polarity is identical, between two NMOS pipe source-drain electrode two of cross-over connection the voltage-controlled current source sense of current is identical and polarity is identical; Get the DP of the signal output part of two data transmitters, the common mode intermediate level of DM differential signal, get the intermediate level of physical layer interface circuit supply voltage, get this differential signal common mode intermediate level with the comparative level difference of the intermediate level of this supply voltage control voltage as four voltage-controlled current sources, when differential signal common mode intermediate level is higher than the intermediate level of this supply voltage, in two voltage-controlled current sources of each data transmitter, the output current that the sense of current flows to the voltage-controlled current source of signal output part reduces, the output current of the voltage-controlled current source of sense of current flow-out signal output increases, when differential signal common mode intermediate level is lower than the intermediate level of this supply voltage, in two voltage-controlled current sources of each data transmitter, the output current that the sense of current flows to the voltage-controlled current source of signal output part increases, the output current of the voltage-controlled current source of sense of current flow-out signal output reduces;
Polarity is size of current the changing in the opposite direction with control voltage of two voltage-controlled current sources on the contrary;
The size of current of identical i.e. two voltage-controlled current sources of polarity is identical with the change direction of control voltage.
2. physical layer interface circuit according to claim 1, it is characterized in that, also comprise an operational amplifier, the intermediate level of described differential signal common mode intermediate level, supply voltage connects two inputs of described operational amplifier respectively, and the output level of described operational amplifier is as the control voltage of described four voltage-controlled current sources.
3. physical layer interface circuit according to claim 1 and 2, it is characterized in that, at two substitutional resistances of signal output part serial connection of two data transmitters, export the common mode intermediate level of differential signal as physical layer interface circuit with the level of described two interconnected ends of substitutional resistance.
4. physical layer interface circuit according to claim 1 and 2, it is characterized in that, two substitutional resistances that are connected in series between physical layer interface circuit power supply and ground are with the level of described two interconnected ends of the substitutional resistance intermediate level as the physical layer interface circuit supply voltage.
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| CN2008100437785A CN101674071B (en) | 2008-09-11 | 2008-09-11 | Physical layer interface circuit |
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| CN105099432B (en) * | 2014-05-19 | 2019-04-30 | 奇景光电股份有限公司 | output buffer |
| CN104242714B (en) * | 2014-07-10 | 2018-01-02 | 丁文萍 | A kind of wireless power transmission device high frequency electric source equipment of Class D structures |
| CN104242715B (en) * | 2014-07-10 | 2018-01-19 | 丁文萍 | A kind of wireless power transmission device high frequency electric source equipment of Class E structures |
| CN107518916A (en) * | 2017-06-26 | 2017-12-29 | Tcl医疗超声技术（无锡）有限公司 | A kind of ultrasonic wave transmitting circuit for medical ultrasonic diagnostic |
| CN112968683B (en) * | 2021-03-18 | 2024-11-19 | 中国电子科技集团公司第五十四研究所 | A high-speed multi-mode multi-channel LVCMOS interface circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5945842A (en) * | 1996-06-28 | 1999-08-31 | Nec Corporation | Output circuit for conversion from CMOS circuit level to ECL circuit level |
| CN1971569A (en) * | 2005-11-22 | 2007-05-30 | 上海华虹Nec电子有限公司 | An improved simulation model of high-voltage device and its application method |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5945842A (en) * | 1996-06-28 | 1999-08-31 | Nec Corporation | Output circuit for conversion from CMOS circuit level to ECL circuit level |
| CN1971569A (en) * | 2005-11-22 | 2007-05-30 | 上海华虹Nec电子有限公司 | An improved simulation model of high-voltage device and its application method |
Non-Patent Citations (1)
| Title |
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| JP特开平8-237103A 1996.09.13 |
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