CN101620879A - Operating method for realizing multi-bit data storage of ferroelectric memory - Google Patents
Operating method for realizing multi-bit data storage of ferroelectric memory Download PDFInfo
- Publication number
- CN101620879A CN101620879A CN200910055566A CN200910055566A CN101620879A CN 101620879 A CN101620879 A CN 101620879A CN 200910055566 A CN200910055566 A CN 200910055566A CN 200910055566 A CN200910055566 A CN 200910055566A CN 101620879 A CN101620879 A CN 101620879A
- Authority
- CN
- China
- Prior art keywords
- storage
- voltage
- polarization value
- read
- sat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5657—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using ferroelectric storage elements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
Abstract
本发明提出一种实现铁电存储器多位数据存储的操作方法,属于微电子技术领域,它在铁电存储器存储单元中,通过外加不同的写脉冲电压来使得铁电薄膜相应产生不同大小的剩余极化强度,并相应定义为不同的存储态,再通过一个固定外加正读电压,读取相应的各存储态,从而在单个存储单元中实现多位存储功能。利用本发明多位数据存储的操作方法,使得多位存储器件可以极大地提高存储密度,大大地降低了生产成本。
The invention proposes an operation method for realizing multi-bit data storage of ferroelectric memory, which belongs to the field of microelectronics technology. In the storage unit of ferroelectric memory, different write pulse voltages are applied to make the ferroelectric film correspondingly produce residuals of different sizes. Polarization intensity, and correspondingly defined as different storage states, and then read the corresponding storage states through a fixed external positive read voltage, so as to realize multi-bit storage function in a single memory cell. By using the operation method of the multi-bit data storage of the present invention, the multi-bit storage device can greatly increase the storage density and greatly reduce the production cost.
Description
技术领域 technical field
本发明提供一种实现铁电存储器多位数据存储的操作方法,属于微电子技术领域。The invention provides an operation method for realizing multi-bit data storage of a ferroelectric memory, which belongs to the technical field of microelectronics.
背景技术 Background technique
在半导体市场中,存储器占有极其重要地位。随着便携式电子设备的逐步普及,不挥发存储器的市场也越来越大,目前Flash占不挥发存储器市场的90%。但随着半导体技术的进步,Flash遇到了越来越多的技术瓶颈,隧穿氧化层不能随着集成电路工艺的发展无限制地减薄。解决这个问题的思路是研发新一代不挥发存储器,主要有磁存储器(MRAM),相变存储器(PCM),电阻存储器(ReRAM)和铁电存储器(FeRAM),其中铁电存储器最先实现商品化,具有很强商业潜质。In the semiconductor market, memory occupies an extremely important position. With the gradual popularization of portable electronic devices, the market of non-volatile memory is also increasing. At present, Flash accounts for 90% of the market of non-volatile memory. However, with the advancement of semiconductor technology, Flash has encountered more and more technical bottlenecks, and the tunnel oxide layer cannot be thinned indefinitely with the development of integrated circuit technology. The idea to solve this problem is to develop a new generation of non-volatile memory, mainly including magnetic memory (MRAM), phase change memory (PCM), resistive memory (ReRAM) and ferroelectric memory (FeRAM), among which ferroelectric memory is the first to be commercialized , with strong commercial potential.
铁电存储器在的关键在于其铁电薄膜电容单元。它主要是利用铁电材料具有的自发极化特性,即自发极化方向可以在反向外电场作用下发生反转的性质而实现存储功能。一般铁电存储器采用钙钛矿结构系列的材料,例如锆钛酸铅(PZT)。此材料的主要特征是有铁电特性,即极化方向与外电场之间具有电滞回线的关系。这种特性使之非常适于做存储器,其剩余极化的正负两个状态分别对应着存储器的“0”和“1”态,并可通过改变外电场的方向来改变存储状态或通过外围电路来传感其极化状态,读取信息。The key to ferroelectric memory lies in its ferroelectric thin film capacitor unit. It mainly uses the spontaneous polarization characteristic of ferroelectric materials, that is, the property that the direction of spontaneous polarization can be reversed under the action of a reverse external electric field to realize the storage function. Generally, ferroelectric memories use perovskite structure series materials, such as lead zirconate titanate (PZT). The main feature of this material is that it has ferroelectric properties, that is, there is an electric hysteresis loop relationship between the polarization direction and the external electric field. This feature makes it very suitable for memory, the positive and negative states of the remnant polarization correspond to the "0" and "1" states of the memory, and the storage state can be changed by changing the direction of the external electric field or through the peripheral circuit to sense its polarization state and read the information.
传统的铁电存储单元一般都只用一对绝对值相同的正负脉冲电压产生一对正负极化强度值,来定义“0”与“1”态,在一个铁电存储单元上只能获取单个状态值,即只可实现一位数据存储,资源利用率低,存储效率低。Traditional ferroelectric memory cells generally only use a pair of positive and negative pulse voltages with the same absolute value to generate a pair of positive and negative polarization values to define the "0" and "1" states. Obtain a single state value, that is, only one bit of data storage can be realized, the resource utilization rate is low, and the storage efficiency is low.
发明内容 Contents of the invention
本发明的目的在于提出一种实现铁电存储器多位数据存储的操作方法,提高存储密度,降低生产成本。The object of the present invention is to provide an operation method for realizing multi-bit data storage of ferroelectric memory, improve storage density and reduce production cost.
本发明的技术方案是:一种实现铁电存储器多位数据存储的操作方法,在铁电存储器的铁电薄膜电容存储单元上,通过外加n对电压值不等的正负写脉冲电压±Vi,i=1、2、…、n,得到2n个剩余极化强度值,并相应定义出2n个存储态,再通过外加一个固定正读电压来读取2n个存储态;其读写操作方法如下:The technical solution of the present invention is: an operation method for realizing multi-bit data storage of a ferroelectric memory, on the ferroelectric thin film capacitor storage unit of the ferroelectric memory, by adding n pairs of positive and negative write pulse voltages with different voltage values ±V i , i=1, 2, ..., n, get 2n remanent polarization values, and define 2n storage states accordingly, and then read 2n storage states by adding a fixed positive read voltage; its read and write operations Methods as below:
写操作:以n=2为例,n>2时依此类推;2对电压值不等的外加正负写脉冲电压±V1和±V2,定义:V2>V1>0,可产生4个不同的剩余极化强度值Prj,j=0、1、2、3,对4个剩余极化强度值Prj赋值定义,具体步骤如下:Write operation: take n=2 as an example, and so on when n>2; 2 pairs of positive and negative write pulse voltages ±V 1 and ±V 2 with different voltage values, definition: V 2 >V 1 >0, can be Generate 4 different remanent polarization values P rj , j=0, 1, 2, 3, assign and define the 4 remanent polarization values P rj , the specific steps are as follows:
步骤1:在铁电薄膜电容上外加一个大的正写脉冲电压V2后,使铁电薄膜电容剩余极化强度值为Pr0,定义为存储态“00”;Step 1: After applying a large positive write pulse voltage V 2 to the ferroelectric film capacitor, the remanent polarization value of the ferroelectric film capacitor is P r0 , which is defined as the storage state "00";
步骤2:在铁电薄膜电容上外加一个小的正写脉冲电压V1后,使铁电薄膜电容剩余极化强度值为Pr1,定义为存储态“01”;Step 2: After applying a small positive write pulse voltage V 1 to the ferroelectric film capacitor, the remanent polarization value of the ferroelectric film capacitor is P r1 , which is defined as the storage state "01";
步骤3:在铁电薄膜电容上外加一个小的负写脉冲电压-V1后,使铁电薄膜电容剩余极化强度值为Pr2,定义为存储态“11”;Step 3: After applying a small negative write pulse voltage -V 1 to the ferroelectric film capacitor, the remanent polarization value of the ferroelectric film capacitor is P r2 , which is defined as the storage state "11";
步骤4:在铁电薄膜电容上外加一个大的负写脉冲电压-V2后,使铁电薄膜电容剩余极化强度值为Pr3,定义为存储态“10”;Step 4: after a large negative write pulse voltage -V 2 is applied to the ferroelectric film capacitor, the remanent polarization value of the ferroelectric film capacitor is P r3 , which is defined as the storage state "10";
读操作:通过外加一个固定正读电压,把不同存储态的铁电薄膜的剩余极化强度值Pr都极化到所述固定正读电压对应的饱和极化强度值Psat,从而相应产生不同的差值Psat-Pr,转换成具体电荷量被读操作系统所读取;对应于上述写操作中n=2的例子,四个不同存储态读取信号如下:Read operation: By applying a fixed positive read voltage, the remanent polarization values P r of the ferroelectric thin films in different storage states are polarized to the saturation polarization value P sat corresponding to the fixed positive read voltage, thereby correspondingly generating Different difference values P sat -P r are converted into specific charges and read by the read operating system; corresponding to the example of n=2 in the above write operation, the read signals of four different storage states are as follows:
存储态“00”对应的读取信号差值为Psat-Pr0;The read signal difference corresponding to the storage state "00" is P sat -P r0 ;
存储态“01”对应的读取信号差值为Psat-Pr1;The read signal difference corresponding to the storage state "01" is P sat -P r1 ;
存储态“11”对应的读取信号差值为Psat-Pr2;The read signal difference corresponding to the storage state "11" is P sat -P r2 ;
存储态“10”对应的读取信号差值为Psat-Pr3。The read signal difference corresponding to the storage state "10" is P sat -P r3 .
在写操作中,所述外加写脉冲电压持续时铁电薄膜产生饱和极化强度值;所述外加写脉冲电压消除后铁电薄膜会由饱和极化强度值变为相应的剩余极化强度值Pr。所述铁电薄膜材料的饱和极化强度值和剩余极化强度值Pr与所述外加写脉冲电压值有关。In the write operation, when the external write pulse voltage continues, the ferroelectric film produces a saturation polarization value; after the external write pulse voltage is eliminated, the ferroelectric film will change from the saturated polarization value to the corresponding residual polarization value Pr . The saturation polarization value and the remnant polarization value P r of the ferroelectric thin film material are related to the applied write pulse voltage value.
在读操作中,所述外加固定正读电压值与外加最大正写脉冲电压值相等。所述外加固定正读电压持续时对应产生一个正饱和极化强度值Psat;并且通过差值Psat-Pr的不同来区分各种存储态;只需外加一个固定读电压就能读取不同的存储态。所述差值Psat-Pr引起的电荷量大小由铁电薄膜电容的尺寸大小决定。In a read operation, the applied fixed positive read voltage value is equal to the applied maximum positive write pulse voltage value. When the external fixed positive read voltage is continued, a positive saturation polarization value P sat is correspondingly generated; and various storage states are distinguished by the difference P sat -P r ; only a fixed read voltage can be added to read different storage states. The amount of charge caused by the difference P sat -P r is determined by the size of the ferroelectric film capacitor.
所述存储态的数量2n取决于读操作系统对电荷信号的分辨能力。The number 2n of the storage states depends on the ability of the read operating system to distinguish the charge signal.
本发明铁电存储器多位数据存储的操作方法的优点是:通过外加多对绝对值相等的正负脉冲电压产生多对正负极化强度值,从而在一个铁电存储单元上获取多状态值,即可实现多位数据存储,同时只采用一个外加读电压,读取相应的存储态,设计简单易行,从而简化外加读取电路的逻辑设计成本。本发明大大提高了铁电存储器的存储密度,并同时降低了生产成本。The advantage of the operation method of the multi-bit data storage of the ferroelectric memory of the present invention is: by adding many pairs of positive and negative pulse voltages with equal absolute values to generate many pairs of positive and negative polarization strength values, thereby obtaining multi-state values on a ferroelectric memory unit , can realize multi-bit data storage, and at the same time, only one external read voltage is used to read the corresponding storage state. The design is simple and easy, thereby simplifying the logic design cost of the external read circuit. The invention greatly improves the storage density of the ferroelectric memory and reduces the production cost at the same time.
附图说明 Description of drawings
图1为一个铁电薄膜电容在外加电压下测得的电滞回线图;Fig. 1 is a hysteresis loop diagram measured under an applied voltage for a ferroelectric film capacitor;
图2为一个铁电薄膜电容在不同正负电压下,测得的相应的剩余极化强度值的曲线图;Fig. 2 is a ferroelectric thin film capacitance under different positive and negative voltages, the graph of the corresponding remanent polarization value that measures;
图3为本发明多位数据存储的操作方法的一个实施例所采用的1T1C结构的铁电存储器单元示意图;3 is a schematic diagram of a ferroelectric memory cell with a 1T1C structure used in an embodiment of the operation method for multi-bit data storage of the present invention;
图4为实施例外加写脉冲电压得到的铁电材料电滞回线以及相应定义的四个存储态图;Fig. 4 is the hysteresis loop of the ferroelectric material obtained by adding the writing pulse voltage and four storage state diagrams correspondingly defined;
图5A-5D分别为实施例定义的四个存储态写操作的时序图;5A-5D are respectively timing diagrams of four storage state write operations defined in the embodiment;
图6为实施例读操作的时序图;FIG. 6 is a timing diagram of an embodiment read operation;
图7为实施例读取“01”态的电滞回线示意图;Fig. 7 is a schematic diagram of an electric hysteresis loop for reading the "01" state in the embodiment;
图8为实施例读信息操作统计表。Fig. 8 is a statistics table of reading information operation of the embodiment.
图中标号说明:Explanation of symbols in the figure:
00:一个正电压持续时的饱和极化强度值;00: Saturation polarization value when a positive voltage lasts;
01:一个正电压后的剩余极化强度值;01: Remanent polarization value after a positive voltage;
02:一个大小相同的负电压后的剩余极化强度值;02: Remanent polarization value after a negative voltage of the same size;
001:一个普通电容CB;001: an ordinary capacitor C B ;
002:铁电薄膜电容CFE;002: ferroelectric film capacitor C FE ;
003:铁电薄膜电容CFE的上电极;003: The upper electrode of the ferroelectric film capacitor C FE ;
004:铁电薄膜电容CFE的下电极;004: The lower electrode of the ferroelectric film capacitor C FE ;
005:一个NMOS管(栅极接字线WL,漏极接位线BL,源极接铁电薄膜电容上电极003),005: An NMOS transistor (the gate is connected to the word line WL, the drain is connected to the bit line BL, and the source is connected to the upper electrode 003 of the ferroelectric film capacitor),
010:极板线PL;010: plate line PL;
020:字线WL;020: word line WL;
030:位线BL;030: bit line BL;
101、102、103、104、105、201、202、203、204、205:时段;101, 102, 103, 104, 105, 201, 202, 203, 204, 205: time period;
10:Psat-Pr的差值。10: Difference of P sat -P r .
具体实施方式 Detailed ways
下面结合附图通过实施例对本发明铁电存储器多位数据存储的操作方法进行具体的描述:The operation method of the multi-bit data storage of the ferroelectric memory of the present invention is specifically described below in conjunction with the accompanying drawings:
首先用一个外加电压下测试铁电薄膜电容的电滞回线,当外加电压持续时,会有一个饱和极化强度Psat00;当外加正负电压消除后可分别得到的2个剩余极化强度值01、02,如图1所示。First, test the hysteresis loop of the ferroelectric film capacitor with an applied voltage. When the applied voltage continues, there will be a
在同一个铁电薄膜电容中,通过不同正负电压下可以得到大小不等的剩余极化强度值;此外在正负脉冲电压绝对值相等的情况下,得到的剩余极化强度值差不多相等,并如图2所示。In the same ferroelectric film capacitor, different values of remanent polarization can be obtained under different positive and negative voltages; in addition, when the absolute values of positive and negative pulse voltages are equal, the obtained remanent polarization values are almost equal, And as shown in Figure 2.
本发明实施例(2位,4态数据存储)采用的1T1C结构的铁电存储器单元,如图3。在写操作时,都要使该单元的字线WL020为高电平,让门管005导通,从而使铁电薄膜电容CFE002和位线BL030相接。此外由于门管005有个阈值损失,因此位线030为高电平时都应提升到V+VTN(V为铁电薄膜电容002上所要求的写电压,VTN为门管005的阈值电压),才能使铁电薄膜电容CFE002上所加的电压为所要求的写电压。The ferroelectric memory cell with 1T1C structure adopted in the embodiment of the present invention (2-bit, 4-state data storage), as shown in FIG. 3 . During the write operation, the word line WL020 of the cell must be set at a high level, and the
在实施例中,通过外加两对正负写脉冲电压可以得到其铁电材料电滞回线以及相应定义的四个存储态(图4显示),图中给出了在正负8V和正负4V的外加电压下的4个剩余极化强度值,此外还有8V电压下的的饱和极化强度值,并在参考图4列表展示其具体数值。In the embodiment, by applying two pairs of positive and negative write pulse voltages, the hysteresis loop of the ferroelectric material and four correspondingly defined storage states (shown in FIG. 4 ) can be obtained. The 4 remanent polarization values under the applied voltage of 4V, in addition to the saturation polarization value under the voltage of 8V, and their specific values are shown in a table with reference to Figure 4.
在写操作时,为避免原来的存储态对新写入的存储态的干扰,在每次外加写脉冲电压时,都预先外加一个电压相同、极性相反的脉冲电压进行消除复位。In the write operation, in order to avoid the interference of the original storage state on the newly written storage state, each time the write pulse voltage is applied, a pulse voltage with the same voltage and opposite polarity is applied in advance to eliminate and reset.
写“00”态:101时段,位线030为0电平,字线020开始出现高电平,极板线为0电平,相应使门管005开通,从而使位线030与铁电薄膜电容下电极004连接。102时段位线030为8V+VTN大小的正电平,字线020保持高电平,极板线为0电平,从而在铁电薄膜电容下电极004相当于加了个8V的电压,整个铁电薄膜电容002等效外加一个-8V的预反向极化电压,从而避免此单元的原来存储态干扰将要写入的存储态;103时段位线030为0电平,字线020保持高电平,极板线010加个8V的正脉冲电压,从而在铁电薄膜电容002上等效外加个8V正脉冲电压,并把铁电薄膜极化在8V下的正饱和极化状态;104时段,位线030为0电平,字线020保持高电平,极板线为0电平,从而使铁电薄膜由8V下的正饱和极化状态减小为8V下的剩余极化状态Pr0,即实现了写入”00”态;105时段,位线030为0电平,字线020为0电平,极板线为0电平,门管005关闭,一个写操作周期结束,如图5A所示。Write "00" state: 101 period, the
写“01”态:101时段,位线030为0电平,字线020开始出现高电平,极板线为0电平,使门管005开通,从而使位线030与铁电薄膜电容下电极004连接。102时段位线030为4V+VTN大小的正电平,字线020保持高电平,极板线为0电平,从而在铁电薄膜电容下电极004相当于加了个4V的电压,整个铁电薄膜电容002等效外加一个-4V的预反向极化电压,从而避免此单元的原来存储态干扰将要写入的存储态;103时段位线030为0电平,字线020保持高电平,极板线010加个4V的正脉冲电压,从而在铁电薄膜电容002上等效外加个4V正脉冲电压,并把铁电薄膜极化在4V下的正饱和极化状态;104时段,位线030为0电平,字线020保持高电平,极板线为0电平,从而使铁电薄膜由4V下的正饱和极化状态减小为4V下的剩余极化状态Pr1,即实现了写入”01”态;105时段,位线030为0电平,字线020为0电平,极板线为0电平,门管005关闭,一个写操作周期结束,如图5B所示。Write "01" state: 101 period, the
写“11”态:101时段,位线030为0电平,字线020开始出现高电平,极板线为0电平,使门管005开通,从而使位线030与铁电薄膜电容下电极004连接。102时段位线030为0电平,字线020保持高电平,极板线为4V电平,从而在铁电薄膜电容上电极003相当于加了个4V的电压,整个铁电薄膜电容002等效外加一个4V的预反向极化电压,从而避免此单元的原来存储态干扰将要写入的存储态;103时段位线030为4V+VTN电平,字线020保持高电平,极板线010为0电平,从而在铁电薄膜电容002上等效外加个大小为4V的负脉冲电压,并把铁电薄膜极化在-4V下的负饱和极化状态;104时段,位线030为0电平,字线020保持高电平,极板线为0电平,从而使铁电薄膜由-4V下的负饱和极化状态减小为-4V下的剩余极化状态Pr2,即实现了写入”11”态;105时段,位线030为0电平,字线020为0电平,极板线为0电平,门管005关闭,一个写操作周期结束,如图5C所示。Write "11" state: 101 period, the
写“10”态:101时段,位线030为0电平,字线020开始出现高电平,极板线为0电平,使门管005开通,从而使位线030与铁电薄膜电容下电极004连接。102时段位线030为0电平,字线020保持高电平,极板线为8V电平,从而在铁电薄膜电容上电极003相当于加了个8V的电压,整个铁电薄膜电容002等效外加一个8V的预反向极化电压,从而避免此单元的原来存储态干扰将要写入的存储态;103时段位线030为8V+VTN电平,字线020保持高电平,极板线010为0电平,从而在铁电薄膜电容002上等效外加个大小为8V的负脉冲电压,并把铁电薄膜极化在-8V下的负饱和极化状态;104时段,位线030为0电平,字线020保持高电平,极板线为0电平,从而使铁电薄膜由-8V下的负饱和极化状态减小为-8V下的剩余极化状态Pr3,即实现了写入”10”态;105时段,位线030为0电平,字线020为0电平,极板线为0电平,门管005关闭,一个写操作周期结束,如图5D所示。Write "10" state: 101 period, the
读操作:201时段,位线030为0电平,字线020开始出现高电平,极板线为0电平,使门管005开通,从而使位线030,铁电薄膜电容下电极004,普通电容001三者连接,普通电容001另一端接地。202时段,字线020保持高电平,极板线010为8V,位线030通过铁电薄膜电容002上不同存储态的电容值不同并与一普通电容001串联可读取不同的电压值;203时段,字线020保持高电平,极板线010为8V,位线030的不同电压值可通过外接灵敏放大器放大成区别更明显的不同电压值;204时段,字线020保持高电平,极板线010为0电平,位线030保持由于外接灵敏放大器放大的不同电压值;205时段,字线020保持高电平,极板线010为0电平,位线030已被外电路读取重新转为0电平;此读取是破坏性读出,因此读操作结束后还得重新写入原状态,其重新写入操作在参考图5A-5D中已详细介绍,这样一个读操作结束,如图6所示。Read operation: during
为了方便理解读操作,给出读取“01”态时相应的电滞回线示意图(图7)。其中“01”态的饱和极化与剩余极化差值10可以很清楚地看出外加8V的读电压时,铁电薄膜极化状态发生的变化,进而产生相应的电荷变化,最终引发位线030上电压值变化。In order to facilitate the understanding of the read operation, a schematic diagram of the corresponding electric hysteresis loop when reading the "01" state is given (Fig. 7). The difference between the saturation polarization and the remanent polarization of the "01" state is 10. It can be clearly seen that when an external read voltage of 8V is applied, the polarization state of the ferroelectric film changes, which in turn produces a corresponding charge change, and finally triggers the bit line The voltage value on the 030 changes.
最后对读取操作信息作一个统计表,如图8。表中详细展示了不同的写电压下,定义的存储态,并在8V读电压下的发生的电荷变化,通过不同的电荷变化使同一铁电薄膜电容产生不同的电容,从而最终体现为位线030上不同的电位。Finally, make a statistical table for the read operation information, as shown in Figure 8. The table shows in detail the defined storage states under different write voltages, and the charge changes that occur under the 8V read voltage. Through different charge changes, the same ferroelectric film capacitor produces different capacitances, which are finally reflected as bit lines. Different potentials on 030.
以上阐述的是n=2(2位,4态)铁电存储器多位数据存储的读写操作方法,What set forth above is the read and write operation method of n=2 (2, 4 states) ferroelectric memory multi-bit data storage,
当n>2时,依此类推。例如:当n=3写操作时,3对电压值不等的外加正负写脉冲电压±V1、±V2和±V3,V3>V2>V1>0,可产生6个不同的剩余极化强度值Prj,j=0、1、2、3、4、5,对6个剩余极化强度值Prj赋值定义如下:When n>2, and so on. For example: when n=3 write operations, 3 pairs of positive and negative write pulse voltages ±V 1 , ±V 2 and ±V 3 with different voltage values, V 3 >V 2 >V 1 >0, can generate 6 Different remanent polarization values P rj , j=0, 1, 2, 3, 4, 5, the assignment of the 6 remanent polarization values P rj is defined as follows:
V3对应剩余极化强度值为Pr0,定义为存储态“000”;V 3 corresponds to the remanent polarization value P r0 , which is defined as the storage state "000";
V2对应剩余极化强度值为Pr1,定义为存储态“001”;V 2 corresponds to the remanent polarization value P r1 , which is defined as the storage state "001";
V1对应剩余极化强度值为Pr2,定义为存储态“010”;V 1 corresponds to the remanent polarization value P r2 , which is defined as the storage state "010";
-V1对应剩余极化强度值为Pr3,定义为存储态“011”;-V 1 corresponds to the remanent polarization value P r3 , which is defined as the storage state "011";
-V2对应剩余极化强度值为Pr4,定义为存储态“100”;-V 2 corresponds to the remanent polarization value P r4 , which is defined as the storage state "100";
-V3对应剩余极化强度值为Pr5,定义为存储态“101”。-V 3 corresponds to the remanent polarization value P r5 , which is defined as the storage state “101”.
对应于上述写操作中n=3的例子,通过外加一个固定正读电压V3,可得到6个不同存储态读取信号如下:Corresponding to the above example of n=3 in the write operation, by applying a fixed positive read voltage V 3 , six read signals of different storage states can be obtained as follows:
存储态“000”对应的读取信号差值为Psat-Pr0;The read signal difference corresponding to the storage state "000" is P sat -P r0 ;
存储态“001”对应的读取信号差值为Psat-Pr1;The read signal difference corresponding to the storage state "001" is P sat -P r1 ;
存储态“010”对应的读取信号差值为Psat-Pr2;The read signal difference corresponding to the storage state "010" is P sat -P r2 ;
存储态“011”对应的读取信号差值为Psat-Pr3;The read signal difference corresponding to the storage state "011" is P sat -P r3 ;
存储态“100”对应的读取信号差值为Psat-Pr4;The read signal difference corresponding to the storage state "100" is P sat -P r4 ;
存储态“101”对应的读取信号差值为Psat-Pr5。The read signal difference corresponding to the storage state "101" is P sat -P r5 .
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200910055566A CN101620879A (en) | 2009-07-29 | 2009-07-29 | Operating method for realizing multi-bit data storage of ferroelectric memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200910055566A CN101620879A (en) | 2009-07-29 | 2009-07-29 | Operating method for realizing multi-bit data storage of ferroelectric memory |
Publications (1)
Publication Number | Publication Date |
---|---|
CN101620879A true CN101620879A (en) | 2010-01-06 |
Family
ID=41514061
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200910055566A Pending CN101620879A (en) | 2009-07-29 | 2009-07-29 | Operating method for realizing multi-bit data storage of ferroelectric memory |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN101620879A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2012074776A2 (en) | 2010-11-30 | 2012-06-07 | Radiant Technologies, Inc. | Analog memories utilizing ferroelectric capacitors |
CN106575702A (en) * | 2014-08-19 | 2017-04-19 | 沙特基础工业全球技术公司 | Non-volatile ferroelectric memory cells with multilevel operation |
CN111223873A (en) * | 2020-01-16 | 2020-06-02 | 华中科技大学 | Asymmetric ferroelectric functional layer array and preparation method of ferroelectric tunnel junction multi-valued memory cell |
CN111402939A (en) * | 2020-03-26 | 2020-07-10 | 珠海拍字节信息科技有限公司 | Ferroelectric memory and method of operating the same |
CN113808639A (en) * | 2021-09-24 | 2021-12-17 | 电子科技大学 | Ferroelectric memory cell read-write characteristic verification circuit structure |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1201239A (en) * | 1997-05-30 | 1998-12-09 | 日本电气株式会社 | Semiconductor memory device capable of storing multi-bit data in one memory cell |
EP1403876A1 (en) * | 2002-09-30 | 2004-03-31 | Texas Instruments Incorporated | Ferroelectric memory with wide operating voltage and multi-bit storage per cell |
US20050024913A1 (en) * | 2003-07-30 | 2005-02-03 | Hynix Semiconductor Inc. | Nonvolatile ferroelectric memory device having a multi-bit control function |
US7038934B2 (en) * | 2001-12-13 | 2006-05-02 | Hynix Semiconductor Inc. | Nonvolatile ferroelectric memory device and method for storing multiple bit using the same |
-
2009
- 2009-07-29 CN CN200910055566A patent/CN101620879A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1201239A (en) * | 1997-05-30 | 1998-12-09 | 日本电气株式会社 | Semiconductor memory device capable of storing multi-bit data in one memory cell |
US7038934B2 (en) * | 2001-12-13 | 2006-05-02 | Hynix Semiconductor Inc. | Nonvolatile ferroelectric memory device and method for storing multiple bit using the same |
EP1403876A1 (en) * | 2002-09-30 | 2004-03-31 | Texas Instruments Incorporated | Ferroelectric memory with wide operating voltage and multi-bit storage per cell |
US20050024913A1 (en) * | 2003-07-30 | 2005-02-03 | Hynix Semiconductor Inc. | Nonvolatile ferroelectric memory device having a multi-bit control function |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2012074776A2 (en) | 2010-11-30 | 2012-06-07 | Radiant Technologies, Inc. | Analog memories utilizing ferroelectric capacitors |
CN103262170A (en) * | 2010-11-30 | 2013-08-21 | 拉迪安特技术公司 | Analog memories utilizing ferroelectric capacitors |
EP2647009A4 (en) * | 2010-11-30 | 2016-05-11 | Radiant Technologies Inc | Analog memories utilizing ferroelectric capacitors |
CN106575702A (en) * | 2014-08-19 | 2017-04-19 | 沙特基础工业全球技术公司 | Non-volatile ferroelectric memory cells with multilevel operation |
CN106575702B (en) * | 2014-08-19 | 2018-05-22 | 沙特基础工业全球技术公司 | Nonvolatile ferroelectric memory unit with multistage operations |
US10068630B2 (en) | 2014-08-19 | 2018-09-04 | Sabic Global Technologies B.V. | Non-volatile ferroelectric memory cells with multilevel operation |
CN111223873A (en) * | 2020-01-16 | 2020-06-02 | 华中科技大学 | Asymmetric ferroelectric functional layer array and preparation method of ferroelectric tunnel junction multi-valued memory cell |
WO2021143187A1 (en) * | 2020-01-16 | 2021-07-22 | 华中科技大学 | Method for fabricating asymmetric ferroelectric functional layer array and ferroelectric tunnel junction multi-value storage unit |
CN111223873B (en) * | 2020-01-16 | 2022-08-05 | 华中科技大学 | Asymmetric ferroelectric functional layer array and preparation method of ferroelectric tunnel junction multi-valued memory cell |
CN111402939A (en) * | 2020-03-26 | 2020-07-10 | 珠海拍字节信息科技有限公司 | Ferroelectric memory and method of operating the same |
CN111402939B (en) * | 2020-03-26 | 2025-02-14 | 无锡舜铭存储科技有限公司 | Ferroelectric memory and operation method thereof |
CN113808639A (en) * | 2021-09-24 | 2021-12-17 | 电子科技大学 | Ferroelectric memory cell read-write characteristic verification circuit structure |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7221600B2 (en) | Arithmetic circuit integrated with a variable resistance memory element | |
US6363002B1 (en) | Ferroelectric memory with bipolar drive pulses | |
TW480490B (en) | Non-volatile memory | |
JP3848772B2 (en) | Ferroelectric random access memory device and memory cell data writing / reading method | |
US11742013B2 (en) | Apparatus and method for controlling erasing data in ferroelectric memory cells | |
US7397687B2 (en) | Ferroelectric memory device having ferroelectric capacitor | |
US9117535B2 (en) | Single sided bit line restore for power reduction | |
JP4350222B2 (en) | Method of operating a ferroelectric memory device | |
JP2018514891A (en) | Setting of reference voltage for data sensing in ferroelectric memory | |
CN101620879A (en) | Operating method for realizing multi-bit data storage of ferroelectric memory | |
WO2015138469A1 (en) | Circuit and method for imprint reduction in fram memories | |
WO2022120910A1 (en) | Ferroelectric memory and storage data reading method thereof | |
JP3720983B2 (en) | Ferroelectric memory | |
Thirumala et al. | Reconfigurable Ferroelectric transistor–Part II: Application in low-power nonvolatile memories | |
Bayram et al. | NV-TCAM: Alternative interests and practices in NVM designs | |
JP4187664B2 (en) | Ferroelectric resistor nonvolatile memory array | |
JP3970846B2 (en) | Enhancement of read signal in ferroelectric memory | |
US8811057B1 (en) | Power reduction circuit and method | |
CN107180649B (en) | Semiconductor memory device and method of operating semiconductor memory device | |
CN110993001B (en) | A kind of double-terminal self-checking write circuit and data writing method of STT-MRAM | |
CN114360596A (en) | Nonvolatile dynamic memory unit | |
CN100390901C (en) | A programming method for single-transistor cell array of ferroelectric dynamic random access memory | |
CN102800358B (en) | Semiconductor memory device | |
CN1245761C (en) | Non-destructive read-out ferroelectric non-volatile multiple state data storaging mode and its storage unit | |
Li et al. | Design and implementation of fefet-based lookup table |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20100106 |