JP3720983B2 - Ferroelectric memory - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a refresh control circuit for a ferroelectric memory (FRAM) having an array of ferroelectric memory cells.
[0002]
[Prior art]
The FRAM is a data destruction read type ferroelectric memory cell (FRAM cell) in which a switching MOS transistor is connected in series to a binary data storage capacitor using a ferroelectric substance between electrodes in a matrix. A memory cell array is provided.
[0003]
Such FRAM has been actively researched and developed in recent years as a semiconductor memory device with low power consumption. For example, US Pat. No. 4,873,664 (Eaton, Jr.) and SSEaton, Jr. et al. Density NVRAMs ", ISSCC Digest of Technical Papers, pp.130-131, Feb.1988.
[0004]
The FRAM is not only nonvolatile but also a memory that can realize low power consumption, high-speed operation, and high number of rewrites. Therefore, the FRAM is expected as a card memory for non-power supply ID devices in addition to a general-purpose memory.
[0005]
Between the electrodes of the information storage capacitor of the FRAM cell, barium strontium titanate ((Ba, Sr) TiO _Three ), Lead zirconate titanate (Pb (Zr, Ti) O) _Three ; PZT), lanthanum-doped lead zirconate titanate ((Pb, La) (Zr, Ti) O _Three PLZT), lithium niobate (LiNbO) _Three ), Strontium tantalate (SrBi), a bismuth layered compound ₂ Ta ₂ O ₉ SBT), a bismuth layered compound, strontium tantalum niobate (SrBi) ₂ (Ta, Nb) ₂ O ₉ A ferroelectric film composed of SBNT) or the like is used.
[0006]
These ferroelectric films are polarized by applying an electric field, and the relationship between the applied voltage and the amount of polarization exhibits a so-called hysteresis characteristic. The film formation method includes MOD, sol-gel, and sputtering. Method, CVD method, reactive vapor deposition method and the like.
[0007]
Problems in securing the reliability of the FRAM include the number of rewrites, long-term recording retention, and environmental resistance. One of the problems that is difficult to improve is the problem of imprinting the FRAM cell. This imprint is a phenomenon in which, when data is written, it is left for a long time or exposed to a high temperature, and an error occurs in that data having a polarity opposite to that of the data is not correctly written. is there.
[0008]
In this imprint, when the ferroelectric film is left for a long time or exposed to a high temperature, mobile charges gather around the polarization domain in a direction that stabilizes the polarization, and as a result, the ferroelectric film has an internal structure. This is caused by a state where an electric field is generated.
[0009]
Since the internal electric field generated in this ferroelectric film is temporarily fixed, imprinting is not a phenomenon that leads to hard errors such as element destruction or aging, but it is a serious problem as a soft error peculiar to FRAM. It has become.
[0010]
[Problems to be solved by the invention]
As described above, in the conventional FRAM, when the ferroelectric film is left for a long time or exposed to a high temperature, mobile charges are collected around the polarization domain in the direction of stabilizing the polarization, and as a result, the ferroelectric film There is a problem that a soft error occurs due to imprint caused by an internal electric field generated in the body film.
[0011]
The present invention has been made to solve the above-mentioned problems, and provides a ferroelectric memory capable of suppressing imprinting and preventing the occurrence of soft errors by introducing a refresh operation for memory cells. Objective.
[0013]
[Means for Solving the Problems]
The ferroelectric memory of the present invention is a memory in which ferroelectric memory cells in which switching transistors are connected in series to a capacitor for storing binary data using a ferroelectric between electrodes are arranged in a matrix. A cell line, a word line commonly connected to the gates of the switching transistors of the memory cells in the same row in the memory cell array, and a plate line commonly connected to the plate electrodes of the capacitors of the memory cells in the same row in the memory cell array; A bit line commonly connected to one end of a switching transistor of memory cells in the same column in the memory cell array, a row decoder for selecting and driving the word line, and a plate line driving circuit for selecting and driving the plate line A sense amplifier provided corresponding to each column of the memory cell array; A column selection gate connected to the gate line, a column decoder that decodes a column address signal to select and drive the column selection gate, and selects an arbitrary memory cell in the memory cell array at a predetermined timing. A data read operation for reading binary data from the selected cell, an opposite data write operation for writing data having a logic level opposite to that of the read binary data to the selected cell, and the same logic level as that of the read data A refresh control circuit for controlling a refresh operation for performing a series of identical data write operations for rewriting binary data in the selected cell so as to be repeated by changing a selected column.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, the basic configuration, characteristics, and write / read principle of the FRAM cell will be described.
[0015]
FIG. 1 is a characteristic diagram showing a relationship (hysteresis curve) between an applied electric field (applied voltage V) and a polarization amount P of a ferroelectric thin film such as a PZT film sandwiched between electrode pairs of a ferroelectric capacitor of an FRAM cell. It is.
[0016]
As can be seen from the hysteresis characteristics shown in FIG. 1, the FRAM cell has a strong state in the state where no electric field is applied to the ferroelectric thin film of the ferroelectric capacitor, that is, in the state where the applied voltage V = 0 (V) between the capacitor electrode pair. Depending on whether the remanent polarization Pr of the dielectric thin film is “positive” or “negative”, the FRAM cell can store binary data, and by using such an array of FRAM cells, a nonvolatile FRAM can be formed. Realized.
[0017]
FIG. 2A shows hysteresis characteristics when data is written in a state where the remanent polarization Pr is “positive” in the ferroelectric capacitor and then left for a long time or exposed to a high temperature. FIG. ) Shows hysteresis characteristics when data is written to the ferroelectric capacitor in a state where the remanent polarization Pr is “negative” and then left for a long time or exposed to a high temperature.
[0018]
In these hysteresis characteristics, the center position is shifted as if a bias potential is applied, and the polarization direction is also shifted. This is because the ferroelectric capacitor has changed to an imprint state. During normal operation of the FRAM cell, such a shift in hysteresis characteristics is not observed.
[0019]
The FRAM cell has a 1T / 1C type configuration including one transistor and one capacitor, and a 2T / 2C type configuration including two transistors and two capacitors.
FIG. 15A shows an equivalent circuit of a 1T / 1C type FRAM cell.
[0020]
This 1T / 1C type FRAM cell is composed of one switch MOS transistor Q and one data storage ferroelectric capacitor C, and a word line WL is connected to the gate of the MOS transistor Q. A bit line BL is connected to one end (drain) of the transistor Q, and a plate line PL is connected to one end (plate) of the capacitor C.
[0021]
FIG. 15B shows an equivalent circuit of a 2T / 2C type FRAM cell.
This 2T / 2C type FRAM cell uses two memory cells shown in FIG. 15A. The first bit line BL is connected to one end of the transistor Q1 of the first cell, and the second Connected to one end of the transistor Q2 of the cell is a second bit line / BL paired with the bit line BL ("/" represents an inverted signal, the same applies hereinafter). A word line WL is commonly connected to the gates of the transistors Q1 and Q2, and a plate line PL is commonly connected to the plate electrodes of the capacitors C1 and C2.
[0022]
A sense amplifier (not shown) for bit line potential sense amplification, a precharge / equalize circuit (not shown) and the like are connected to the two bit lines BL and / BL.
[0023]
FIGS. 3A and 3B show the polarization direction of the ferroelectric capacitor in a state where different data of binary data is written in the 2T / 2C type FRAM cell.
[0024]
FIG. 4A shows the waveform of the plate line applied voltage VPL during normal data writing / data reading operation for a 2T / 2C type FRAM cell.
[0025]
At the time of writing / reading data to / from the FRAM cell, the direction of dielectric polarization is controlled by applying a pulse that changes, for example, 0V → 3V → 0V to the plate line PL of the selected memory cell.
[0026]
Next, the principle of the data write operation and the data read operation of the 2T / 2C type FRAM cell will be described with reference to FIGS. 3 (a), 3 (b) and 4 (a).
[0027]
Here, as shown in FIG. 3A, the capacitor C1 has upward polarization in the figure (polarization in the direction from the plate electrode toward the bit line, hereinafter referred to as positive polarization), and the capacitor C2 has downward polarization in the figure ( A state where polarization in the direction from the bit line toward the plate electrode (hereinafter referred to as negative polarization) appears is defined as data “0”.
[0028]
Further, as shown in FIG. 3B, a state where negative polarization appears in the capacitor C1 and positive polarization appears in the capacitor C2 is defined as data “1”.
<Data writing>
In the data write operation of the 2T / 2C type FRAM cell, in the initial state, the plate line PL is set to the ground potential Vss (0 V), and the two bit lines BL and / BL are precharged to 0 V, respectively. deep.
[0029]
(Write “1”)
First, of the two bit lines BL and / BL, the first bit line BL is set to 3V, and 3V is applied to the word line WL to turn on the two transistors Q1 and Q2.
[0030]
As a result, a potential difference is generated between both ends of the first capacitor C1, and the polarization is in the state of point a in FIG. 1. As shown in FIG. 3B, the downward polarization (negative polarization) in the figure is generated. appear. On the other hand, the second capacitor C2 has no potential difference between both ends, and its polarization is in the state of point b in FIG.
[0031]
Next, when the plate line PL is set to 3V, the potential difference between both ends of the first capacitor C1 becomes 0V, and the polarization is in the state of point b in FIG. On the other hand, the second capacitor C2 has a potential difference between both ends, and its polarization is in a state of point c in FIG. 1, and as shown in FIG. 3B, upward polarization (positive polarization) in the figure. ) Occurs.
[0032]
Next, when the plate line PL is set to 0V, a potential difference is generated between both ends of the first capacitor C1, the polarization is in the state of point a in FIG. 1, and the potential difference between the both ends of the second capacitor C2 is set. The voltage becomes 0 V, and the polarization is in the state of point d in FIG. Thereafter, the word line WL is set to 0 V, and the two transistors Q1 and Q2 are turned off.
[0033]
With the above operation, the two capacitors C1 and C2 are polarized in opposite directions (negative polarization in C1 and positive polarization in C2), and “1” writing is realized.
[0034]
(Write “0”)
Contrary to the above “1” write, first, the second bit line BL of the two bit lines BL, / BL is set to 3 V, 3 V is applied to the word line WL, and two transistors Q1 are applied. , Q2 is turned on.
[0035]
As a result, a potential difference is generated between both ends of the second capacitor C2, and the polarization is in the state of point a in FIG. 1, and downward polarization (negative polarization) in the figure is caused as shown in FIG. appear. On the other hand, the first capacitor C1 has no potential difference between both ends, and its polarization is in the state of point b in FIG.
[0036]
Next, when the plate line PL is set to 3V, the potential difference between both ends of the second capacitor C2 becomes 0V, and the polarization is in the state of point b in FIG. On the other hand, the first capacitor C1 has a potential difference between both ends, and its polarization is in the state of point c in FIG. 1, and as shown in FIG. 3A, upward polarization (positive polarization) in the figure. ) Occurs.
[0037]
Next, when the plate line PL is set to 0 V, a potential difference is generated between both ends of the second capacitor C2, the polarization is in the state of point a in FIG. 1, and the potential difference between the both ends of the first capacitor C1 is set. The voltage becomes 0 V, and the polarization is in the state of point d in FIG. Thereafter, the word line WL is set to 0 V, and the two transistors Q1 and Q2 are turned off.
[0038]
Through the above operation, the two capacitors C1 and C2 are polarized in opposite directions (positive polarization in C1 and negative polarization in C2), and “0” writing is realized.
[0039]
<Reading data>
In the data read operation of the 2T / 2C type FRAM cell, the polarization directions held in the opposite directions to the two ferroelectric capacitors C1 and C2 are read and read from the relationship between the two directions. Data “1” and “0” are discriminated.
[0040]
That is, in the initial state, the plate line PL is set to 0V, and the two bit lines BL and / BL are precharged to 0V. Here, it is assumed that data in a state where polarizations in opposite directions are generated is written in the two capacitors C1 and C2, for example, as shown in FIG.
[0041]
First, when the plate line PL is set to 3V and 3V is applied to the word line WL to turn on the two transistors Q1 and Q2, a potential difference is generated between both ends of the second capacitor C2, and the polarization of the two transistors Q1 and Q2 is changed. Although the direction is reversed, the polarization direction of the first capacitor C1 is not reversed. The read potentials from the two capacitors C1 and C2 are sense-amplified by the sense amplifier, so that the two bit lines BL and / BL are set to 0 V and 3 V correspondingly, and based on the output of the sense amplifier. It is determined whether the read data is “1” or “0”.
[0042]
Subsequently, when the plate line PL is set to 0 V, a potential difference is generated between both ends of the second capacitor C2, the direction of polarization is reversed, and the direction of polarization of the first capacitor C1 is not reversed. Return.
[0043]
That is, when the data read operation is completed, the data in the FRAM cell remains destroyed, and therefore, an operation (rewrite) for writing the same data as the read data is performed.
[0044]
The writing / reading on the 1T / 1C type FRAM cell is basically performed in the same manner as the above-described writing / reading on the 2T / 2C type FRAM cell. The 1T / 1C type FRAM cell obtains data by comparing a signal voltage read in accordance with the polarization direction of one ferroelectric capacitor C1 with, for example, a reference voltage generated from a reference cell. be able to.
[0045]
Next, the FRAM and its refresh control method according to the first embodiment of the present invention will be described.
5 and 6 are block diagrams schematically showing the column system, row system, and refresh control circuit system of the FRAM according to the first embodiment.
[0046]
FIG. 7A is a timing waveform diagram showing the setting operation of the FRAM refresh operation mode in FIG. 5 and FIG. FIG. 7B is a timing waveform diagram showing internal signals in the FRAM refresh operation mode in FIGS.
[0047]
In FIG. 5, 10 is a memory cell array in which data destruction read type FRAM cells are arranged in a matrix, 11 is a sense amplifier (S / A) provided corresponding to each column of the memory cell array, and 12 is a column. Decoders (CD) and 13 are column selection gates (CG) for selecting a column of the memory cell array 10 based on a decode signal from the column decoder 12, and DQ is a data line.
[0048]
14 is a column address buffer to which a column address signal is input, 15 is a column predecoder that predecodes the column address signal from the column address buffer 14 and inputs it to the column decoder 12, and 16 is a column from the column address buffer 14. A column address transition detection (ATD) circuit for detecting transition of the address signal, / CENB is a control signal (column enable signal) for controlling the operation of the ATD circuit 16, and 17 is a detection output signal of the ATD circuit 16. The data line buffer for transferring data to and from the sense amplifier 11 through the data line DQ and the column selection gate 13, and RWD are connected to the data line buffer 17. Write data line, 18 is the read An input / output (I / O) circuit connected to the write data line RWD, 19 is a reverse data transfer circuit connected to the read / write data line RWD, and 20 is write data of the read / write data line RWD. An original data transfer circuit connected to the line.
[0049]
The reverse data transfer circuit 19 is controlled in operation by a refresh control signal FREF, takes in cell data read from the memory cell array 10 to the read data line of the read / write data line RWD, and has its binary level. The reverse data having the reverse level is transferred to the write data line of the read / write data line RWD.
[0050]
The operation of the original data transfer circuit 20 is controlled following the operation of the reverse data transfer circuit 19, and the reverse level of the binary level of the reverse data (that is, the cell read to the read data line) The original data having the same level as the data) is transferred to the write data line of the read / write data line RWD.
[0051]
In FIG. 6, reference numeral 21 denotes a / WE input buffer circuit which receives a control signal input / WE (write enable) for permitting a write operation and generates an internal signal WINT.
[0052]
Reference numeral 22 denotes a / CE input buffer circuit which receives a control signal input / CE (chip enable) for permitting the operation of the FRAM chip and generates an internal signal CINT.
[0053]
Upon receiving the signals WINT and CINT and detecting that they are activated in a predetermined order, the refresh control signal generation circuit 23 generates (activates) a refresh control signal FREF for starting a refresh operation.
[0054]
When the FREF is input, the counter address transfer circuit 24 generates a short-time pulse signal FTRS and outputs it to the address counter 25. The address counter 25 receives the FTRS, starts a count operation, and generates a refresh address signal.
[0055]
The row address signal of the refresh address signal is input to the row decoder 26 for selecting a row of the memory cell array (10 in FIG. 5), and the column address signal of the refresh address signal is the column address buffer ( Input in 14) of FIG.
[0056]
As a result, the memory cell array 10 sequentially designates rows by the output signal (word line drive signal) of the row decoder 26 and is selected during a period when a certain row is selected (as long as / CE is active). A column (column) (12 in FIG. 5) sequentially designates a column at a high speed.
[0057]
In other words, the column decoder (12 in FIG. 5) has a function as a column access control circuit for accessing the column address in the column direction in the memory cell array 10 at high speed.
[0058]
5 and 6, the refresh control signal generation circuit 23, the counter address transfer circuit 24, the address counter 25, the column address transition detection circuit 16, the data line buffer 17, and the read / write data line RWD. Then, the reverse data transfer circuit 19 and the original data transfer circuit 20 select the arbitrary row in the cell array 10 at a predetermined timing and read the binary data from the memory cell of the selected row. A refresh operation for sequentially performing a series of a reverse data write operation for writing data having a logic level opposite to that of binary data to the memory cell, and a same data write operation for rewriting binary data having the same logic level as the read data. Configures a refresh control circuit system that repeats by changing the selected row To have.
[0059]
FIG. 8 is a circuit diagram showing a part of FIGS. 5 and 6 in detail.
The memory cell array is divided into, for example, four cell arrays 31, 32, 33, and 34, which are arranged in parallel. In these cell arrays 31, 32, 33, and 34, as described above, a data destructive read type in which a switch MOS transistor is connected in series to a binary data storage capacitor using a ferroelectric film between electrodes. FRAM cells are arranged in a matrix.
[0060]
WL is a word line (for example, polysilicon wiring) commonly connected to the gates of the switching transistors of the memory cells in the same row in the cell arrays 31, 32, 33, and 34. In this example, only one is shown as a representative. Yes.
[0061]
PL is provided separately for each of the cell arrays 31, 32, 33, and 34, and is a plate line that is commonly connected to the plate electrodes of the capacitors of the memory cells in the same row. Only shows.
[0062]
BL is a bit line commonly connected to one end of the switching transistor of the memory cell in the same column in each of the memory cell arrays 31, 32, 33, and 34. In this example, BL is a representative for each of the cell arrays 31, 32, 33, and 34. Only one is shown.
[0063]
Reference numeral 40 denotes a row decoder (RD) that selects a part of a plurality of word lines WL according to an address signal input from the outside and supplies a word line voltage (drives the word line). Are shared by the cell arrays 31, 32, 33 and 34.
[0064]
35, 36, 37, 38 are arranged on one end side in the row direction corresponding to each of the cell arrays 31, 32, 33, 34, and a plurality of plate lines PL are provided for each of the memory cell arrays 31, 32, 33, 34. 2 is a plate line driving circuit (plate decoder PD) for selectively driving a part of them.
[0065]
41, 42, 43, and 44 are arranged on one end side in the column direction corresponding to each of the cell arrays 31, 32, 33, and 34, and connected to the bit line BL for each of the cell arrays 31, 32, 33, and 34. This is a sense amplifier (SA) circuit that amplifies a minute potential difference appearing on a bit line.
[0066]
Columns 51, 52, 53, 54 are connected to the bit line BL for each of the cell arrays 31, 32, 33, 34 and are controlled by the column selection line CSL to selectively connect the bit line and the data line 55. A selection gate (CG) circuit.
[0067]
Reference numeral 56 denotes a column decoder (CD) that selects the column selection gate circuits 51, 52, 53, and 54 according to an address signal input from the outside and drives the column selection line CSL.
[0068]
A data line sense amplifier circuit 57 amplifies data on the data line 55.
FIG. 9 is a circuit diagram showing a part of the cell arrays 31, 32, 33, and 34 and peripheral circuits in FIG.
[0069]
Each plate line drive circuit 35, 36, 37, 38 is composed of a two-input NAND circuit and an inverter circuit, and the inverter circuit of each plate line drive circuit 35, 36, 37, 38 corresponds to the corresponding cell array 31, 32, 33. , 34 is supplied with a power supply voltage to the plate lines CPL1, CPL2, CPL3, CPL4.
[0070]
Plate control lines PLC1 to PLC4 are arranged in the column direction corresponding to the plate line drive circuits 35, 36, 37, and 38, respectively. The plate control lines PLC1 to PLC4 correspond to the plate control line drive. Driven by the circuits 62, 63, 64, 65.
[0071]
The plate control line drive circuits 62, 63, 64, 65 are connected to one input terminals of the two input NAND circuits of the plate line drive circuits 35, 36, 37, 38, respectively, A word line WL is commonly connected to the other input terminal of the NAND circuit.
[0072]
The plate control line drive circuits 62, 63, 64 and 65 are composed of a two-input NAND circuit and an inverter circuit, and a plate line drive enable control signal PLC is input to one input terminal of the two-input NAND circuit. On the other input terminal, a plate line drive timing signal φ and a signal delayed by predetermined delay times D1, D2, and D3 by delay gates 66, 67, and 68 are input correspondingly.
[0073]
Accordingly, the plate control line driving circuits 62, 63, 64, 65 sequentially drive the corresponding cell array 31, 32, 33, 34 by sequentially driving the corresponding plate line driving circuits 35, 36, 37, 38. It has become.
[0074]
FIG. 10 shows a specific example of the refresh control signal generation circuit 23 in FIG.
In FIG. 10, 101 is a first inverter that inverts the signal WINT input from the / WE input buffer 21, 102 is a second inverter that inverts the signal CINT input from the / CE input buffer 22, and 103 is the first inverter. And a third inverter 104 that inverts the output of the second inverter 102, and the switch control is performed by a complementary signal output from the second inverter 102 and the third inverter 103. The output of the first inverter 101 is input to one end. CMOS transfer gate 105, a latch circuit for latching the signal at the other end of the CMOS transfer gate 104, 106 a NAND circuit to which the output of the latch circuit 105 and the output of the third inverter 103 are input, 107 is the above-mentioned The output of the NAND circuit 106 is inverted to A fourth inverter for outputting a threshold control signal FREF.
[0075]
FIG. 11 shows a specific example of the counter address transfer circuit 24 in FIG.
In FIG. 11, reference numeral 111 denotes an odd-stage delay circuit that delays and inverts the signal FREF input from the refresh control signal generation circuit 23 to generate an inverted delay signal, and 112 denotes a NAND that receives the signal FREF and the inverted delay signal. A circuit 113 is a first inverter that inverts the output of the NAND circuit 112 and outputs the pulse signal FTRS, and 114 is a second inverter that inverts the output of the first inverter 113 and outputs an inverted signal / FTRS. It is an inverter.
[0076]
FIG. 12 shows a specific example of one stage of the address counter circuit 25 in FIG.
In FIG. 12, 121 to 122 are clocked inverters driven when complementary signals Cj-1 and / Cj-1 are correspondingly activated / deactivated, and 123 to 124 are complementary signals Cj-1 and / Cj. -1 and a clocked inverter whose operation is controlled by a clock signal Cj-1, 125 to 127 are inverters, which constitute a master-slave type flip-flop (F / F) and are complementary to the next stage circuit. Signals Cj and / Cj are output.
[0077]
FIG. 13 shows a specific example of the reverse data transfer circuit 19 in FIG.
In FIG. 13, reference numeral 131 denotes a first inverter that inverts the column enable signal / CENB that informs that the charging / discharging of the bit line BL has ended, and 132 denotes an output of the first inverter and the refresh control signal generation circuit 23. The first NAND circuit to which the signal FREF from the input signal is input, 133 is a second inverter that inverts the output of the first NAND circuit 132 and outputs the signal DDW, and 134 is the output of the second inverter 133 that is delayed. An odd-numbered delay circuit that generates an inverted delay signal by being inverted, 135 is a second NAND circuit to which the output of the second inverter 133 and the inverted delay signal are input, and 136 is an output of the second NAND circuit 135. The third inverter 137 for inverting the output and outputting the reverse data transfer control signal DW is the third inverter Inverts the output of inverter 136 is a fourth inverter for outputting an inverted signal / DW.
[0078]
The complementary signals DW and / DW switch control the clocked inverters 138 and 139 for the reverse data transfer gates respectively inserted into the read / write data line RWD and the read / write data line / RWD complementary to the read / write data line RWD. Used to do.
[0079]
FIG. 14 is a circuit showing a specific example of the original data transfer circuit 20 in FIG.
In FIG. 14, 141 is an even-numbered delay circuit that delays the signal DDW inputted from the inverse data transfer circuit 19, and 142 is an odd-numbered stage that delays and inverts the output of the delay circuit 141 to generate an inverted delay signal. 143 is a NAND circuit to which the output of the delay circuit 141 and the inverted delay signal are input, 144 is a first inverter that inverts the output of the NAND circuit 143 and outputs the same data transfer control signal MW, 145 This is a second inverter that inverts the output of the first inverter 144 and outputs an inverted signal / MW.
[0080]
The complementary signals MW and / MW switch control the clocked inverters 146 and 147 for the original data transfer gate respectively inserted into the read / write data line RWD and the read / write data line / RWD which is complementary to the read / write data line RWD. Used to do.
[0081]
Next, the refresh control operation of the FRAM according to the first embodiment shown in FIGS. 5 to 14 will be described with reference to FIG.
In the first embodiment, control is performed so that the refresh operation is started at a timing based on a control signal input from the outside of the FRAM.
[0082]
That is, as shown in FIG. 7, after / WE becomes active (in this example, “L” level), / CE becomes active (in this example, “L” level). When entering CE), the refresh control signal generation circuit 23 shown in FIG. 10 outputs the refresh control signal FREF to start the refresh operation.
[0083]
Thereby, the counter address transfer circuit 24 shown in FIG. 11 outputs the pulse signal FTRS, and the address counter circuit 25 in FIG. 6 starts the counting operation. Then, in a state where a row address of the memory cell array 10 is selected while a certain row address is designated, the column address is C ₀ , C ₁ , C ₂ , C _Three ..., C _n And the selected cell is switched.
[0084]
In this process, first, binary data is read out from the selected cell. In this case, the column circuit operates when the ATD circuit 16 in FIG. 5 receives the column enable signal / CENB informing that the charging / discharging of the bit line BL is completed, and the column address is latched.
[0085]
And the first column address C ₀ The data of the selected cell is read to the data line DQ, and further transferred to the read data line of the read / write data line RWD via the data line buffer 17.
[0086]
At this time, the reverse data transfer circuit 19 shown in FIG. 13 outputs the reverse data transfer control signal DW based on the column enable signal / CENB from the ATD circuit 16 and the signal FREF from the refresh control signal generation circuit 23. Data having a logical level opposite to that of the binary data read to the read data line is sent to the write data line. As a result, a write operation for the selected cell is performed. At this point, the data imprint state, that is, the state of FIG. 2A or 2B can be restored or reduced, that is, the state of FIG.
[0087]
Further, the original data write circuit 20 shown in FIG. 14 outputs the same data transfer control signal MW based on the signal DDW from the reverse data write circuit 19, and has the same logic level as the data read to the read data line. The binary data is sent to the write data line. As a result, a write operation is performed on the selected cell (rewrite is performed by the same operation as the read operation).
[0088]
Such a series of operations (refresh operations) is performed by the column address C. ₀ , C ₁ , C ₂ , C _Three ..., C _n The selected column is changed by, and the selected row is changed by the row address, and the process is repeated.
[0089]
Next, a plurality of examples of the FRAM refresh control method according to the second embodiment of the present invention will be described.
<First embodiment>
In the first embodiment, control is performed by the refresh control circuit so that a refresh operation is performed after a predetermined time elapses after the completion of the write operation for each normal data write operation to the selected memory cell.
[0090]
In other words, an FRAM cell is selected, and first, a data read operation is performed on the selected cell to check the original data write state. Based on the result, an opposite data write operation is performed. At this point, the data imprint state, that is, the state of FIG. 2A or 2B can be restored or reduced, that is, the state of FIG. Further, the original data is rewritten, and a series of operations (refresh operations) is completed.
[0091]
<Second embodiment>
In the second embodiment, assuming that the device on which the FRAM is mounted does not have a backup function, the refresh operation is performed when the power supply voltage of the device is raised (that is, when the operating power supply of the FRAM is raised). Control is performed by the refresh control circuit system as described above.
[0092]
The second embodiment is effective in consideration of the fact that the longest time that is left as it is after writing data to the FRAM cell is often the time during which the power supply of the device equipped with the FRAM is turned off. is there.
[0093]
<Third embodiment>
In the third embodiment, it is assumed that the device on which the FRAM is mounted does not have a backup function, and the series of operations is performed when the power supply voltage of the device is lowered (that is, when the operating power supply of the FRAM is lowered). Control is performed by the refresh control circuit so as to perform (refresh operation).
[0094]
As a result, the imprint state during the previous operation can be restored or reduced, and the time that is left as it is after the data has been written to the FRAM cell is within the time until the next power supply voltage rise, That is, the third embodiment is effective because it can be minimized.
[0095]
<Fourth embodiment>
In the fourth embodiment, during the refresh operation in the first to third embodiments, a data write operation opposite to the data read operation in the refresh operation is performed, and pulses having different pulse widths are applied to the plate line PL. Control is performed by the refresh control circuit.
[0096]
<Fifth embodiment>
In the fifth embodiment, during the refresh operation in the first to third embodiments, a data write operation opposite to the data read operation in the refresh operation is performed by applying a pulse having a longer pulse width to the plate line PL. Control is performed by the refresh control circuit so as to do so. Thereby, the reduction effect of the imprint state of data can be heightened.
[0097]
<Sixth embodiment>
In the sixth embodiment, in the refresh operation in the first to third embodiments, the same data write operation is applied to the plate line PL in the same data write operation as the opposite data write operation in the refresh operation. Control is performed by the refresh control circuit. Thereby, the reduction effect of the imprint state of data can be heightened.
[0098]
<Seventh embodiment>
In the seventh embodiment, in the refresh operation in the first to third embodiments, the data write operation opposite to the data read operation in the refresh operation is performed by applying a pulse having a pulse width longer than that of the normal data write operation to the plate line. Control is performed by the refresh control circuit so as to be applied to PL.
[0099]
<Eighth embodiment>
In the eighth embodiment, during the refresh operation in the first to third embodiments, the refresh control circuit controls so that the opposite data write operation in the refresh operation is repeated a plurality of times. Specifically, control is performed so that the data read and rewrite operations are performed in the same manner as the normal data read operation for the selected cell in which the opposite data is written by the opposite data write operation after the data read as described above. do it. Thereby, the reduction effect of the imprint state of data can be heightened.
[0100]
<Ninth embodiment>
In the ninth embodiment, during the refresh operation in the first to third embodiments, the refresh control circuit performs a data write operation opposite to the data read operation in the refresh operation with a bias potential applied. Control is performed by.
[0101]
In this case, the potential VPL of the plate line PL at the time of writing shown in FIG. 4A is set to nV (n <0) and 3V as shown in FIGS. 4B, 4C, and 4D, for example. It is desirable that the height of the pulse applied to the plate PL line is substantially increased. Thereby, the reduction effect of the imprint state of data can be heightened.
[0102]
In the FRAM according to the first embodiment and the second embodiment, the refresh control is performed by paying attention to the fact that the above-described FRAM cell imprint phenomenon is not an element hard error but a soft error. Thus, an operation problem (soft error) of the FRAM cell is prevented from occurring.
[0103]
Since the imprint is a temporary fixation of the internal electric field of the capacitor of the FRAM cell, it can be eliminated by turning the polarization of the capacitor in the opposite direction or by inverting it several times. Therefore, by adding a refresh operation to the FRAM cell, the long-term reliability of the FRAM is dramatically improved.
[0104]
Even if the frequency of the refresh operation is lower than the refresh operation of a dynamic random access memory (DRAM), a sufficient effect can be obtained. This is because the state change of the FRAM cell to the imprint state is 10 times as long as the charge disappears due to leakage in the DRAM cell capacitor. ^Four This is because the state changes more than twice as slowly.
[0105]
In the first place, the power consumption of the FRAM is small, and the increase in the power consumption by the refresh operation is only about 1% at most compared with the power consumption during the normal operation of the FRAM. Since the increase is negligible compared with the power consumption, it is not an operation that influences the power consumption like the refresh operation of the DRAM.
[0106]
Further, the present invention can provide a sufficient effect even when applied only when the power supply voltage is on. In other words, if the present invention is applied when the power supply voltage rises or falls, a refresh operation may not be performed when the power supply voltage is off in a device that does not have a backup power supply.
[0107]
Therefore, the advantage of non-volatility of FRAM is not lost. Of course, if the present invention is applied to a device having a backup power supply even when the power supply voltage is off, after a certain period of time, the reliability will be higher, and the guaranteed temperature of FRAM and the warranty period (usually guaranteed at 85 ° C for 10 years). Further improvement can be achieved.
[0108]
Furthermore, when the present invention is applied at the rise or fall of the power supply voltage, the refresh operation can be normally performed within the time required for the setup of a device such as a personal computer. There is no influence on the lowering time.
[0109]
Further, the present invention is not limited to the data destruction type FRAM as described above, but is also effective when applied to a data nondestructive type FRAM as described below.
Next, as a third embodiment of the present invention, a case where the present invention is applied to an FRAM including a memory cell array in which data non-destructive read type FRAM cells are arranged in a matrix will be described.
[0110]
FIGS. 16A and 16B are an equivalent circuit diagram and a cross-sectional view shown for explaining the configuration and operation principle of an example of the non-destructive memory cell 160. FIG.
In this cell, a voltage is applied between a gate electrode 162 of a ferroelectric film type MFS FET (field effect transistor) using a ferroelectric as a gate insulating film 161 and a substrate 163, whereby a gate insulating film is formed. A certain ferroelectric substance reverses its polarization, and electrons or holes are induced in the channel region between the drain 164 and the source 165 of the transistor depending on the polarization direction, and the threshold voltage of the transistor changes. At this time, information can be read as the magnitude of the drain current value (channel resistance value) at a certain voltage.
[0111]
Depending on the type of the ferroelectric film, an interface layer may be generated and the trap level on the silicon substrate may not be controlled. In this case, an equivalent circuit is shown in FIGS. 17 (a) and 17 (b). A non-destructive memory cell 170 having an MF MIS structure as shown in the figure and a cross-sectional view can be used. In this cell, a gate oxide film 173 and a floating gate layer 174 are provided between a substrate 171 and a ferroelectric gate film 172.
[0112]
In the non-destructive memory cell described above, the word line WL is connected to the gate electrode 175 and the bit line BL is connected to the drain 176. Further, the well region for fixing the substrate potential of the non-destructive memory cell is separated in the bit line direction, or is shared with the cell source 177.
[0113]
Data writing to the non-destructive memory cell is performed by applying an electric field between a word line connected to the gate electrode and the well / source.
[0114]
In addition, data reading from the non-destructive memory cell is performed by selecting a word line connected to the gate electrode and flowing to the bit line by a current detection circuit connected to the bit line connected to the drain. Sense the amount of current.
[0115]
The ferroelectric memory using the data non-destructive read type memory cell as described above also conforms to the first and second embodiments of the ferroelectric memory using the data destructive read type memory cell. It is possible to perform refresh control.
[0116]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a ferroelectric memory that can suppress imprinting and prevent occurrence of a soft error by introducing a refresh operation for a memory cell.
[Brief description of the drawings]
FIG. 1 is a diagram showing a relationship (hysteresis characteristic) between an applied electric field and a polarization amount of a ferroelectric capacitor of a data destruction type memory cell of an FRAM according to a first embodiment of the present invention;
2 is a diagram showing an example of a state in which the hysteresis characteristic of the memory cell in FIG. 1 is shifted; FIG.
FIG. 3 is an equivalent circuit diagram shown for explaining a data write operation of the FRAM cell in FIG. 1;
4 is a waveform diagram showing a waveform of a plate line applied voltage applied to a plate electrode of a ferroelectric capacitor during a data write / read operation of the FRAM cell in FIG. 1;
FIG. 5 is a block diagram schematically showing a column system of the FRAM according to the first embodiment of the present invention.
FIG. 6 is a block diagram schematically showing a row system and a refresh control circuit system of the FRAM according to the first embodiment of the present invention.
7 is a timing waveform chart showing the operation of the circuit of FIG.
FIG. 8 is a circuit diagram showing a part of FIGS. 5 and 6 in detail.
9 is a circuit diagram showing a part of the cell array and peripheral circuits in FIG.
10 is a circuit diagram showing a specific example of a refresh control signal generation circuit in FIG. 6. FIG.
11 is a circuit diagram showing a specific example of the counter address transfer circuit in FIG. 6;
12 is a circuit diagram showing a specific example of the address counter circuit in FIG. 6. FIG.
13 is a circuit diagram showing a specific example of the reverse data transfer circuit in FIG. 5. FIG.
14 is a circuit diagram showing a specific example of the original data transfer circuit in FIG. 5. FIG.
FIG. 15 is an equivalent circuit diagram showing a 1T / 1C type FRAM cell and a 2T / 2C type FRAM cell.
FIG. 16 is a circuit diagram showing an example of a data non-destructive memory cell of an FRAM according to a third embodiment of the present invention.
FIG. 17 is a circuit diagram showing another example of the data non-destructive memory cell of the FRAM according to the third embodiment of the present invention.
[Explanation of symbols]
10: Memory cell array,
11 ... sense amplifier (S / A),
12 ... Column decoder (CD),
13: Column selection gate (CG),
14: Column address buffer,
15 ... column predecoder,
16 ... Column address transition detection (ATD) circuit,
17: Data line buffer,
18 ... I / O circuit,
19: Reverse data transfer circuit,
20 ... Original data transfer circuit,
DQ ... data line,
RWD: Read / write data line,
21 ... / WE input buffer,
22 ... / CE input buffer,
23. Refresh control signal generation circuit,
24 ... Counter address transfer circuit,
25 ... Address counter,
26: Row decoder.

Claims (13)

A memory cell array in which ferroelectric memory cells in which switching transistors are connected in series to a capacitor for storing binary data using a ferroelectric between electrodes are arranged in a matrix;
A word line commonly connected to gates of switching transistors of memory cells in the same row in the memory cell array;
A plate line commonly connected to plate electrodes of capacitors of memory cells in the same row in the memory cell array;
A bit line commonly connected to one end of a switching transistor of memory cells in the same column in the memory cell array;
A row decoder for selecting and driving the word line;
A plate line driving circuit for selecting and driving the plate line;
A sense amplifier provided corresponding to each column of the memory cell array;
A column select gate connected to the bit line;
A column decoder that decodes a column address signal to select and drive the column selection gate;
A data read operation for selecting an arbitrary memory cell in the memory cell array and reading binary data from the selected cell at a predetermined timing. Data having a logical level opposite to the read binary data is given to the selected cell. Refresh control for controlling to repeat a refresh operation in which the same data write operation for rewriting binary data having the same logic level as the read data to the selected cell as a series is changed by changing the selected column. A circuit ,
The refresh control circuit includes:
A refresh control signal generation circuit for generating a refresh control signal based on a control signal input from the outside;
A counter address transfer circuit that receives the refresh control signal and generates a predetermined pulse signal;
An address counter that receives the pulse signal, starts a count operation, generates a refresh address signal, and supplies a row address signal of the refresh address signal to the row decoder;
A column address transition detection circuit which is provided for detecting transition of the column address signal and which is controlled by a predetermined control signal to determine whether the operation is possible;
A data line buffer for controlling operation by a detection output signal of the column address transition detection circuit, and transferring data to and from the sense amplifier via the column selection gate;
A read / write data line connected to the data line buffer;
Connected to the read / write data line, the operation is controlled by the refresh control signal, the cell data read from the memory cell array to the read data line of the read / write data line is taken, and its binary level A reverse data transfer circuit for transferring reverse data having a reverse level to a write data line of the read / write data lines;
The operation is controlled following the operation of the reverse data transfer circuit, connected to the read / write data line, and original data having a level opposite to the binary level of the reverse data is included in the read / write data line. A ferroelectric memory comprising an original data transfer circuit for transferring to a write data line . A memory cell array in which ferroelectric memory cells in which switching transistors are connected in series to a capacitor for storing binary data using a ferroelectric between electrodes are arranged in a matrix;
A word line commonly connected to gates of switching transistors of memory cells in the same row in the memory cell array;
A plate line commonly connected to plate electrodes of capacitors of memory cells in the same row in the memory cell array;
A bit line commonly connected to one end of a switching transistor of memory cells in the same column in the memory cell array;
A row decoder for selecting and driving the word line;
A plate line driving circuit for selecting and driving the plate line;
A sense amplifier provided corresponding to each column of the memory cell array;
A column select gate connected to the bit line;
A column decoder that decodes a column address signal to select and drive the column selection gate;
A data read operation for reading binary data from a selected memory cell by selecting an arbitrary row and column in the memory cell array at a predetermined timing, and data having a logical level opposite to the read binary data The reverse data write operation for writing to the selected cell, and the refresh operation for sequentially performing the same data write operation for rewriting binary data of the same logic level as the read data to the selected cell as a series, repeatedly changing the selected column, And a refresh control circuit for controlling the selected row to be repeated .
The refresh control circuit includes:
A refresh control signal generation circuit for generating a refresh control signal based on a control signal input from the outside;
A counter address transfer circuit that receives the refresh control signal and generates a predetermined pulse signal;
An address counter that receives the pulse signal, starts a count operation, generates a refresh address signal, and supplies a row address signal of the refresh address signal to the row decoder;
A column address transition detection circuit which is provided for detecting transition of the column address signal and which is controlled by a predetermined control signal to determine whether the operation is possible;
A data line buffer for controlling operation by a detection output signal of the column address transition detection circuit, and transferring data to and from the sense amplifier via the column selection gate;
A read / write data line connected to the data line buffer;
Connected to the read / write data line, the operation is controlled by the refresh control signal, the cell data read from the memory cell array to the read data line of the read / write data line is taken, and its binary level A reverse data transfer circuit for transferring reverse data having a reverse level to a write data line of the read / write data lines;
The operation is controlled following the operation of the reverse data transfer circuit, connected to the read / write data line, and original data having a level opposite to the binary level of the reverse data is included in the read / write data line. A ferroelectric memory comprising an original data transfer circuit for transferring to a write data line . A memory cell array in which ferroelectric memory cells in which switching transistors are connected in series to a capacitor for storing binary data using a ferroelectric between electrodes are arranged in a matrix;
A word line commonly connected to gates of switching transistors of memory cells in the same row in the memory cell array;
A plate line commonly connected to plate electrodes of capacitors of memory cells in the same row in the memory cell array;
A bit line commonly connected to one end of a switching transistor of memory cells in the same column in the memory cell array;
A row decoder for selecting and driving the word line;
A plate line driving circuit for selecting and driving the plate line;
A sense amplifier provided corresponding to each column of the memory cell array;
A column select gate connected to the bit line;
A column decoder that decodes a column address signal to select and drive the column selection gate;
Data read operation for selecting an arbitrary memory cell in the memory cell array and reading binary data from the selected cell, opposite data write operation for writing data having a logic level opposite to the read binary data to the selected cell A refresh operation for performing a series of identical data write operations for rewriting binary data having the same logic level as the read data to the selected cell is performed at a timing based on an external control signal, and the refresh operation is performed on the selected column. Refresh control circuit that controls to repeat while changing
And a ferroelectric memory . The ferroelectric memory according to claim 1 or 2 ,
The refresh control signal generation circuit includes an internal signal generated based on a control signal input / WE for permitting a write operation and an internal signal generated based on a control signal input / CE for permitting an operation of the chip. And the refresh control signal is generated when the internal signals are activated in a predetermined order. The ferroelectric memory according to any one of claims 1 to 3 ,
The ferroelectric memory according to claim 1, wherein the refresh control circuit performs control so that the refresh operation is performed after a predetermined elapsed time from the completion of the write operation for each normal data write operation to the selected memory cell. The ferroelectric memory according to any one of claims 1 to 3 ,
The ferroelectric memory according to claim 1, wherein the refresh control circuit performs control so that the refresh operation is performed when a power supply voltage rises. The ferroelectric memory according to any one of claims 1 to 3 ,
The ferroelectric memory according to claim 1, wherein the refresh control circuit controls the refresh operation when the power supply voltage falls. The ferroelectric memory according to any one of claims 5 to 7 ,
A ferroelectric memory characterized in that a data read operation opposite to a data read operation in the refresh operation is performed by applying pulses having different pulse widths to the plate line. The ferroelectric memory according to claim 8 , wherein
A ferroelectric memory, wherein a data write operation opposite to a data read operation in the refresh operation is performed by applying a pulse having a long pulse width to the plate line. The ferroelectric memory according to any one of claims 5 to 7 ,
A ferroelectric memory, wherein the same data write operation is performed by applying a pulse having a longer pulse width to the plate line than the opposite data write operation in the refresh operation. The ferroelectric memory according to any one of claims 5 to 7 ,
A ferroelectric memory characterized in that a data write operation opposite to the data read operation in the refresh operation is performed by applying a pulse having a pulse width longer than that of a normal data write operation to the plate line. The ferroelectric memory according to any one of claims 5 to 7 ,
A ferroelectric memory, wherein an opposite data write operation in the refresh operation is repeated a plurality of times. The ferroelectric memory according to any one of claims 5 to 7 ,
A ferroelectric memory, wherein a data write operation opposite to the data read operation in the refresh operation is performed with a bias potential applied.

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