CN101604684B - Staggered stacked chip package structure with metal pads on the inner leads of the lead frame - Google Patents
Staggered stacked chip package structure with metal pads on the inner leads of the lead frame Download PDFInfo
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- CN101604684B CN101604684B CN2008100996341A CN200810099634A CN101604684B CN 101604684 B CN101604684 B CN 101604684B CN 2008100996341 A CN2008100996341 A CN 2008100996341A CN 200810099634 A CN200810099634 A CN 200810099634A CN 101604684 B CN101604684 B CN 101604684B
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
本发明提供一种导线架的内引脚具有金属焊盘的交错堆叠式芯片封装结构，包含：一个由多个相对排列的内引脚群、多个外引脚群以及一芯片承座所组成的导线架，其中芯片承座配置于多个相对排列的内引脚群之间，且与多个相对排列的内引脚群形成一高度差；一多芯片交错堆叠结构，由多个芯片交错堆叠而成，多芯片交错堆叠结构配置于芯片承座上且与多个相对排列的内引脚群形成电性连接；以及一封装体，包覆多芯片交错堆叠结构及导线架并将多个外引脚群伸出于该封装体外；其特征在于导线架中的内引脚还被覆一绝缘层且绝缘层上再选择性地形成多个金属焊盘。
The present invention provides a staggered stacked chip packaging structure in which the inner pins of a lead frame have metal pads, comprising: a lead frame composed of a plurality of relatively arranged inner pin groups, a plurality of outer pin groups and a chip support, wherein the chip support is arranged between the plurality of relatively arranged inner pin groups and forms a height difference with the plurality of relatively arranged inner pin groups; a multi-chip staggered stacking structure, formed by staggered stacking of a plurality of chips, the multi-chip staggered stacking structure is arranged on the chip support and forms an electrical connection with the plurality of relatively arranged inner pin groups; and a packaging body, covering the multi-chip staggered stacking structure and the lead frame and extending the plurality of outer pin groups out of the packaging body; the characteristic is that the inner pins in the lead frame are also covered with an insulating layer and a plurality of metal pads are selectively formed on the insulating layer.
Description
Technical field
The present invention relates to a kind of multi-chip interleaving stack package structure, particularly relevant for a kind of multi-chip interleaving stack package structure that on the interior pin of lead frame, disposes metal pad.
Background technology
In recent years, semi-conductive last part technology is all carrying out three-dimensional (Three Dimension; Encapsulation 3D) reaches big relatively semiconductor integrated level (Integrated) or capacity of internal memory etc. in the hope of utilizing minimum area.In order to reach this purpose, present stage has developed to send as an envoy to and has reached three-dimensional (Three Dimension with the mode of chip-stacked (chip stacked); Encapsulation 3D).
In the prior art, the stack manner of chip is that a plurality of chips are stacked on the substrate each other, uses the technology (wire bonding process) of wire-bonded that a plurality of chips are connected with substrate then.Figure 1A is the existing the generalized section identical or stack chip packaging structure of close chip size that has.Shown in Figure 1A, existing stack chip packaging structure 100 comprises a circuit substrate (package substrate) 110, chip 120a, chip 120b, a sept (spacer) 130, many leads 140 and a packing colloid (encapsulant) 150.Have a plurality of pads 112 on the circuit substrate 110, and also have a plurality of pad 122a and 122b respectively on chip 120a and the 120b, wherein pad 122a and 122b are arranged on chip 120a and the 120b with kenel (peripheral type) on every side.Chip 120a is disposed on the circuit substrate 110, and chip 120b is disposed at the top of chip 120a via sept 130.The two ends of lead 140 are connected to pad 112 and 122a via wire bonding technique, so that chip 120a is electrically connected at circuit substrate 110.And the two ends of other part lead 140 also are connected to pad 112 and 122b via wire bonding technique, so that chip 120b is electrically connected at circuit substrate 110.Be disposed on the circuit substrate 110 as for 150 of packing colloids, and coat these leads 140, chip 120a and 120b.
Because pad 122a and 122b are arranged on chip 120a and the 120b with kenel on every side; Therefore the direct carries chips 120b of chip 120a; So prior art must be between chip 120a and 120b configuration space thing 130; Make between chip 120a and the 120b at a distance of a suitable distance, in order to the carrying out of follow-up wire bonding technique.Yet the use of sept 130 but causes the thickness of existing stack chip packaging structure 100 to reduce further easily.
In addition, prior art proposes another kind of stack chip packaging structure with different chip sizes, and its generalized section is shown in Figure 1B.Please refer to Figure 1B, existing stack chip packaging structure 10 comprises a circuit substrate (package substrate) 110, chip 120c, chip 120d, many leads 140 and a packing colloid 150.Have a plurality of pads 112 on the circuit substrate 110.The size of chip 120c is greater than the size of chip 120d, and also has a plurality of pad 122c and 122d on chip 120c and the 120d respectively, and wherein pad 122c and 122d are arranged on chip 120c and the 120d with kenel (peripheral type) on every side.Chip 120c is disposed on the circuit substrate 110, and chip 120d is disposed at the top of chip 120c.The two ends of part lead 140 are connected to pad 112 and 122c via wire bonding technique (wire bonding process), so that chip 120c is electrically connected at circuit substrate 110.And the two ends of other part lead 140 also are connected to pad 112 and 122d via wire bonding technique, so that chip 120d is electrically connected at circuit substrate 110.Be disposed on the circuit substrate 110 as for 150 of packing colloids, and coat these leads 140, chip 120c and 120d.
Because chip 120d is less than chip 120c, therefore when chip 120d was disposed on the chip 120c, chip 120d can not cover the pad 122c of chip 120c.But when the prior art chip that a plurality of different sizes are big or small piles up stack chip packaging structure 10 with above-mentioned mode, because the chip size on upper strata must be more little, so stack chip packaging structure 10 has the restriction of piling up quantity of chip.
In above-mentioned two kinds of traditional stack manners; Except there being Figure 1A to use the mode of sept 130; Shortcoming and Figure 1B of causing the thickness of stack chip packaging structure 100 to reduce further easily; Because the chip size on upper strata must be more little, so can produce outside the problem that chip can be restricted in design or when using; Make owing to the chip design on the stack chip packaging structure is complicated day by day that also the circuit on the chip connects necessary wire jumper or cross-line; And then the problem that on technology, produces; For example: when injecting the mould stream of high pressure because carrying out sealing (molding); May cause the plain conductor of these mutual wire jumpers or cross-line to produce displacement and cause short circuit, make the production capacity of stack chip packaging structure or reliability may reduce.
Summary of the invention
Because the shortcoming and the problem of the chip-stacked mode described in the background of invention, the present invention provides a kind of mode of using multi-chip interleaving to pile up, the akin chip stack of a plurality of sizes is built up a kind of encapsulating structure of three-dimensional.
Main purpose of the present invention is to provide the structure that disposes a plurality of metal pads on a kind of interior pin in lead frame again to carry out the structure of multi-chip interleaving stacked package, makes it have preferable circuit design elasticity and better reliability degree by the structure that has increased a plurality of metal pads of configuration on the interior pin.
Another main purpose of the present invention provide a kind of in lead frame the structure of configuration bus frame carry out the structure of multi-chip interleaving stacked package, make it have preferable circuit design elasticity and better reliability degree by the structure that increases total coil holder.
In view of the above; The present invention provides the staggered and stacked chip-packaging structure that has metal pad on a kind of interior pin of lead frame; Comprise: lead frame; Be made up of the interior pin crowd of a plurality of relative arrangements, a plurality of outer pin crowd and a chip bearing, its chips bearing is disposed between the interior pin crowd of a plurality of relative arrangements, and forms a difference in height with the interior pin crowd of these a plurality of relative arrangements; The multi-chip interleaving stacked structure, being staggeredly stacked by a plurality of chips forms, and this multi-chip interleaving stacked structure is disposed on the chip bearing and forms electric connection via the interior pin crowd of many strip metals lead and a plurality of relative arrangements; And packaging body, coat multi-chip interleaving stacked structure and lead frame, and a plurality of outer pin crowd of lead frame stretches out in outside this packaging body; Wherein also be covered on the local location of pins in a plurality of in the lead frame and optionally form a plurality of metal pads again on an insulating barrier and the insulating barrier.
The present invention then provides the conducting wire frame structure that has metal pad on a kind of interior pin; Form by a plurality of interior pin crowd of relative arrangement, a plurality of outer pin crowd and chip bearings of being; The chip bearing is disposed between the interior pin crowd of a plurality of relative arrangements and forms a difference in height with the interior pin crowd of these a plurality of relative arrangements, optionally forms a plurality of metal pads on pin local lining one insulating barrier and this insulating barrier in it is characterized in that.
The present invention then provides the staggered and stacked chip-packaging structure that has metal pad on a kind of interior pin of lead frame again; Comprise: lead frame; Form by the interior pin crowd of a plurality of relative arrangements, a plurality of outer pin crowd and a chip bearing; And the chip bearing forms a difference in height between the pin crowd and with interior pin crowd in being disposed at, and optionally forms a plurality of metal pads on also be covered on the local location of interior pin an insulating barrier and the insulating barrier; The multi-chip interleaving stacked structure, by a plurality of chip-stacked forming, this multi-chip interleaving stacked structure is disposed on the chip bearing and via many strip metals lead and interior pin crowd and forms electric connection; And packaging body, coat multi-chip interleaving stacked structure and lead frame, and the outer pin crowd of lead frame stretches out in outside this packaging body; Wherein comprise at least one total coil holder in the lead frame, be disposed between interior pin crowd and the chip bearing.
Description of drawings
Figure 1A, Figure 1B are the sketch mapes of prior art;
Fig. 2 A and Fig. 2 C are the vertical views of chip structure of the present invention;
Fig. 2 B and Fig. 2 D are the cutaway views of chip structure of the present invention;
Fig. 2 E is the cutaway view of multi-chip interleaving stacked structure of the present invention;
Fig. 3 A, 3B and 3C are sketch mapes of reshuffling layer manufacture process of the present invention;
Fig. 4 A and 4B figure are cutaway views of reshuffling the wire bonds district in the layer of the present invention;
Fig. 5 and Fig. 6 are the cutaway views with the multi-chip interleaving stacked structure of reshuffling layer of the present invention;
Fig. 7 is the vertical view of multi-chip interleaving stacked structure encapsulation of the present invention;
Fig. 8 A, 8B, 8C and 8D are the vertical views of another embodiment of multi-chip interleaving stacked structure encapsulation of the present invention;
Fig. 9 A and 9B are the vertical views of another embodiment of multi-chip interleaving stacked structure encapsulation of the present invention;
Figure 10 is the cutaway view of the multi-chip interleaving stacked structure encapsulation of Fig. 7 of the present invention;
Figure 11 is the cutaway view of an embodiment of multi-chip interleaving stacked structure encapsulation of the present invention;
Figure 12 is the cutaway view of another embodiment of multi-chip interleaving stacked structure encapsulation of the present invention;
Figure 13 is the cutaway view of another embodiment of multi-chip interleaving stacked structure of the present invention;
Figure 14 is the cutaway view of another embodiment of multi-chip interleaving stacked structure of the present invention;
Figure 15 is the cutaway view of another embodiment of multi-chip interleaving stacked structure of the present invention;
Figure 16 is the cutaway view of another embodiment of multi-chip interleaving stacked structure of the present invention;
Figure 17 is the cutaway view of another embodiment of multi-chip interleaving stacked structure of the present invention;
Figure 18 is the cutaway view of another embodiment of multi-chip interleaving stacked structure of the present invention;
Figure 19 is the cutaway view of another embodiment of multi-chip interleaving stacked structure of the present invention; And
Figure 20 is the cutaway view of another embodiment of multi-chip interleaving stacked structure of the present invention.
The primary clustering symbol description:
10,100,400: stack chip packaging structure
110,410: circuit substrate
112,122a, 122b, 122c, 122d: pad
120a, 120b, 120c, 120d: chip
130: sept
140,242,420,420a, 420b: lead
150,430: packing colloid
200: chip
210: the chip active face
220: chip back
230: adhesion coating
240: pad
250: the wire bonds district
260: the wire welding area edge
30: the multi-chip interleaving stacked structure
310: the chip body
312a: first pad
312b: second pad
320: the wire bonds district
330: the first protective layers
332: the first openings
340: reconfiguration line layer
344: the three pads
350: the second protective layers
352: the second openings
300: chip structure
400: reshuffle layer
50: the multi-chip interleaving stacked structure
500 (a, b, c, d): chip structure
600: lead frame
610: interior pin crowd
6101～6104: interior pin
611: insulating barrier
6121～6124: interior pin
613: metal pad
Pin crowd in 615: the first
Pin crowd in 616: the second
617: connecting portion
618: platform part
620: the chip bearing
630: total coil holder
6301～63010: total coil holder
632: insulating barrier
634: metal pad
6341～6343: metal pad
640 (a～n): plain conductor
70: the multi-chip interleaving stacked structure
A～f: pad
A '～f ': pad
Embodiment
The present invention is a kind of mode of using chip to be staggeredly stacked in this direction of inquiring into, the akin chip stack of a plurality of sizes is built up a kind of encapsulating structure of three-dimensional.In order to understand the present invention up hill and dale, detailed step and composition thereof will be proposed in following description.Apparently, enforcement of the present invention does not limit the specific details that the art of chip-stacked mode is had the knack of.On the other hand, the detailed step of last part technologies such as well-known chip generation type and chip thinning is not described in the details, with the restriction of avoiding causing the present invention unnecessary.Yet,, can describe in detail as follows for preferred embodiment of the present invention; Yet except these are described in detail; The present invention can also be implemented among other the embodiment widely, and scope of the present invention constrained not, its with after the claim scope be as the criterion.
In the semiconductor packaging process in modern times, all be a wafer (wafer) of having accomplished FEOL (Front End Process) to be carried out thinning earlier handle (Thinning Process), the thickness of chip is ground between 2～20mil; Then, coating (coating) or wire mark (printing) one deck macromolecule (polymer) material are in the back side of chip again, and this macromolecular material can be a kind of resin (resine), particularly a kind of B-Stage resin.Via a baking or irradiation technology, make macromolecular material present a kind of semi-curing glue again with viscosity; Follow again, an adhesive tape that can remove (tape) is attached on the macromolecular material of semi-solid preparation shape; Then, carry out the cutting (sawing process) of wafer, make wafer become many chip (die); At last, just can many chip be connected with substrate and chip is formed the stacked chips structure.
As with reference to shown in figure 2A and Fig. 2 B, be the floor map and the generalized section of the chip 200 of the aforementioned technology of a completion.Shown in Fig. 2 A, chip 200 has the back side 220 of an active face 210 and a relative active surface, and has formed an adhesion coating 230 on the chip back 220; To stress at this; Adhesion coating 230 of the present invention is not defined as aforesaid semi-curing glue; The purpose of this adhesion coating 230 is engaging with lead frame or chip formation, therefore, so long as have the sticky material of this function; Be enforcement aspect of the present invention, for example: glued membrane (die attached film).In addition; In an embodiment of the present invention, dispose a plurality of pads 240 on the active surface 210 of chip 200, and a plurality of pad 240 has been disposed on the side of chip 200; And a plurality of pads 240 on the active surface 210 of another chip 20 are configured on another side; Stress that at this a plurality of pads 240 on chip 20 and the chip 200 are to be configured on the relative side, please refer to shown in Fig. 2 C and Fig. 2 D.Therefore, can form a kind of multi-chip interleaving stacked structure 30, shown in Fig. 2 E.And when the structure 30 that formation multi-chip interleaving of the present invention piles up; Be with the number of chips that will pile up be foundation; The overlapping area that decides each chip to be staggeredly stacked; For example, when undermost two chip 20a and 200a engaged with adhesion coating 230, chip 200a covered chip 20a alternately greater than area over half; And be covered in chip 200a alternately when going up as chip 20b, its area that is covered in chip 200a then covers the area of chip 20a greater than chip 200a, and the chip on upper strata to cover lower floor's area of chip alternately big more; Simultaneously; Each chip is that alignment line forms with the edge line 260 in wire bonds district 250; Therefore can form similar stair-stepping structure at the dual-side of this multi-chip interleaving stacked structure, the feasible pad that is configured on the chip is not all covered by the chip on upper strata or covers.In addition, be stressed that edge line 260 is actually and does not exist on the chip 200, it is only as a reference line.Explain with a specific embodiment; The size of chip 20 or chip 200 is about 10mm * 13mm * 75um; And the thickness of the adhesion coating 230 at the chip 20 or chip 200 back sides is about 60um, and the substrate thickness of carrying multi-chip interleaving stacked structure is about 200um to 250um; So according to the dimensional structure of said chip, the maximum that the structure that is staggeredly stacked of the present invention is accomplished after piling up is piled up spreading width (overhang): with 6 layers of chip is example, is about 1mm; With 8 layers of chip is that example then can be less than 1.5mm.Be stressed that once more; The quantity and the size thereof of the chip of the structure of piling up for above-mentioned formation multi-chip interleaving; The present invention does not limit; As long as the structure that ability formed multi-chip interleaving according to the previous description piles up is enforcement aspect of the present invention, for example the be staggeredly stacked structure or the structure that is staggeredly stacked of 4 layers of chip of 2 layers of chip.
Explain that then the present invention disposes another embodiment of a plurality of pads on chip 20 or chip 200, be to use a kind of layer (Redistribution Layer that reshuffle in the present embodiment; RDL) with the pad configuration on the chip to a side of chip so that can form the structure that multi-chip interleaving piles up, and the execution mode of this reconfiguration line layer explanation is as follows.
Please refer to Fig. 3 A～Fig. 3 C, be the manufacture process sketch map with chip structure of reconfiguration line layer of the present invention.Shown in Fig. 3 A; Chip body 310 at first is provided; And the single side being adjacent to chip body 310 is cooked up wire bonds district 320; And a plurality of pads 312 on the active surface of chip body 310 are divided into the first pad 312a and the second pad 312b, wherein the first pad 312a is positioned at wire bonds district 320, the second pad 312b and then is positioned at outside the wire bonds district 320.Then please refer to Fig. 3 B, on chip body 310, form first protective layer 330, wherein first protective layer 330 has a plurality of first openings 332, to expose the first pad 312a and the second pad 312b.On first protective layer 330, form reconfiguration line layer 340 then.And reconfiguration line layer 340 comprises many leads 342 and a plurality of the 3rd pads 344; Wherein the 3rd pad 344 is positioned at wire bonds district 320; And these leads 342 extend to the 3rd pad 344 from the second pad 312b respectively, so that the second pad 312b is electrically connected at the 3rd pad 344.In addition, the material of reconfiguration line layer 340 can be gold, copper, nickel, titanizing tungsten, titanium or other electric conducting material.Please refer to Fig. 3 C again; After forming reconfiguration line layer 340, second protective layer 350 is covered on the reconfiguration line layer 340, and the structure of formation chip 300; Wherein second protective layer 350 has a plurality of second openings 352, to expose the first pad 312a and the 3rd pad 344.
Be stressed that; Though the first above-mentioned pad 312a and the second pad 312b are arranged on the active surface of chip body 310 with kenel on every side; Yet the first pad 312a and the second pad 312b also can be arranged on the chip body 310 via face array kenel (area array type) or other kenel, and certain second pad 312b is electrically connected at the 3rd pad 344 via lead 342.In addition; Present embodiment does not limit the arrangement mode of the 3rd pad 344 yet; Though the 3rd pad 344 and the first pad 312a are arranged in two row in Fig. 3 B; And the single side along chip body 310 is arranged, but the 3rd pad 344 and the first pad 312a also can with single-row, multiple row or other mode be arranged in the wire bonds district 320.
Please continue to be the generalized section that is illustrated along hatching A-A ' and B-B ' respectively among Fig. 3 C with reference to figure 4A and Fig. 4 B.Can know that by above-mentioned the 3rd figure chip 300 mainly comprises chip body 310 and reshuffles 400 on layer and form, and wherein reshuffles layer 400 and is formed by first protective layer 330, reconfiguration line layer 340 and 350 of second protective layers.Chip body 310 has wire bonds district 320, and wire bonds district 320 is adjacent to the single side of chip body 310.In addition, chip body 310 has a plurality of first pad 312a and the second pad 312b, and wherein the first pad 312a is positioned at wire bonds district 320, and the second pad 312b is positioned at outside the wire bonds district 320.
First protective layer 330 is disposed on the chip body 310, and wherein first protective layer 330 has a plurality of first openings 332, to expose these the first pad 312a and the second pad 312b.Reconfiguration line layer 340 is disposed on first protective layer 330, and wherein reconfiguration line layer 340 extends in the wire bonds district 320 from the second pad 312b, and reconfiguration line layer 340 has a plurality of the 3rd pads 344, and it is disposed in the wire bonds district 320.Second protective layer 350 is covered on the reconfiguration line layer 340, and wherein second protective layer 350 has a plurality of second openings 352, to expose these first pad 312a and the 3rd pad 344.Because the first pad 312a and the 3rd pad 344 all are positioned at wire bonds district 320; Therefore the zone beyond the wire bonds district 320 on second protective layer 350 just can provide the platform of a carrying; To carry another chip structure; Therefore, can form the structure 30 that a kind of multi-chip interleaving piles up.
Please refer to shown in Figure 5, the structure 50 that a kind of multi-chip interleaving of the present invention piles up.Multi-chip interleaving stacked structure 50 is piled up by a plurality of chips 500 and forms; For example be staggeredly stacked by 4 chips; Wherein have on each chip and reshuffle layer 400, thus can the pad 312b on the chip be disposed on the wire bonds district 320 of chip, and form multi-chip interleaving stacked structure 50.Because the stack manner of multi-chip interleaving stacked structure 50 is identical with above-mentioned multi-chip interleaving stacked structure 30, repeats no more at this.In addition, be to connect between the individual chip 500 of formation multi-chip interleaving stacked structure 50 with the formed adhesion coating 230 of a macromolecular material.
Multi-chip interleaving stacked structure of the present invention is except above-mentioned structure; Be multi-chip interleaving stacked structure 30 and 50; Also can and have the chip 500 of reshuffling layer 400 with chip 20 piles up to form another kind of multi-chip interleaving stacked structure 70 alternately; As shown in Figure 6, it is staggeredly stacked by 6 chips and forms.Because the stack manner of shape multi-chip interleaving stacked structure 70 is identical with the stack manner that forms multi-chip interleaving stacked structure 30 and 50, repeats no more at this.Yet be stressed that; Present embodiment do not limit chip 20 and chip 500 what person on the upper strata or what person in lower floor; The present invention does not limit, and it is enforcement aspect of the present invention so long as form multi-chip interleaving stacked structure of the present invention with chip 20 or chip 200 and chip 500.Simultaneously, also to stress once more, the quantity of the chip of the structure of piling up for above-mentioned formation multi-chip interleaving, the present invention does not limit, and for example shown in Fig. 2 E, it is staggeredly stacked by 8 chips and forms; Shown in Figure 5, it is staggeredly stacked by 4 chips and forms; Shown in Figure 6, it is staggeredly stacked by 6 chips and forms; Certainly also can be by other the mode of forming, so as long as the structure that ability formed multi-chip interleaving according to the previous description piles up is enforcement aspect of the present invention.
Then, the present invention also proposes a kind of stack type chip packaging structure according to above-mentioned multi-chip interleaving stacked structure 30,50 and 70, and specifies as follows.Simultaneously, in following declarative procedure, will be embodiment, yet be stressed that multi-chip interleaving stacked structure 30 and 70 also is suitable for the content that present embodiment is disclosed with multi-chip interleaving stacked structure 50.
At first, please refer to Fig. 7, is the floor map of stack type chip packaging structure of the present invention.As shown in Figure 7; Stack type chip packaging structure comprises that lead frame 60 and multi-chip interleaving stacked structure 50A form; Wherein form relatively by interior pin crowd 610, a plurality of outer pin crowds (not being shown on the figure) and 620 of chip bearings of arrangement by a plurality of one-tenth for lead frame 60; Its chips bearing 620 is disposed between the interior pin crowd 610 of a plurality of relative arrangements, and the interior pin crowd 610 and the chip bearing 620 of a plurality of relative arrangements simultaneously also can form a difference in height.In the present embodiment, multi-chip interleaving stacked structure 50A is configured on the chip bearing 620, and by an adhesion coating 230 affixed multi-chip interleaving stacked structure 50A and chip bearings 620; This adhesion coating 230 is not defined as aforesaid semi-curing glue, so long as have the sticky material of this function, is enforcement aspect of the present invention, for example: glued membrane (die attached film).Then, via many strip metals lead 640 multi-chip interleaving stacked structure 50A is connected with the interior pin crowd 610 of lead frame 60 again.In addition, the pad in the wire bonds district of chip 500 can be single-row arrangement (shown in Fig. 2 A), also can be that biserial is arranged (shown in Fig. 3 B or Fig. 3 C), and the present invention does not limit.
Continue please refer to Fig. 7; In the lead frame 60 of stack type chip packaging structure of the present invention; In order to make lead frame 60 that more electrical contact can be provided; With electric connection, further dispose an insulating barrier 611 on interior pin crowd's 610 in the present invention the local location, and on insulating barrier 611, dispose at least one metal pad 613 again as power supply contact, ground contact or signal contact.Thus, many many metal pads 613 on the pin crowd 610 in making are so can provide more elasticity and application on the circuit design.
In addition; With regard to above-mentioned insulating barrier 611; Its coating capable of using (coating) or wire mark (printing) macromolecular material forms, for example: polyimides (polyimide, PI); Or use the mode of pasting (attaching) to form, for example use glued membrane (die attached film).Metal pad 613 plating (plating) technology then capable of using or etching (etching) technology are formed on a metal level (being metal pad 613) on the insulating barrier 611.To stress that at this insulating barrier 611 of the present invention can be to be configured in whole interior pin
The crowd610 or local interior pin crowd 610 on, can certainly use multisegment mode to be formed on interior pin
The crowd On 610, the present invention does not limit yet.In addition, the present invention also can form an insulating barrier 611 and again formation metal pad 613 on this insulating barrier 611 more again on the metal pad 613, many more many metal pads 613 on the pin crowd 610 in so can making.
Explain that then the present invention uses the metal pad 613 on the interior pin crowd 610 to reach the process that plain conductor 640 wire jumpers connect, please again with reference to figure 7.Fig. 7 shows the pad b on lower floor's chip and the chip 500 (b ') and pad c (c ') is reached the sketch map that interior pin 6102 (6122) is connected with interior pin 6103 (6123).Clearly; A plurality of metal pads 613 in present embodiment can utilize on the pin crowd 610 as transit point reach with pad b (b ') and pad c (c ') and interior pin 6103 (6123) and in pin 6102 (6122) wire jumpers is connected, and can not produce the situations of plain conductor 640 mutual leaps.For example, with a strip metal lead 640 the pad b on the chip 500 is connected to earlier on the metal pad 613 on the interior pin 6102 earlier, and then the metal pad 613 on the interior pin 6102 is connected with interior pin 6103 with another strip metal lead 640.Therefore, can reach pad b accomplished with interior pin 6103 and is connected, and another connection pads of the necessary leap c of institute reaches the plain conductor 640 of interior pin 6102 when avoiding pad b directly is connected with interior pin 6103.Then, carry out pad a is connected with a strip metal lead 640 with interior pin 6101, again the pad c on the chip 500 is connected to earlier on total coil holder 6102, then with another strip metal lead 640 pad d is connected on total coil holder 6104 again.Therefore, can reach pad b is accomplished in the process that is connected with interior pin 6103, avoid crossing over the plain conductor 640 of another connection pads c and interior pin 6102.And the pad b ' of another side and pad c ' and interior pin 6123 and in pin 6122 wire jumper connection procedures also be to use the identical process completion to be connected; Therefore accomplish pad b ' and pad c ' and interior pin 6123 and in after being connected of pin 6122, can not produce the situations of plain conductor 640 mutual leaps yet.
Continue please refer to Fig. 8 A and Fig. 8 B; In the lead frame 600 of staggered and stacked chip-packaging structure of the present invention; Comprise that further at least one total coil holder 630 (bus bar) is disposed between the interior pin crowd 610 of chip bearing 620 and a plurality of relative arrangements; Wherein total coil holder 630 can adopt the strip configuration, shown in Fig. 8 A and Fig. 8 B; Simultaneously total coil holder 630 also can adopt ring-type configuration (not being shown among the figure).In addition, as previously mentioned, the pad in the wire bonds district of chip 500 can be single-row arrangement, also can be that biserial is arranged, and the present invention does not limit.
Explain that then the present invention uses total coil holder 630 and interior pin crowd 610 to reach the process that plain conductor 640 wire jumpers connect, please again with reference to figure 8A.Fig. 8 A shows a sketch map that the pad on the chip 500 is connected with total coil holder 630 and interior pin crowd 610.Clearly, present embodiment can utilize total coil holder 6301 and total coil holder 6302 as the transit point of ground connection, and pad a and pad a ' are connected with interior pin 6101 and interior pin 6121; Then, with the pad c on lower floor's chip and the chip 500 (c ') and pad d (d ') and interior pin 6101 (6121) and in the sketch map that is connected of pin 6103 (6123).Clearly; Present embodiment can be selected earlier with a strip metal lead 640 pad c on the chip and pad c ' to be connected to earlier on the metal pad 6131 and the metal pad 6132 on the interior pin 6122 on the interior pin 6102, and then with another strip metal lead 640 metal pad 6131 and metal pad 6132 is connected with interior pin 6101 and interior pin 6121; Then; Pad d and pad d ' are connected to earlier on the metal pad 6133 and the metal pad 6134 on the interior pin 6123 on the interior pin 6103, and then metal pad 6133 and metal pad 6134 are connected with interior pin 6104 and interior pin 6124 with another strip metal lead 640.Therefore; Can reach pad c and pad c ' are accomplished in the process that is connected with interior pin 6101 and interior pin 6121; When avoiding pad c (c ') directly is connected with interior pin 6101 (6121), institute must another connection pads of leap b (b ') reaches the plain conductor 640 of interior pin 6102 (6122); Simultaneously; To with pad d and pad d ' and interior pin 6104 and in pin 6124 completion when being connected; When avoiding pad d (d ') directly is connected with interior pin 6104 (6124), institute must another connection pads of leap e (e ') reaches the plain conductor 640 of interior pin 6103 (6123).
And in another embodiment, shown in Fig. 8 B, be to use the structure of multiple bus frame 630 to reach the sketch map that wire jumper connects.At Fig. 8 B promptly is to show a sketch map that the pad c on the chip 500 (c '), pad d (d ') and pad e (e ') are connected with pin 6103 (6123) in interior pin 6101 (6121), interior pin 6104 (6124) reach; Wherein pad a and pad a ' are connected with total coil holder 6301 and total coil holder 6302, to connect as the ground connection transit point.Clearly, present embodiment can utilize total coil holder 6301 and total coil holder 6302 as the ground connection transit point, and utilizes total coil holder 6305 and total coil holder 6304 signal transit points.For example; Elder generation is connected to pad c on the chip 500 and pad c ' earlier on the metal pad 6131 and the metal pad 6132 on the interior pin 6122 on the interior pin 6102 with a strip metal lead 640, and then with another strip metal lead 640 metal pad 6131 and metal pad 613 is connected with interior pin 6101 and interior pin 6121; In addition; Pad d and pad d ' are connected to earlier on the metal pad 6133 and the metal pad 6134 on the interior pin 6123 on the interior pin 6103, and then metal pad 6133 and metal pad 6134 are connected with interior pin 6104 and interior pin 6124 with another strip metal lead 640; Follow again, pad e and pad e ' are connected to earlier on total coil holder 6305 and the total coil holder 6304, and then total coil holder 6305 and total coil holder 6304 are connected with interior pin 6103 and interior pin 6123 with another strip metal lead 640.Therefore; Can reach pad c and pad c ' are connected with interior pin 6101 and 6121 completion of interior pin; Reach the plain conductor 640 of interior pin 6102 (6122) and when avoiding pad c (c ') directly is connected with interior pin 6101 (6121), institute must another connection pads of leap b (b '); And with pad d and pad d ' and interior pin 6104 and in pin 6124 completion be connected; Reach the plain conductor 640 of interior pin 6103 (6123) and when avoiding pad d (d ') directly is connected with interior pin 6104 (6124), institute must another connection pads of leap e (e ').
Therefore; The structure that is used as a plurality of transit points by the metal pad 613 on the interior pin in the lead frame 600 (promptly 6131～6134) and total coil holder 630 (promptly 6301,6302,6304,6305) of the present invention; Make when necessary wire jumper connects carrying out circuit to connect, can avoid the staggered leap of plain conductor, and cause unnecessary short circuit; The chip that makes encapsulation accomplish produces the problem of reliability, elasticity more in the time of also can making circuit design.
Then, please refer to shown in Fig. 8 C and Fig. 8 D, is the floor map of another embodiment of stack type chip packaging structure of the present invention.Shown in Fig. 8 C and Fig. 8 B; Stack type chip packaging structure comprises lead frame 600 and 50 compositions of multi-chip interleaving stacked structure; Wherein form relatively by interior pin crowd 610, a plurality of outer pin crowds (not being shown on the figure) and 620 of chip bearings of arrangement by a plurality of one-tenth for lead frame 600; Its chips bearing 620 is disposed between the interior pin crowd 610 of a plurality of relative arrangements, also can form a difference in height or form a copline between the interior pin crowd 610 of a plurality of relative arrangements simultaneously and the chip bearing 620.In the present embodiment; Also in order to make lead frame 600 that more electrical contact can be provided; With electric connection, so further disposing an insulating barrier 611 on interior pin crowd's 610 the local location and on insulating barrier 611, disposing at least one metal pad 613 again as power supply contact, ground contact or signal contact.Thus, many many metal pads 613 on the pin crowd 610 in making are so can provide more elasticity and application on the circuit design.In addition; In the present embodiment; Lead frame 600 comprises that further at least one total coil holder 630 (bus bar) is disposed between the interior pin crowd 610 of chip bearing 620 and a plurality of relative arrangements; Wherein total coil holder 630 can adopt at least one strip configuration, and total coil holder 630 of each strip configuration is formed with a plurality of metal segments (promptly 6301,6302,6303,6304,6305,6306), shown in Fig. 8 C and Fig. 8 D; Simultaneously total coil holder 630 also can adopt the ring-type configuration, and total coil holder 630 of each ring-type configuration also is to form with a plurality of metal segments, and the present invention does not limit.In addition, as previously mentioned, the pad 312/344 in the wire bonds district of chip 500 can be single-row arrangement, also can be that biserial is arranged, and the present invention is not restriction also.In addition; Because total coil holder 630 of the present invention with a plurality of metal segments (for example: 6301～6306) form all is; Therefore each metal segments is all independent separately; Make lead frame 600 increase the formed total coil holder 630 of many metal segments virtually, these metal segments then can be in order to the electric connection as power supply contact, ground contact or signal contact, so more elasticity and application on the circuit design can further be provided.
Explain that then the present invention uses total coil holder 630 to reach the process that plain conductor 640 wire jumpers connect, please again with reference to figure 8C.Fig. 8 C shows the sketch map that the pad on the multi-chip interleaving stacked structure 50 is connected with the interior pin of lead frame.Clearly; Present embodiment is that the metal pad 613 on the pin crowd 610 and a plurality of metal segments of forming total coil holder 630 are (for example: 6301～6306) as transit point in utilizing; Be used for reaching pad a (a ') is connected with interior pin 6101 (6121) to interior pin 6105 (6125) wire jumpers to pad f (f '), and can not produce plain conductor 640 situations of leaps each other.For example, earlier the pad a on the multi-chip interleaving stacked structure 50 is connected to the metal segments 6301 of total coil holder 630 earlier, and this metal segments 6301 is as a ground connection tie point with a strip metal lead 640; Pin 6102 in then pad b being directly connected to; With a strip metal lead 640 the pad c on the multi-chip interleaving stacked structure 50 is connected to the metal segments 6303 of total coil holder 630 earlier then, and then is connected with interior pin 6103 with the metal segments 6303 of another strip metal lead 640 with total coil holder 630; Then, the pad d on the chip 500 is connected to earlier on the metal pad 6131 on the interior pin 6102, and then metal pad 6131 is connected with interior pin 6101 with another strip metal lead 640 with a strip metal lead 640.Therefore, when pad c and pad d and interior pin 6103 and in pin 6101 accomplish when being connected, can avoid the mutual leap of 640 of plain conductors that plain conductor 640 and pad d with connection pads c and interior pin 6103 reach interior pin 6101.Then; Carry out pad e is connected with the wire jumper of interior pin 6105; Earlier the pad e on the multi-chip interleaving stacked structure 50 is connected to the metal segments 6305 of total coil holder 630 earlier, and then is connected with interior pin 6105 with the metal segments 6305 of another strip metal lead 640 with total coil holder 630 with a strip metal lead 640.Therefore, when pad e is connected with interior pin 6105 completion, can avoid the plain conductor 640 of connection pads e and interior pin 6105 must cross over the plain conductors 640 that another connection pads f reach interior pin 6104.And at the pad a ' of another side to the configuration of pad f ' and interior pin 6121 to interior pin 6125 and aforementioned identical, so its wire jumper connection procedure is also with aforementioned identical, so repeat no more.Therefore accomplishing pad a ' to being connected of pad f ' and interior pin 6121 to interior pin 6125, can not produce plain conductor 640 situations of leaps each other yet.
And in another embodiment, when having a plurality of pads must carry out the wire jumper connection on the multi-chip interleaving stacked structure 50, can use the structure of multiple bus frame 630 to reach, shown in Fig. 8 C.Fig. 8 C shows the sketch map that the pad on the multi-chip interleaving stacked structure 50 is connected with interior pin.Clearly; In the present embodiment; Dispose insulating barrier 611 in also being to use on the pin crowd 610 and on insulating barrier 611, dispose at least one metal pad 613 again; And cooperate that (for example: 6301～63010) formed total coil holder 630 is used as transit point, is used for reaching pad (a/a '～f/f ') is connected with interior pin crowd 610 wire jumpers, and can produce the situations of plain conductor 640 mutual leaps by a plurality of metal segments.For example, with a strip metal lead 640 pad a on the multi-chip interleaving stacked structure 50 or a ' are connected to the metal segments 6305 or 6306 on total coil holder 630 earlier earlier, and this metal segments 6305 or 6306 is as a ground connection tie point; With a strip metal lead 640 pad b on the multi-chip interleaving stacked structure 50 or b ' are directly connected to earlier on the metal segments 6301 or 6302 of total coil holder 630 then; Then be connected on the metal pad 6131 or 6132 on the interior pin 6102 or 6122 with the metal segments 6301 or 6302 of another strip metal lead 640 again, and then metal pad 6131 and interior pin 6101 be connected on the interior pin 6104 or 6124 with another strip metal lead 640 with total coil holder 630.Then; With a strip metal lead 640 pad d on the multi-chip interleaving stacked structure 50 or d ' are directly connected to earlier on the metal pad 6133 or 6134 on the interior pin 6103 or 6123, and then metal pad 6133 or 6134 are connected with interior pin 6105 or 6125 with another strip metal lead 640.
Therefore; When pad b or b ' and interior pin 6102 or 6122 and pad d or d ' and interior pin 6105 or 6125 accomplish when being connected, can avoid mutual leap with 640 of the plain conductors of the plain conductor 640 of connection pads b or b ' and interior pin 6102 or 6122 and connection pads d or d ' and interior pin 6105 or 6122.Then pad e or e ' are connected to earlier on the metal segments 6307 or 6308 of total coil holder 630 again; And then with another strip metal lead 640 metal segments 6307 of total coil holder 630 or 6308 is accomplished with interior pin 6102 or 6122 and to be connected; So, also can avoid effectively connection pads e or e ' and plain conductor 640 leap another connection pads f of interior pin 6102 or 6122 or the plain conductor 640 of f ' and interior pin 6103 or 6123.
Therefore; Present embodiment (for example: 6301～63010) formed total coil holder 630 is used as the structure of a plurality of transit points with a plurality of metal segments by a plurality of metal pads on the interior pin crowd 610 in the lead frame 600 613; When necessary wire jumper connects carrying out circuit to connect; Can avoid the staggered leap of plain conductor, and cause unnecessary short circuit, so can improve the reliability of packaged chip.Simultaneously, elasticity more in the time of also can making circuit design.
Please refer to Fig. 9 A and Fig. 9 B, is the floor map of an embodiment again of stack type chip packaging structure of the present invention.Shown in Fig. 9 A and Fig. 9 B; Stack type chip packaging structure comprises lead frame 600 and 500 compositions of multi-chip interleaving stacked structure; Wherein form relatively by interior pin crowd 610, a plurality of outer pin crowds (not being shown on the figure) and 620 of chip bearings of arrangement by a plurality of one-tenth for lead frame 600; Its chips bearing 620 is disposed between the interior pin crowd 610 of a plurality of relative arrangements, also can form a difference in height between the interior pin crowd 610 of a plurality of relative arrangements simultaneously and the chip bearing 620.In the present embodiment, multi-chip interleaving stacked structure 500 is configured on the chip bearing 620, and via plain conductor 640 multi-chip interleaving stacked structure 500 is connected with the interior pin crowd 610 of lead frame 600.
Continue please refer to Fig. 9 A and Fig. 9 B; In the lead frame 600 of stack type chip packaging structure of the present invention; Dispose an insulating barrier 611 on the interior pin crowd 610 and on insulating barrier 611, dispose at least one metal pad 613 again; Thus, many many metal pads 613 on the pin crowd 610 in making are so can provide more elasticity and application on the circuit design.In addition; Also dispose an insulating barrier 632 on total coil holder 630 in the present invention and on insulating barrier 632, dispose at least one metal pad 634 again; More elasticity and application on the circuit design make also many many metal pads 634 on total coil holder 630, so can be provided.
Be stressed that total coil holder 630 can adopt the strip configuration, shown in Fig. 9 A and Fig. 9 B; Simultaneously total coil holder 630 also can adopt ring-type configuration (not being shown among the figure), and the present invention does not limit.In addition, as previously mentioned, the pad in the wire bonds district of chip 500 can be single-row arrangement, also can be that biserial is arranged, and the present invention is not restriction also.
The process that present embodiment uses plain conductor 640 wire jumpers to connect then is described; Clearly; Present embodiment is that the metal pad 613 on the pin crowd 610 and a plurality of metal pads 634 on total coil holder 6301 and the total coil holder 6302 reach as transit point pad a (a ') is connected with interior pin 6101 (6121) to interior pin 6105 (6125) wire jumpers to pad f (f ') in utilizing, and can not produce the situations of plain conductor 640 mutual leaps.For example, with a strip metal lead 640 the pad a on the multi-chip interleaving stacked structure is connected to total coil holder 6301 earlier earlier, and this total coil holder 6301 is as a ground connection tie point; Pin 6102 in then pad b being directly connected to; With a strip metal lead 640 the pad c on the multi-chip interleaving stacked structure is connected to earlier on the metal pad 6131 on the interior pin 6102 then, and then metal pad 6131 is connected with interior pin 6101 with another strip metal lead 640.Therefore, accomplish when being connected, can avoid the mutual leap of 640 of plain conductors that plain conductor 640 and pad b with connection pads c and interior pin 6101 reach interior pin 6102 when pad c and interior pin 6101.
Follow again, the pad d on the multi-chip interleaving stacked structure is connected to earlier on the metal pad 6133 on the interior pin 6103, and then metal pad 6133 is connected with interior pin 6104 with another strip metal lead 640 with a strip metal lead 640; Then; Carry out pad e is connected with the wire jumper of interior pin 6105; With a strip metal lead 640 the pad e on the multi-chip interleaving stacked structure is connected to earlier on the metal pad 6135 on the interior pin 6104 earlier, and then metal pad 6135 is connected with interior pin 6105 with another strip metal lead 640; At last; Carry out pad f is connected with the wire jumper of interior pin 6103; Earlier the pad f on the multi-chip interleaving stacked structure is connected to the metal pad 6341 of total coil holder 6301 earlier, and then is connected with interior pin 6103 with the metal pad 6341 of another strip metal lead 640 with total coil holder 6301 with a strip metal lead 640.Therefore; When pad d, pad e, pad f with interior pin 6103, interior pin 6104, when interior pin 6105 is accomplished and is connected, can avoid the connection pads d (e) and the plain conductor 640 of interior pin 6104 (6105) must cross over the plain conductors 640 of another connection pads f and interior pin 6103.And at the pad a ' of another side to the configuration of pad f ' and interior pin 6121 to interior pin 6125 and aforementioned identical, so its wire jumper connection procedure is also with aforementioned identical, so repeat no more.Therefore accomplishing pad a ' to being connected of pad f ' and interior pin 6121 to interior pin 6125, can not produce plain conductor 640 situations of leaps each other yet.
And in another embodiment, shown in Fig. 9 B, when having a plurality of pads must carry out the wire jumper connection on the chip 500, can use the structure of multiple bus frame 630 to reach.In the present embodiment; All dispose on the interior pin crowd 610 and also dispose a plurality of metal pads 634 on many metal pads 613 and a plurality of total coil holder 630 and be used as transit point, wherein 630 of metal pad 613 and metal pad 634 and interior pin crowd 610 and total coil holders are isolated by an insulating barrier.Because the actual connection of present embodiment and wire jumper process are identical with aforesaid Fig. 9 A, so repeat no more.
In addition; To stress once more; Multi-chip interleaving stacked structure of the present invention is fixed on the lead frame 600; A plurality of chips 500 in the multi-chip interleaving stacked structure wherein, its can be same size and identical function chip (for example: memory chip), or the chip size in a plurality of chip 500 and function (for example: the chip of the superiors is that other chip of chip for driving then is a memory chip) inequality.And the chip size that piles up for multi-chip interleaving or chip functions etc. are not characteristic of the present invention, just repeat no more at this.
Then please refer to Figure 10, is that the present invention is along the generalized section of Fig. 7 along the multi-chip interleaving stack package structure of AA line segment section.Shown in figure 10; Be connected by many strip metals lead 640a, 640b, 640c, 640d between lead frame 600 and the multi-chip interleaving stacked structure 50; Wherein lead frame 600 is made up of interior pin crowd 610, a plurality of outer pin crowds (not being shown on the figure) and 620 of chip bearings of a plurality of relative arrangements; And chip bearing 620 is disposed between the interior pin crowd 610 of a plurality of relative arrangements, and forms a difference in height with the interior pin crowd of a plurality of relative arrangements 610.Dispose an insulating barrier 611 on the interior in the present embodiment pin crowd 610 and on insulating barrier 611, dispose at least one metal pad 613 again.Thus, many many metal pads 613 on the pin crowd 610 in making are so can provide more elasticity and application on the circuit design.
Shown in figure 10, plain conductor is to be connected on the pad of chip 500a with the end of wire bonding technique with plain conductor 640a, and the other end of plain conductor 640a then is connected on the pad of chip structure 500b.Then, the end of plain conductor 640b is connected on the pad of chip 500b, and then the other end of plain conductor 640b is connected on the pad of chip 500c.Then repeat the process of plain conductor 640a and 640b again, with chip 500c and chip 500d, and chip 500c and chip 500f accomplish and electrically connect with plain conductor 640d, 640c.Follow again, respectively (for example: interior pin 6101 or 6121) accomplish and electrically connect the interior pin crowd 610 of a plurality of relative arrangements of chip 500a, 500d and lead frame 600 with plain conductor 640g.Thus, via plain conductor 640a, 640b, 640c and 640d etc. successively accomplish connect after, just can chip 500a, 500b, 500c and 500d be electrically connected at lead frame 600, wherein the material of these plain conductors 640 can be used gold.
Simultaneously, owing to dispose metal pad 613 on the interior pin crowd 610 of the lead frame 600 of present embodiment, it can be used as the metal pad 613 that comprises power supply contact, ground contact or signal contact.For example; When signaling transfer point that metal pad 613 connects as circuit; So the pad that can the end of plain conductor 640e be connected in chip 500d (for example: pad b '); And the other end of plain conductor 640e be connected to metal pad 613 (for example: metal pad 6132), and then by plain conductor 640f with metal pad 6132 be connected to some in pin (for example: interior pin 6123).So at another side of chip 500a, then can by many strip metals lead 640g with chip 500a (for example: pad a) with interior pin crowd 610 (for example: interior pin 6101) be connected.The pad that then end of plain conductor 640g is connected in chip 500a (for example: pad b); And the other end of plain conductor 640g be connected to metal pad 613 (for example: metal pad 6131), and then by plain conductor 640i, 640f with metal pad 6131 be connected to some in pin (for example: interior pin 6103).So; Switching via metal pad 613; Increase with regard to not producing the radian that makes the plain conductor that to cross in order to cross over other plain conductor, also so not only can increase the elasticity in circuit design or the application, also can effectively improve the production capacity and the reliability of packaging technology.
In addition; Also be stressed that; Chip 500b directly is stacked on the chip 500a; Be to be fixed together as adhesion coating between the two, and chip 500b is the zone that is stacked in beyond the wire bonds district 320 of chip 500a, so follow-up wire bonding technique can successfully carry out with a macromolecular material 230.In addition, present embodiment does not limit the wire bonding technique of plain conductor 640, so it also can select to connect in regular turn to the direction of chip 500a by the pad on the chip 500f, chip 500a is connected with lead frame 600 at last again.
Then please refer to Figure 11, is the generalized section (be Fig. 8 A along AA line segment or Fig. 8 C along the AA line segment generalized section) of multi-chip interleaving stack package structure of the present invention.Shown in figure 11; Be connected by many strip metals lead 640 between lead frame 600 and the multi-chip interleaving stacked structure 50; Wherein lead frame 600 is made up of interior pin crowd 610, a plurality of outer pin crowds (not being shown on the figure) and 620 of chip bearings of a plurality of relative arrangements; And chip bearing 620 is disposed between the interior pin crowd 610 of a plurality of relative arrangements; And form a difference in height with the interior pin crowd 610 of a plurality of relative arrangements, and at least one total coil holder 630 is disposed between interior pin crowd 610 and the chip bearing 620.Total coil holder in the present embodiment is the configuration with 620 one-tenth one coplines of chip bearing.In the present embodiment, configuration one insulating barrier 611 and on insulating barrier 611, dispose at least one metal pad 613 again on the interior pin crowd 610.
Shown in figure 11, plain conductor 640 is to be connected on the pad of chip 500a with the end of wire bonding technique with plain conductor, and the other end of plain conductor then is connected on the pad of chip structure 500b; Then, an end of plain conductor is connected on the pad of chip 500b, and then the other end of plain conductor is connected on the pad of chip 500c; Then repeat the process of plain conductor again, chip 500c and chip 500d are accomplished electric connection with plain conductor; Follow again, with the interior pin crowd 610 of a plurality of relative arrangements of chip 500a and lead frame 600 (for example: interior pin 6102 or 6122) accomplish and electrically connect with plain conductor 640i.Thus, via plain conductor 640 and 640i etc. successively accomplish connect after, just can chip 500a, 500b, 500c and 500d be electrically connected at lead frame 600, wherein the material of these plain conductors 640 can be used gold.
Simultaneously, because the lead frame 600 of present embodiment also disposes total coil holder 630 except on interior pin crowd 610, disposing a plurality of metal pads 613, it can be used as electric connection point or the signaling transfer point that comprises power supply contact, ground contact or signal contact.For example; With Fig. 8 C is example; When the transit point that connects as circuit with total coil holder 630; So can the end of plain conductor 640e be connected on the pad of chip 500a, and the other end of plain conductor 640j is connected on total coil holder (for example: total coil holder 6301), and then by plain conductor 640k with total coil holder 6301 be connected to some in pin (for example: interior pin 6123).Then, the end of plain conductor 640i is connected on the pad of chip 500a, and the other end of plain conductor 640m be connected in metal pad 613 on the pin; And then with another strip metal lead 640n with metal pad 613 be connected to some in pin (for example: interior pin 6121).
In addition, the chip 500b of multi-chip interleaving stacked structure 50, its also can be again with a plurality of pad configuration on it on another side of chip.So, the pad on the chip 500b is connected by many strip metals lead 640g at the side of chip 500b.Then; The pad that is connected in chip 500c with the end of plain conductor 640e (for example: pad c); And the other end of plain conductor 640e is connected on total coil holder (for example: total coil holder 6302), and then by plain conductor 640f with total coil holder 6302 be connected to some in pin (for example: interior pin 613).Follow again, the end of plain conductor 640g be connected on the pad of chip 500b, and the other end of plain conductor 640g be connected in metal pad 613 on the pin; And then with another strip metal lead 640h with metal pad 613 be connected to some on the pin.
In addition; Also be stressed that; Chip 500b directly is stacked on the chip 500a; Be to be fixed together as adhesion coating between the two, and chip 500b is the zone that is stacked in beyond the wire bonds district of chip 500a, so follow-up wire bonding technique can successfully carry out with a macromolecular material.In addition, present embodiment does not limit the wire bonding technique of plain conductor 640, so it also can select to connect in regular turn to the direction of chip 500a by the pad on the chip 500d, chip 500a is connected with lead frame 600 at last again.
Then please refer to Figure 12～Figure 14, for along Fig. 8 A along the AA line segment or Fig. 8 C along the generalized section of AA line segment, be the generalized section of another embodiment of multi-chip interleaving stacked structure of the present invention.Difference between Figure 12～Figure 14 of the present invention and above-mentioned Figure 11 be the total coil holder 630 in the lead frame 600 be disposed in geometric position between pin crowd 610 and the chip bearing 620 inequality; In the present embodiment Figure 12 for example, its total coil holder 630 are the configurations with 610 one-tenth one coplines of interior pin crowd; Figure 13 in the present embodiment becomes the configuration of a difference in height between its total coil holder 630 and interior pin crowd 610 and the chip bearing 620; And Figure 14 in the present embodiment; In being in the lead frame 600, difference between itself and above-mentioned Figure 11 to Figure 13 is copline between pin crowd 610 and the chip bearing 620, always then formation one difference in height between coil holder 630 and interior pin crowd 610 and the chip bearing 620.Clearly; Figure 12 to Figure 14 is except the structure of lead frame 600 slightly the difference; Come connection procedure then identical by many strip metals lead 640 between lead frame 600 and the multi-chip interleaving stacked structure 50, and wire bonding technique is not characteristic of the present invention, so repeat no more.
Again then please again with reference to Figure 15, the generalized section of an embodiment again that is Fig. 8 B of the present invention along BB line segment or Fig. 9 B along the BB line segment.Difference between Figure 15 and Figure 11～14 figure is that the total coil holder 630 among Figure 15 is to use the structure of a plurality of total coil holders, and the configuration mode of these a plurality of total coil holders 630 can be the strip configuration of Fig. 8 B, the ring-type configuration that also can be, and the present invention does not then limit.Same, also can be further (for example: 6301～63010) form on total coil holder 630 in the present embodiment with a plurality of metal segments.Clearly, because the increase of total coil holder quantity makes the quantity that can be used as electric connection also just increase, therefore can be so that the pad (312a on the multi-chip stacking structure 50; 344) connection has more elasticity; So; Increase with regard to not producing the radian that makes the plain conductor that to cross in order to cross over other plain conductor, also so not only can increase the elasticity in circuit design or the application, also can effectively improve the production capacity and the reliability of packaging technology.Owing to come connection procedure then identical by many strip metals lead 640 between lead frame 600 and the multi-chip interleaving stacked structure 50, and wire bonding technique is not characteristic of the present invention, so repeat no more.
Please refer to Figure 16～Figure 19, is that the present invention is along the generalized section of Fig. 9 A along the multi-chip interleaving stack package structure of AA line segment section.Shown in figure 16; Be connected by many strip metals lead 640 between lead frame 600 and the multi-chip interleaving stacked structure 50; Wherein lead frame 600 is made up of interior pin crowd 610, a plurality of outer pin crowds (not being shown on the figure) and 620 of chip bearings of a plurality of relative arrangements; And chip bearing 620 is disposed between the interior pin crowd 610 of a plurality of relative arrangements; And form a difference in height with the interior pin crowd 610 of a plurality of relative arrangements, and at least one total coil holder 630 is disposed between interior pin crowd 610 and the chip bearing 620.Dispose an insulating barrier 611 on the interior in the present embodiment pin crowd 610 and on insulating barrier 611, dispose at least one metal pad 613 again.Thus, many many metal pads 613 on the pin crowd 610 in making are so can provide more elasticity and application on the circuit design.In addition, become the configuration of a copline between the total coil holder 630 in the present embodiment and the chip bearing 620, wherein total coil holder 630 can adopt the strip configuration, shown in Fig. 9 A and Fig. 9 B; Simultaneously total coil holder 630 also can adopt ring-type configuration (not being shown among the figure).In addition; In order to make lead frame 600 that more electrical contact can be provided; With electric connection, also dispose an insulating barrier 632 on total coil holder 630 in the present invention and on insulating barrier 632, dispose at least one metal pad 634 again as power supply contact, ground contact or signal contact.More elasticity and application on the circuit design thus, make many many metal pads 634 on total coil holder 630, so can be provided.
Shown in figure 16; Plain conductor 640 is with wire bonding technique the end of plain conductor 640a to be connected in the first pad 312a or the 3rd pad 344 (the first pad 312a or the 3rd pad 344 among for example aforementioned the 3rd figure) of chip 500a, and the other end of plain conductor 640a then is connected in the first pad 312a or the 3rd pad 344 of chip structure 500b; Then, the end of plain conductor 640b is connected on the first pad 312a or the 3rd pad 344 of chip 500b, and then the other end of plain conductor 600b is connected on the first pad 312a or the 3rd pad 344 of chip 500c; Then repeat the process of plain conductor 640a and 640b again, chip 500c and chip 500d are accomplished electric connection with plain conductor 640c; Follow again, with plain conductor 640d with the pad on the chip 500a (for example: pad b ') with the interior pin crowd 610 of a plurality of relative arrangements of lead frame 600 (for example: interior pin 6102 or 6122) accomplish and electrically connect.Thus, via plain conductor 640a, 640b, 640c and 640d etc. successively accomplish connect after, just can chip 500a, 500b, 500c and 500d be electrically connected at lead frame 600, wherein the material of these plain conductors 640 can be used gold.
Simultaneously; Because the lead frame 600 of present embodiment is except disposing on interior pin crowd 610 a plurality of metal pads 613; Also on total coil holder 630, dispose a plurality of metal pads 634 again, it can be used as electric connection point or the signaling transfer point that comprises power supply contact, ground contact or signal contact.For example; With Fig. 9 A is example; When the transit point that connects as circuit with the metal pad 634 on total coil holder 630; So can with the end of plain conductor 640e be connected in chip 500a pad (for example: pad f '), and the other end of plain conductor 640e is connected on total coil holder (for example: total coil holder 6342), and then by plain conductor 640f with total coil holder 6342 be connected to some in pin (for example: interior pin 6123).Then, with the end of plain conductor 640g be connected in chip 500a pad (for example: pad c '), and the other end of plain conductor 640g be connected on the pin 6122 metal pad (for example: metal pad 6132); And then with another strip metal lead 640h with metal pad 6132 be connected to some in pin (for example: interior pin 6121).In addition, the chip 500d of multi-chip interleaving stacked structure 50 the superiors, its also can be again with a plurality of pad configuration on it on another side of chip, shown in Fig. 2 D and Fig. 5 B.So at another side of chip 500d, then can by many strip metals lead 640i with the pad on the chip 500d (for example: pad b) with interior pin crowd 610 (for example: interior pin 6102) be connected.Then; The pad that is connected in chip 500d with the end of plain conductor 640j (for example: pad f); And the other end of plain conductor 640j is connected on total coil holder (for example: total coil holder 6341), and then by another plain conductor 640k with total coil holder 634l be connected to some in pin (for example: interior pin 6103).Follow again, with the end of plain conductor 640m be connected in chip 500d pad (for example: pad d), and the other end of plain conductor 640m be connected on the pin 6102 metal pad (for example: metal pad 6133); And then with another strip metal lead 640n with metal pad 6133 be connected to some in pin (for example: interior pin 6104).
Then please refer to Figure 17～Figure 19, for along the generalized section of Fig. 9 A along the AA line segment, is the generalized section of another embodiment of multi-chip interleaving stacked structure of the present invention.Figure 17 of the present invention～19 figure and difference between above-mentioned Figure 16 are that the geometric position that the total coil holder 630 in the lead frame 600 is disposed between interior pin crowd 610 and the chip bearing 620 is inequality; In the present embodiment Figure 17 for example, its total coil holder 630 are the configurations with 610 one-tenth one coplines of interior pin crowd; Figure 18 in the present embodiment becomes the configuration of a difference in height between its total coil holder 630 and interior pin crowd 610 and the chip bearing 620; And Figure 19 in the present embodiment; In being in the lead frame 600, difference between itself and above-mentioned Figure 16～Figure 18 is copline between pin crowd 610 and the chip bearing 620, always then formation one difference in height between coil holder 630 and interior pin crowd 610 and the chip bearing 620.Clearly; Figure 17～19 figure is except the structure of lead frame 600 slightly the difference; Come connection procedure then identical by many strip metals lead 640 between lead frame 600 and the multi-chip interleaving stacked structure 50, and wire bonding technique is not characteristic of the present invention, so repeat no more.
Then please again with reference to Figure 20, be the again generalized section of an embodiment of Fig. 9 B of the present invention again along BB line segment line segment.Difference between Figure 20 and Figure 16 to Figure 19 is that the total coil holder 630 among Figure 20 is to use the structure of a plurality of total coil holders; And the configuration mode of these a plurality of total coil holders 630 can be the strip configuration of Fig. 9 B; The ring-type configuration (not being shown among the figure) that yet can be, the present invention does not then limit.Clearly, because the increase of total coil holder quantity makes the quantity that can be used as electric connection also just increase, therefore can be so that the pad (312a on the multi-chip stacking structure 50; 344) connection has more elasticity; So; Increase with regard to not producing the radian that makes the plain conductor that to cross in order to cross over other plain conductor, also so not only can increase the elasticity in circuit design or the application, also can effectively improve the production capacity and the reliability of packaging technology.Owing to come connection procedure then identical by many strip metals lead 640 between lead frame 600 and the multi-chip interleaving stacked structure 50, and wire bonding technique is not characteristic of the present invention, so repeat no more.
Via above explanation, the embodiment described in the present invention does not limit the quantity of stacked chips 500, all know this art should be according to the above-mentioned method that discloses, and produce the stack type chip packaging structure of the chip 500 that has more than three.Simultaneously, the stacking direction of multi-chip interleaving stacked structure 50 of the present invention does not limit announcement person among the embodiment yet, and it also can carry out piling up of alternating quantity with one with respect to the direction that is disclosed among the previous embodiment with the stacking direction of chip 500.Because the mode that chip join mode between the multi-chip interleaving stacked structure (being called 70) of different directions and multi-chip interleaving stacked structure 70 engage with lead frame 600; And use plain conductor 640 to connect mode of multi-chip interleaving stacked structure 70 and lead frame 600 or the like; All identical with previous said embodiment; Therefore for the execution mode of multi-chip interleaving stacked structure and lead frame 600, just repeat no more at this.
To stress again at this; In all above-mentioned embodiment of the present invention, the insulating barrier 632 on the insulating barrier 611 on the interior pin crowd 610 and the total coil holder 630, coating all capable of using (coating) or wire mark (printing) macromolecular material forms; For example: polyimides (polyimide; PI), or also can utilize the mode of stickup (attaching) to form, for example use glued membrane (die attached film).Metal pad 613 and metal pad 634 plating (plating) technology then capable of using or etching (etching) technology are formed on a metal level on insulating barrier 611 and the insulating barrier 632.Will stress that at this insulating barrier 611 of the present invention and insulating barrier 632 can be to be configured on whole interior pin 610 and the total coil holder 630, on pin 610 and the total coil holder 630, the present invention does not limit yet in can certainly being formed on multisegment mode.In addition, the present invention also can form an insulating barrier and again formation metal pad 613 on this insulating barrier more again on metal pad 613 and metal pad 634, so can make many more many metal pads 613 on the lead frame of the present invention.
Apparently, according to the description among the top embodiment, the present invention has many corrections and difference.Therefore need in the scope of its additional claim item, understand, except above-mentioned detailed description, the present invention can also implement in other embodiment widely.Above-mentionedly being merely preferred embodiment of the present invention, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being accomplished under the disclosed spirit and changes or modification, all should be included in the following claim scope.
Claims (9)
1. have the staggered and stacked chip-packaging structure of metal pad on the interior pin of a lead frame, it is characterized in that, comprise:
Lead frame; Form by the interior pin crowd of a plurality of relative arrangements, a plurality of outer pin crowd and a chip bearing; Said chip bearing is disposed between the interior pin crowd of said relative arrangement and forms a difference in height with the interior pin crowd of said relative arrangement, optionally forms a plurality of metal pads on also be covered on the local location of pin in said an insulating barrier and the said insulating barrier;
The multi-chip interleaving stacked structure; Be staggeredly stacked by a plurality of upper stratas chip and a plurality of lower floors chip and form; Said multi-chip interleaving stacked structure is disposed on the said chip bearing and forms electric connection via the interior pin crowd of many strip metals lead and said relative arrangement; Wherein configuration and expose on the active face of a plurality of pads and each above-mentioned a plurality of lower floors chip is also disposed near another side with respect to above-mentioned a plurality of exposed pad of above-mentioned upper strata chip and is exposed a plurality of pads near the side on the active face of each above-mentioned a plurality of upper stratas chip; And above-mentioned multi-chip interleaving stacked structure is that to cover lower floor's area of chip alternately with the chip on upper strata more bigger, makes to be configured in all not cresteds of pad on each above-mentioned upper strata chip and each the above-mentioned lower floor chip; And
Packaging body coats said multi-chip interleaving stacked structure and said lead frame, and said outer pin crowd stretches out in outside the said packaging body;
Comprise at least one total coil holder in the wherein said lead frame, said total coil holder is disposed between the interior pin crowd and said chip bearing of said relative arrangement.
2. encapsulating structure as claimed in claim 1 is characterized in that, each the said chip in the said multi-chip interleaving stacked structure comprises:
The chip body; Has wire bonds zone; Said wire bonds region adjacent is in the single side or the adjacent dual-side of said chip body, and wherein said chip body has a plurality of first pad and a plurality of extra-regional second pads of said wire bonds that are positioned at that are positioned at said wire bonds zone;
First protective layer is disposed on the said chip body, and wherein said first protective layer has a plurality of first openings, to expose said first pad and said second pad;
Reconfiguration line layer is disposed on said first protective layer, and wherein said reconfiguration line layer extends in the said wire bonds zone from said second pad, and said reconfiguration line layer has a plurality of the 3rd pads that are positioned at said wire bonds zone; And
Second protective layer is covered on the said reconfiguration line layer, and wherein said second protective layer has a plurality of second openings, to expose said first pad and said the 3rd pad.
3. encapsulating structure as claimed in claim 1 is characterized in that, said total coil holder and said chip bearing form a copline.
4. encapsulating structure as claimed in claim 1 is characterized in that, said total coil holder and interior pin crowd form a copline.
5. encapsulating structure as claimed in claim 1 is characterized in that, all forms a difference in height between the interior pin crowd of said total coil holder and said relative arrangement and said chip bearing three.
6. encapsulating structure as claimed in claim 1 is characterized in that, said total coil holder is annular arrangement.
7. encapsulating structure as claimed in claim 1 is characterized in that, said total coil holder is a stripe-arrangement.
8. encapsulating structure as claimed in claim 7 is characterized in that, said total coil holder is formed with a plurality of metal segments.
9. encapsulating structure as claimed in claim 7 is characterized in that, optionally forms a plurality of metal pads on also be covered on said total coil holder an insulating barrier and the said insulating barrier.
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| US11638359B2 (en) | 2021-05-05 | 2023-04-25 | Toyota Motor Engineering & Manufacturing North America, Inc. | Low profile power module package |
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| CN117954410A (en) * | 2022-10-17 | 2024-04-30 | 长鑫存储技术有限公司 | Semiconductor packaging structure |
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| CN101131978A (en) * | 2006-08-21 | 2008-02-27 | 南茂科技股份有限公司 | Integrated circuit packaging structure and multilayer lead frame used by same |
| CN101170104A (en) * | 2006-10-25 | 2008-04-30 | 南茂科技股份有限公司 | Stacked chip packaging structure with multi-section bus bar in lead frame |
| CN101170103A (en) * | 2006-10-25 | 2008-04-30 | 南茂科技股份有限公司 | Stacked chip package structure with bus frame in lead frame |
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