CN100543982C - Multi-chip stacking packaging structure with asymmetric lead frame - Google Patents
Multi-chip stacking packaging structure with asymmetric lead frame Download PDFInfo
- Publication number
- CN100543982C CN100543982C CNB2006101503982A CN200610150398A CN100543982C CN 100543982 C CN100543982 C CN 100543982C CN B2006101503982 A CNB2006101503982 A CN B2006101503982A CN 200610150398 A CN200610150398 A CN 200610150398A CN 100543982 C CN100543982 C CN 100543982C
- Authority
- CN
- China
- Prior art keywords
- chip
- pin group
- interior pin
- weld pad
- interior
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 42
- 239000004020 conductor Substances 0.000 claims description 41
- 239000000565 sealant Substances 0.000 claims description 35
- 239000011241 protective layer Substances 0.000 claims description 20
- 238000010276 construction Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 9
- 239000002184 metal Substances 0.000 abstract description 9
- 239000008393 encapsulating agent Substances 0.000 abstract 1
- 238000004021 metal welding Methods 0.000 abstract 1
- 230000005012 migration Effects 0.000 description 55
- 238000013508 migration Methods 0.000 description 55
- 238000000034 method Methods 0.000 description 28
- 230000008569 process Effects 0.000 description 22
- 238000005516 engineering process Methods 0.000 description 18
- 238000005538 encapsulation Methods 0.000 description 14
- 239000000463 material Substances 0.000 description 11
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 239000012945 sealing adhesive Substances 0.000 description 4
- 239000002390 adhesive tape Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 229920002521 macromolecule Polymers 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- QEVHRUUCFGRFIF-MDEJGZGSSA-N reserpine Chemical compound O([C@H]1[C@@H]([C@H]([C@H]2C[C@@H]3C4=C(C5=CC=C(OC)C=C5N4)CCN3C[C@H]2C1)C(=O)OC)OC)C(=O)C1=CC(OC)=C(OC)C(OC)=C1 QEVHRUUCFGRFIF-MDEJGZGSSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a stack type chip packaging structure, comprising: the lead frame is composed of a plurality of inner pins and a plurality of outer pins, the inner pins comprise a plurality of parallel first inner pin groups and parallel second inner pin groups, the tail ends of the first inner pin groups and the second inner pin groups are oppositely arranged at intervals, the first inner pin groups are provided with sinking structures, and the tail end positions of the first inner pin groups and the tail end positions of the second inner pin groups have different vertical heights; then fixedly connecting the multi-chip stack structure on the first inner pin group, and electrically connecting the metal welding points on the same side edge with the first inner pin group and the second inner pin group through a plurality of metal wires; and encapsulating the multi-chip stack structure and the inner leads with an encapsulant and having a top edge surface and a bottom edge surface.
Description
Technical field
The present invention relates to a kind of multi-chip stacking encapsulating structure, particularly relate to a kind of use and have the structure that the lead frame of pin carries out the multi-chip stacking encapsulation in the differing heights.
Background technology
In recent years, semi-conductive last part technology is all carrying out three dimensions (Three Dimension; Encapsulation 3D) reaches higher density or capacity of internal memory etc. in the hope of utilizing minimum area.In order to reach this purpose, present stage has developed and has used the mode of chip-stacked (chip stacked) to reach three dimensions (Three Dimension; Encapsulation 3D).
In known technology, the stack manner of chip is stacked in a plurality of chips on the substrate mutually, uses the technology (wire bonding process) of routing that a plurality of chips are connected with substrate then.It is the structure of the chip-stacked encapsulation of substrate with the lead frame that Fig. 1 promptly discloses a kind of, and wherein Figure 1A is the floor map of Figure 1A for generalized section Figure 1B.Shown in Figure 1A, lead frame 5 can be divided into the interior 5a of pin portion, the outer pin 5b of portion and platform part 5c, and wherein platform part 5c and the interior pin 5a of portion and the outer pin 5b of portion have difference in height.At first chip-stacked on the interior pin 5a of lead frame 5 with three, then with plain conductor 10,11,12 weld pad on three chips 7,8,9 is connected on the platform part 5c of lead frame 5 again, then, carry out interior pin 5a and the part platform part 5c sealing of formative technology (molding process) with three stacked chips and lead frame 5, but expose the outer pin 5b of portion, with pin as other interface of connection.
In the above-mentioned known chip stack package structure, because plain conductor 10,11,12 length and radian between the platform part 5c of each chip and lead frame 5 are all inequality, so except in carrying out the sealing process, the long plain conductor of length and radian easily produces displacement and causes outside the short circuit of chip, also can be inequality because of plain conductor 10,11,12 length, cause the phase place of signal of telecommunication problem such as change.
Summary of the invention
Because the shortcoming and the problem of the chip-stacked mode described in the background of invention the invention provides a kind of mode of using multi-chip migration to pile up, the akin chip stack of a plurality of sizes is built up a kind of three-dimensional encapsulating structure.
Main purpose of the present invention is providing a kind of encapsulating structure of multi-chip stacking, makes it have higher encapsulation integrated level and thin thickness.
Another object of the present invention provides a kind of conducting wire frame structure with pin in the differing heights, and it can be encapsulated with the multi-chip migration stacked structure.
A further object of the present invention provides a kind of conducting wire frame structure with pin in the differing heights, the mould stream when carrying out injecting glue make the sealant after the encapsulation can do the adjustment of height, so that can reach balance according to the number of chips in the multi-chip migration stacked structure.
In view of the above, the invention provides a kind of stacked chip packaging construction, comprise: lead frame, constituted by pin in a plurality of and a plurality of outer pin, interior pin then includes a plurality of first parallel interior pin groups and the second parallel interior pin group, and pin group's end is with at interval relative arrangements in the pin group and second in first, and the first interior pin group has heavy interposed structure and forms the first interior pin group's terminal position and the second interior pin group's terminal position has different vertical heights; Then multi-chip stacking structure is fixed on the first interior pin group, and pin group in the pin group and second in the metal bond pad on the edge, the same side and first is electrically connected by many strip metals lead; And use sealant coat multi-chip stacking structure and in pin and have apical margin surface and root edge surface.
Then, the present invention provides a kind of conducting wire frame structure again, constituted by pin in a plurality of and a plurality of outer pin, pin group includes a plurality of first parallel interior pin groups and the second parallel interior pin group in it, and pin group's end is with at interval relative arrangements in the pin group and second in first, and the first interior pin group has heavy interposed structure and forms the first interior pin group's terminal position and the second interior pin group's terminal position has different vertical heights.
Description of drawings
Figure 1A is the cutaway view of prior art;
Figure 1B is the vertical view of Figure 1A;
Fig. 2 A is the vertical view of chip structure of the present invention;
Fig. 2 B is the cutaway view of chip structure of the present invention;
Fig. 2 C is the cutaway view of multi-chip migration stacked structure of the present invention;
Fig. 3 A～C is the schematic diagram of putting layer manufacture process of reseting of the present invention;
Fig. 4 A～B is a cutaway view of reseting the wire bonds district of putting in the floor of the present invention;
Fig. 5 is the cutaway view of reseting the multi-chip migration stacked structure of putting layer that has of the present invention;
Fig. 6 is the cutaway view of lead frame of the present invention;
Fig. 7 becomes the cutaway view of the multi-chip migration stacked structure encapsulation of symmetric shape for sealant of the present invention;
Fig. 8 becomes the cutaway view of another embodiment of the multi-chip migration stacked structure encapsulation of symmetric shape for sealant of the present invention;
Fig. 9 becomes the cutaway view of an embodiment again of the multi-chip migration stacked structure encapsulation of symmetric shape for sealant of the present invention;
Figure 10 becomes the cutaway view of embodiment of the multi-chip migration stacked structure encapsulation of asymmetric shape for sealant of the present invention;
Figure 11 becomes the cutaway view of another embodiment of the multi-chip migration stacked structure encapsulation of asymmetric shape for sealant of the present invention;
Figure 12 becomes the cutaway view of an embodiment again of the multi-chip migration stacked structure encapsulation of asymmetric shape for sealant of the present invention.
The primary clustering description of symbols
2,3,4: semiconductor subassembly
5: lead frame
5a: interior pin portion
5b: outer pin portion
5c: platform part
7,8,9: weld pad
10,11,12: plain conductor
200: chip
210: the chip active surface
220: chip back
230: adhesion layer
240: weld pad
250: the wire bonds district
260: wire bonds area edge line
30: the multi-chip migration stacked structure
310: the chip body
312a: first weld pad
312b: second weld pad
320: the wire bonds district
322: wire bonds area edge line
330: the first protective layers
332: the first openings
340: reset and put line layer
344: the three weld pads
350: the second protective layers
352: the second openings
300: chip structure
400: reset and put layer
50: the multi-chip migration stacked structure
500 (a, b, c, d): chip
600: lead frame
610: interior pin
Pin group in 611: the first
Pin group in 612: the second
613: platform part
614: connecting portion
615: recessed end
616: the approximate stair-stepping structure of epirelief
620: outer pin
640 (a～e): plain conductor
650: metal coupling
70: sealant
710: the apical margin surface
720: the root edge surface
Embodiment
The present invention is a kind of mode of using chip offset to pile up in this direction of inquiring into, and the akin chip stack of a plurality of sizes is built up a kind of three-dimensional encapsulating structure.In order to understand the present invention up hill and dale, detailed encapsulation step and encapsulating structure thereof will be proposed in following description.Apparently, execution of the present invention does not limit the specific details that the person of ordinary skill in the field understood of chip-stacked mode.On the other hand, the detailed step of last part technologies such as well-known chip generation type and chip thinning is not described in the details, with the restriction of avoiding causing the present invention unnecessary.Yet,, can be described in detail as follows for preferred embodiment of the present invention.In addition, except these were described in detail, the present invention can also implement in other embodiments widely, and interest field of the present invention is as the criterion with claim.
In the semiconductor packaging process in modern times, all be a chip (wafer) of having finished FEOL (FrontEnd Process) to be carried out thinning earlier handle (Thinning Process), the thickness of chip is ground between 2～20mil; Then, coating (coating) or wire mark (printing) one deck macromolecule (polymer) material are in the back side of chip again, and this macromolecular material can be a kind of resin (resine), particularly a kind of B-Stage resin.By a baking or irradiation technology, make macromolecular material present a kind of semi-curing glue again with stickiness; Follow again, an adhesive tape that can remove (tape) is attached on the macromolecular material of semi-solid preparation shape; Then, carry out the cutting (sawing process) of chip, make chip become many chip (die); At last, just many chip can be connected with substrate and chip is formed the stacked chips structure.
Shown in reference Fig. 2 A and Fig. 2 B, finish the floor map and the generalized section of the chip 200 of aforementioned technology.Shown in Fig. 2 B, chip 200 has the back side 220 of active surface 210 and relative active surface, and has formed adhesion layer 230 on the chip back 220; To emphasize at this, adhesion layer 230 of the present invention is not defined as aforesaid semi-curing glue, the purpose of this adhesion layer 230 is engaging with substrate or chip formation, therefore, so long as have the adhesion material of this function, be embodiments of the present invention, for example: glued membrane (die attached film).
Then, please refer to Fig. 2 C, the present invention finishes the generalized section of multi-chip migration stacked structure 30.Shown in Fig. 2 C, the active surface 210 of chip 200 is provided with a plurality of weld pads 240, and a plurality of weld pads 240 have been arranged on the same side of chip 200, therefore, the adhesion layer on the chip back 220 230 and the active surface 210 of another chip 200 are offset after (OFFSET) engage, can form multi-chip migration stacked structure 30, the structure 30 that wherein this multi-chip migration piles up is that the arrangement benchmark of reference forms with the edge line 260 in wire bonds district 250, therefore can form similar stair-stepping multi-chip migration stacked structure 30, be noted that at this, edge line 260 is actually and does not exist on the chip 200, and it is only as line of reference.Still will emphasize that at this adhesion layer 230 of present embodiment is not defined as aforesaid semi-curing glue, therefore the purpose of this adhesion layer 230, so long as have the adhesion material of this function, is embodiments of the present invention engaging with substrate or chip formation.
The present invention uses a kind of reseting to put layer (Redistribution Layer in another embodiment that multi-chip migration piles up; RDL) weld pad with each chip on the chip is set on the side of chip so that can form the structure that multi-chip migration piles up, and this reset put the layer execution mode be described as follows.
Please refer to Fig. 3 A～3C, for of the present invention have reset the manufacture process schematic diagram of chip structure of putting layer.As shown in Figure 3A, chip body 310 at first is provided, and cook up wire bonds district 320 at the side that is adjacent to chip body 310, and a plurality of weld pads 312 on the active surface of chip body 310 are divided into the first weld pad 312a and the second weld pad 312b, wherein the first weld pad 312a is positioned at wire bonds district 320, the second weld pad 312b and then is positioned at outside the wire bonds district 320.Then please refer to Fig. 3 B, form first protective layer 330 on chip body 310, wherein first protective layer 330 has a plurality of first openings 332, to expose the first weld pad 312a and the second weld pad 312b.On first protective layer 330, form to reset then and put line layer 340.Put line layer 340 and comprise many leads 342 and a plurality of the 3rd weld pads 344 and reset, wherein the 3rd weld pad 344 is positioned at wire bonds district 320, and these leads 342 extend to the 3rd weld pad 344 from the second weld pad 312b respectively, so that the second weld pad 312b is electrically connected on the 3rd weld pad 344.In addition, reset the material of putting line layer 340, can be gold, copper, nickel, titanizing tungsten, titanium or other electric conducting material.Please refer to Fig. 3 C again; formation reset put line layer 340 after, second protective layer 350 is covered in to reset puts on the line layer 340, and form chip structure 300; wherein second protective layer 350 has a plurality of second openings 352, to expose the first weld pad 312a and the 3rd weld pad 344.
Be stressed that, though the first above-mentioned weld pad 312a and the second weld pad 312b are arranged on the active surface of chip body 310 with kenel on every side, yet the first weld pad 312a and the second weld pad 312b can also be arranged on the chip body 310 by face array kenel (area array type) or other kenel, and certain second weld pad 312b is electrically connected on the 3rd weld pad 344 by lead 342.In addition, present embodiment does not also limit the arrangement mode of the 3rd weld pad 344, though the 3rd weld pad 344 and the first weld pad 312a are arranged in two row in Fig. 3 B, and the single side along chip body 310 is arranged, but the 3rd weld pad 344 and the first weld pad 312a can also with single-row, multiple row or other mode be arranged in the wire bonds district 320.
Please continue with reference to Fig. 4 A and Fig. 4 B, among Fig. 3 C respectively along hatching A-A ' and the represented generalized section of B-B '.Shown in Fig. 4 A and Fig. 4 B, by in the above-mentioned icon as can be known chip structure 300 mainly comprise chip body 310 and reset and put 400 on layer and form, wherein reset put layer 400 by first protective layer 330, reset and put line layer 340 and second protective layer 350 is formed.Chip body 310 has wire bonds district 320, and wire bonds district 320 is adjacent to the single side of chip body 310.In addition, chip body 310 has a plurality of first weld pad 312a and the second weld pad 312b, and wherein the first weld pad 312a is positioned at wire bonds district 320, and the second weld pad 312b is positioned at outside the wire bonds district 320.
First protective layer 330 is arranged on the chip body 310, and wherein first protective layer 330 has a plurality of first openings 332, to expose these the first weld pad 312a and the second weld pad 312b.Reset and put line layer 340 and be arranged on first protective layer 330, wherein reset and put line layer 340 and extend in the wire bonds district 320 from the second weld pad 312b, and reset and put line layer 340 and have a plurality of the 3rd weld pads 344, it is arranged in the wire bonds district 320.Second protective layer 350 is covered in to reset and puts on the line layer 340, and wherein second protective layer 350 has a plurality of second openings 352, to expose these first weld pad 312a and the 3rd weld pad 344.Because the first weld pad 312a and the 3rd weld pad 344 all are positioned at wire bonds district 320; therefore the zone beyond the wire bonds district 320 on second protective layer 350 just can provide the platform of a carrying; to carry another chip structure; therefore, can form the structure that a kind of multi-chip migration piles up.
Then, please refer to Fig. 5, the generalized section of the structure that another kind of multi-chip migration of the present invention piles up.As shown in Figure 5, multi-chip migration stacked structure 50 is piled up by a plurality of chips 500 and forms, have on its chips 500 to reset and put layer 400, so the weld pad on the chip can be arranged on the wire bonds district 320 of chip 500, therefore this multi-chip migration stacked structure 50 is that alignment line forms with the edge line 322 in wire bonds district 320.And connect with adhesion layer 230 between a plurality of chips 500.At first, the adhesion layer 230 between the chip 500 is the back side that is positioned at chip 500, and the generation type of this adhesion layer 230 is finished simultaneously with chip shown in Fig. 2 B.Because being provided with to reset, the active surface of chip 500 puts layer 400, so the weld pad on the chip (being 312a or 344) can be arranged on the wire bonds district 320 of chip 500, therefore, adhesion layer 230 on chip 500 back sides and reseting of another chip 500 can be put layer 400 is offset after (offset) engage, form a kind of multi-chip migration stacked structure 50, the structure 50 that wherein this multi-chip migration piles up is that the benchmark of reference is arranged heap and formed with the edge line 322 in wire bonds district 320, therefore can form similar stair-stepping multi-chip migration stacked structure 50, as shown in Figure 5.
Then, the present invention also proposes a kind of stack type chip packaging structure according to above-mentioned multi-chip migration stacked structure 30 and 50, and is described in detail as follows.Simultaneously, in following declarative procedure, will be that example carries out, yet be stressed that multi-chip migration stacked structure 30 also is suitable for the disclosed content of present embodiment with multi-chip migration stacked structure 50.
At first, please refer to Fig. 6, lead frame generalized section of the present invention.As shown in Figure 6, interior pin 610 and outer pin 620 that lead frame 600 is arranged relatively by a plurality of one-tenth are formed, wherein interior pin 610 includes pin group 612 in a plurality of parallel first interior pin groups 611 and second, pin group 612 end separates with a gap in the first interior pin group 611 and second simultaneously, make 612 one-tenth relative arrangements of pin group in win interior pin group 611 and second, and pin group 612 height is inequality in the first interior pin group 611 and second.As shown in Figure 6, the first interior pin group 611 is for having heavy structure of putting (downset), and this heavy interposed structure is formed by platform part 613 and connecting portion 614, and wherein the height of platform part 613 is identical with pin group 612 height in second.In addition, the present invention does not limit the shape of connecting portion 614, and it can be inclined-plane or near normal face.To emphasize also that at this platform part 613 also can be the part of pin group 611 in first with connecting portion 614.
Then, please refer to Fig. 7, the generalized section of multi-chip migration stack package structure of the present invention.At first, as shown in Figure 7, lead frame 600 first between pin group 611 and the multi-chip migration stacked structure 50 by with adhesion layer 230 as the material that engages.Clearly, this adhesion layer 230 is attached on the back side of chip 500, as shown in Figure 2; In addition, this adhesion layer 230 also can be selected to be arranged on the first interior pin group 611 of lead frame 600, is connected with multi-chip migration stacked structure 50 then.In addition, in the present embodiment, for first interior pin group 611 of lead frame 600 and the juncture between the multi-chip migration stacked structure 50, also can select to use adhesive tape as connecting material, particularly a kind of two-sided adhesive tape (die attached film) with tackness.
After finishing being connected of lead frame 600 and multi-chip migration stacked structure 50, carry out the connection of plain conductor immediately.Please continue with reference to Fig. 7, plain conductor 640 is connected in the end of plain conductor 640a with routing technology the weld pad of chip 500a, the for example first weld pad 312a or the 3rd weld pad 344 in the earlier figures 3, the other end of plain conductor 640a then is connected on the first weld pad 312a or the 3rd weld pad 344 of chip 500b; Then the end of plain conductor 640b is connected in the first weld pad 312a or the 3rd weld pad 344 of chip 500b, and the other end of plain conductor 640b then is connected on the first weld pad 312a or the 3rd weld pad 344 of chip 500c; Then, repeat the process of plain conductor 640b again, chip 500c and 500d are finished electrical connection with plain conductor 640c.Then, with plain conductor 640d with chip 500d and lead frame 600 first in pin group 611 finish and be electrically connected, then, with plain conductor 640e chip 500d is finished with the second interior pin group 612 again and is connected.Thus, after successively finishing connection by plain conductor 640a, 640b, 640c, 640d and 640e etc., just chip 500a, 500b, 500c and 500d can be electrically connected on the first interior pin group 611 and the second interior pin group 612 of lead frame 600, wherein the material of these plain conductors 640 can be used gold.At last, to finish again in chip offset stack package structure more than the electrical connection is covered in multi-chip migration stacked structure 50 and lead frame 600 with sealant 70 the platform part 613 and second on the pin group 612, and pin 620 outside the lead frame 600 is exposed to outside the sealant 70, can forms stack type chip packaging structure.
In addition, the mode that connects lead frame 600 and multi-chip migration stacked structure 50 with plain conductor, except above-mentioned process, after also can being chosen in the structure of finishing multi-chip migration stacked structure 50, promptly carry out chip 500a earlier, 500b, the plain conductor of 500c and 500d is electrically connected technology, the process of its connection is identical with aforementioned process, then, after the multi-chip migration stacked structure 50 that will finish electrical connection again and lead frame 600 stick together and are integral, carry out the technology of a plain conductor connection again, multi-chip migration stacked structure 50 finished with the interior pin 610 of lead frame 600 be connected, so also can finish the structure of Fig. 7.
In addition, lead frame 600 and multi-chip migration stacked structure 50 finish affixed after, and carrying out the routing technology of plain conductor 640 (wire bonding process) before, earlier on the first weld pad 312a and the 3rd weld pad 344 in the wire bonds district 320 of chip 500, form metal coupling (stud bump) 650 (stud bump) earlier, and then carry out above-mentioned plain conductor 640a, 640b, 640c, 640d, the connection procedure of 640e is with chip 500a, 500b, 500c and 500d are electrically connected on the first interior pin group 611 and the second interior pin group 612 of lead frame 600.Add the purpose of this metal coupling 650,, can reduce the radian of plain conductor 640a, 640b, 640c, 640d, 640e as sept (spacer).Be stressed that at this, the process that forms this metal coupling 650 can be implemented with the process that forms plain conductor 640, that is to say that forming metal coupling 650 is to use same equipment just can reach with formation plain conductor 640, therefore, the setting of increase metal coupling 650 can't increase the difficulty of technology with complicated.
By above explanation, the embodiment described in the present invention does not limit the quantity of reactor core sheet 500, and all those skilled in the art should be according to above-mentioned disclosed method, and produces the stack type chip packaging structure of the chip 500 that has more than three.Simultaneously, the multi-chip migration stacked structure 50 in the embodiment of Fig. 7 also can change multi-chip migration stacked structure 30 into.Because therefore these two multi-chip migration stacked structures 30 and multi-chip migration stacked structure 50 repeat no more all identical with plain conductor connection procedure after lead frame 600 engages.
Please continue with reference to Fig. 8 the generalized section of another embodiment of multi-chip migration stack package structure of the present invention.As shown in Figure 8, interior pin 610 and outer pin 620 that lead frame 600 is arranged relatively by a plurality of one-tenth are formed, wherein interior pin 610 includes pin group 612 in a plurality of parallel first interior pin groups 611 and second, pin group 612 end separates with a gap in the first interior pin group 611 and second simultaneously, make 612 one-tenth relative arrangements of pin group in win interior pin group 611 and second, and pin group 612 height is inequality in the first interior pin group 611 and second.As shown in Figure 8, the first interior pin group's 611 part is identical with Fig. 7, all is to form heavy structure of putting by platform part 613 and connecting portion 614; And in second pin group 612 part, except locating endways to form the recessed approximate stair-stepping structure 615, all the other also with Fig. 7 second in pin group 612 identical.Clearly, the difference place of present embodiment and Fig. 7, pin group 612 end can form recessed approximate stair-stepping structure 615 in second, and pin group 612 is low in the terminal aspect ratio second of this recessed approximate stair-stepping structure 615, therefore when carrying out the connection technology of plain conductor 640, plain conductor 640e can be connected to the end of recessed approximate stair-stepping structure 615 from chip 500d, so, can reduce the radian of plain conductor 640e.Because Fig. 7 is all identical with the plain conductor connection procedure of Fig. 8, therefore repeat no more.
Then, please refer to Fig. 9, the generalized section of an embodiment again of multi-chip migration stack package structure of the present invention.The difference of Fig. 9 and Fig. 8 be in Fig. 9 second in pin group 612 end be the approximate stair-stepping structure 616 that forms epirelief.Clearly, pin group 612 height in the terminal aspect ratio second of the approximate stair-stepping structure 616 of this epirelief, when carrying out the connection technology of plain conductor 640, plain conductor 640e can be connected to the end of the approximate stair-stepping structure 616 of epirelief from chip 500d, so, also can form the encapsulating structure of multi-chip stacking.Because Fig. 7, Fig. 8 are all identical with the plain conductor connection procedure of Fig. 9, therefore repeat no more.
Then, further specify sealant structure of the present invention.Please refer to Fig. 7 and Figure 10, the embodiment generalized section of sealant of the present invention.Sealant 70 of the present invention uses formative technology (moldingprocess) to form sealant, so the mould that molding process uses can have different shapes along with the number of chips of multi-chip migration stacked structure 30 or multi-chip migration stacked structure 50.At first, in Fig. 7, sealant 70 has apical margin surface 710 and root edge surface 720.Because the first interior pin group 611 of lead frame 600 of the present invention is for having heavy structure of putting, this heavy interposed structure is formed by platform part 613 and connecting portion 614, wherein the height of platform part 613 is identical with pin group 612 height in second, and the height that therefore forms pin group 612 in the first interior pin group 611 and second is inequality.After finishing sealing adhesive process, a side of pin group 611 in first, the vertical range of the apical margin of sealant 70 surface 710 to the vertical ranges of platform part 613 (a ') and platform part 613 to the root edge surface 720 of sealant 70 (b ') understood identical; And in second a side of pin group 612, the vertical range (b) that pin group 612 arrives the root edge surface 720 of sealant 70 in pin groups 612 the vertical range (a) and second in the apical margin surface 710 to second of sealant 70 also can be identical.Clearly, the sealant 70 in the present embodiment is a symmetric shape, that is to say a=b=a '=b '.In the structure of this sealant, above in multi-chip migration stacked structure 30 or the multi-chip migration stacked structure 50 chip (for example: chip 500a or 500b) than the platform part 613 and second of lead frame in pin group 612 when high, the present invention can be by adjusting the degree of depth of pin group 611 formed heavy interposed structures in first, topmost chips are (for example: chip 500a) close to the space on the root edge surface 720 of sealant 70 with the first interior pin group 611 formed heavy interposed structures to the space on the apical margin surface 710 of sealant 70 to make multi-chip migration stacked structure 30 or multi-chip migration stacked structure 50, therefore when carrying out sealing adhesive process, can be so that the mould stream under the stream of the mould on the chip 500a that flows through and the first interior pin group's 611 that flows through the heavy interposed structure can obtain balance, to form the symmetric packages structure that present embodiment was disclosed.In addition, when present embodiment and lead frame 600 second in pin group 612 ends when having the approximate hierarchic structure 616 of recessed approximate hierarchic structure 615 or epirelief, also all applicable present embodiment is as Fig. 8 and Fig. 9.
In addition, when the uppermost chip of multi-chip migration stacked structure (for example: height chip 500a) a little less than or a little more than platform part 613 and second in during pin group 612, since lead frame 600 first in pin group 611 be heavy interposed structure, therefore make be fixed in chip 500a on the heavy interposed structure to the space on the apical margin surface 710 of sealant 70 greater than the heavy interposed structure of pin group 611 in first space to the root edge surface 720 of sealant 70; So, when carrying out sealing adhesive process, can cause the mould stream on the chip 500a that flows through and the pin group's 611 in first of flowing through heavy interposed structure mould stream imbalance down, and influence the qualification rate of packaging technology.Therefore, present embodiment can change the mold structure of annotating technology, for example: the height of mold is reduced, topmost chips are (for example: chip 500a) close to the space on the root edge surface 720 of sealant 70 with the first interior pin group 611 formed heavy interposed structures to the space on the apical margin surface 710 of sealant 70 to make multi-chip migration stacked structure 30 or multi-chip migration stacked structure 50, so when carrying out molding process, can be so that the mould stream under the stream of the mould on the chip 500a that flows through and the first interior pin group's 611 that flows through the heavy interposed structure can obtain balance.Therefore, after finishing sealing adhesive process, pin group 612 to the vertical range on the root edge surface 720 of sealant 70 (b ') and second is inequality to the vertical range (b) on root edge surface 720 for the apical margin of sealant 70 surface 710 pin groups' 612 in vertical ranges of platform part 613 (a ') and the apical margin surface 710 to second vertical range (a) and platform part 613, as shown in figure 10.Clearly, the sealant 70 in the present embodiment is a first half and the asymmetric shape of Lower Half, that is to say a=a '; The distance of b=b ' and a equals the distance of b for a short time.Be stressed that at this, utilize mould to reduce the purpose of the apical margin surface 710 of sealant 70 vertical range (a) of pin groups 612 in vertical ranges of platform part 613 (a ') and the apical margin surface 710 to second, except the consumption that can reduce adhesive material, the most important thing is to reach the mould mobile equilibrium in the molding process.In addition, in the present invention, also can be simultaneously adjust a:b (or a ': distance b ') by height design to the heavy interposed structure of pin group 611 in first; In disclosed embodiment, when a:b (or a ': when distance b ') is 1:3, can be so that the mould on the chip 500a that flows through stream and pin group 611 the heavy interposed structure mould stream down in first of flowing through reach the balance of the best.When present embodiment and lead frame 600 second in pin group terminal portion when having the approximate hierarchic structure 616 of recessed approximate hierarchic structure 615 or epirelief, also all applicable present embodiment is as Figure 11 and shown in Figure 12.
In sum, chip structure proposed by the invention is except being in FEOL, just a plurality of weld pads on the chip are arranged at outside the side of chip, also disclose and comprise another way, it mainly is by the planning in suitable wire bonds district and resets and put line layer, first weld pad and the 3rd weld pad are concentrated on the single side of chip structure, make chip structure be suitable for by direct other chip structure of carrying in the zone beyond the wire bonds district.Therefore, pile up the stack type chip packaging structure that forms, compare, just can have thin thickness, and have higher encapsulation integrated level with known technology by the said chip structure.
Apparently, according to the description among the top embodiment, the present invention has many corrections and difference.Therefore need be understood in the scope of its additional claim item, except above-mentioned detailed description, the present invention can also implement widely in other embodiments.Above-mentioned is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should comprise within the scope of the claims.
Claims (4)
1, a kind of stacked chip packaging construction comprises:
Lead frame is made of pin in a plurality of and a plurality of outer pin, and described interior pin includes a plurality of first parallel interior pin groups and the second parallel interior pin group, and pin group's end is with a relative arrangement in interval in the described first interior pin group and second;
Multi-chip stacking structure is fixed on the described first interior pin group, and each upper strata chip of described multi-chip stacking structure tool one chip body and this chip body is electrically connected to the weld pad in the wire bonds district of each the lower floor's chip that is arranged on edge, the same side by plain conductor, and the wire bonds district of this orlop chip is respectively by plain conductor and this pin group electric connection in pin group and this second in first; And
Sealant is in order to coat described multi-chip stacking structure and described a plurality of interior pin and to have apical margin surface and root edge surface;
It is characterized in that:
The pin group has heavy interposed structure and makes the terminal position of pin group in described first and the described second interior pin group's terminal position have different vertical heights in described first.
2, a kind of stacked chip packaging construction comprises:
Lead frame is made of pin in a plurality of and a plurality of outer pin, and described interior pin includes a plurality of first parallel interior pin groups and the second parallel interior pin group, and pin group's end is with a relative arrangement in interval in the described first interior pin group and second;
Multi-chip stacking structure is fixed on the described first interior pin group, and described multi-chip stacking structure has a chip body, and each upper strata chip of this chip body is connected to the weld pad in each the lower floor chip wire bonds district that is arranged on edge, the same side by plain conductor, and the wire bonds district of this orlop chip is respectively by plain conductor and this first interior pin group and this second interior pin group electric connection; And
Sealant coats described multi-chip stacking structure and described a plurality of interior pin and has apical margin surface and root edge surface;
It is characterized in that:
The pin group has heavy interposed structure and makes the terminal position of pin group in described first and the described second interior pin group's terminal position have different vertical heights in described first, and pin group's end also has recessed approximate hierarchic structure in described second.
3, a kind of stacked chip packaging construction comprises:
Lead frame is made of pin in a plurality of and a plurality of outer pin, and described interior pin includes a plurality of first parallel interior pin groups and the second parallel interior pin group, and pin group's end is with a relative arrangement in interval in the described first interior pin group and second;
Multi-chip stacking structure is fixed on the described first interior pin group, and described multi-chip stacking structure has a chip body, and each upper strata chip of this chip body is connected to the weld pad in each the lower floor chip wire bonds district that is arranged on edge, the same side by plain conductor, and the wire bonds district of this orlop chip is respectively by plain conductor and this first interior pin group and this second interior pin group electric connection; And
Sealant coats described multi-chip stacking structure and described a plurality of interior pin and has apical margin surface and root edge surface;
It is characterized in that:
The pin group has heavy interposed structure and makes the terminal position of pin group in described first and the described second interior pin group's terminal position have different vertical heights in described first, and the described second interior pin group's the also lobed approximate hierarchic structure of end.
4, according to claim 1 or 2 or 3 described packaging structures, it is characterized in that: described multi-chip stacking structure comprises:
First protective layer is arranged on the described chip body, and wherein said first protective layer has a plurality of first openings, to expose first weld pad and second weld pad;
Reset and put line layer, be arranged on described first protective layer, wherein said reseting put line layer and extended in the described wire bonds zone from described second weld pad, and described reseting put line layer and had a plurality of the 3rd weld pads that are positioned at described wire bonds zone; And
Second protective layer is covered in described reseting and puts on the line layer, and wherein said second protective layer has a plurality of second openings, to expose described first weld pad and described the 3rd weld pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101503982A CN100543982C (en) | 2006-11-01 | 2006-11-01 | Multi-chip stacking packaging structure with asymmetric lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101503982A CN100543982C (en) | 2006-11-01 | 2006-11-01 | Multi-chip stacking packaging structure with asymmetric lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101174614A CN101174614A (en) | 2008-05-07 |
| CN100543982C true CN100543982C (en) | 2009-09-23 |
Family
ID=39422991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101503982A Active CN100543982C (en) | 2006-11-01 | 2006-11-01 | Multi-chip stacking packaging structure with asymmetric lead frame |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100543982C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5512292B2 (en) * | 2010-01-08 | 2014-06-04 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| CN108292653B (en) * | 2015-09-25 | 2022-11-08 | 英特尔公司 | Method, apparatus and system for interconnecting packaged integrated circuit dies |
| CN111522102A (en) * | 2019-02-01 | 2020-08-11 | 青岛海信宽带多媒体技术有限公司 | Optical module |
| CN113823606A (en) * | 2021-08-12 | 2021-12-21 | 紫光宏茂微电子(上海)有限公司 | Chip stacking and packaging structure and manufacturing method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5291059A (en) * | 1991-11-18 | 1994-03-01 | Mitsubishi Denki Kabushiki Kaisha | Resin-molded semiconductor device and lead frame employed for fabricating the same |
| US20010031513A1 (en) * | 2000-04-14 | 2001-10-18 | Masachika Masuda | Semiconducator device and a method of manufacturing the same |
| US6414379B1 (en) * | 2000-09-29 | 2002-07-02 | Siliconware Precision Industries Co., Ltd. | Structure of disturbing plate having down set |
| CN2631040Y (en) * | 2003-07-29 | 2004-08-04 | 南茂科技股份有限公司 | Center Pad Memory Stacked Package Assembly |
| US20040245630A1 (en) * | 2003-06-09 | 2004-12-09 | Min-Lung Huang | [chip structure] |
| CN1635635A (en) * | 2004-12-17 | 2005-07-06 | 江苏长电科技股份有限公司 | Direct-coupled chip package structure |
-
2006
- 2006-11-01 CN CNB2006101503982A patent/CN100543982C/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5291059A (en) * | 1991-11-18 | 1994-03-01 | Mitsubishi Denki Kabushiki Kaisha | Resin-molded semiconductor device and lead frame employed for fabricating the same |
| US20010031513A1 (en) * | 2000-04-14 | 2001-10-18 | Masachika Masuda | Semiconducator device and a method of manufacturing the same |
| US6414379B1 (en) * | 2000-09-29 | 2002-07-02 | Siliconware Precision Industries Co., Ltd. | Structure of disturbing plate having down set |
| US20040245630A1 (en) * | 2003-06-09 | 2004-12-09 | Min-Lung Huang | [chip structure] |
| CN2631040Y (en) * | 2003-07-29 | 2004-08-04 | 南茂科技股份有限公司 | Center Pad Memory Stacked Package Assembly |
| CN1635635A (en) * | 2004-12-17 | 2005-07-06 | 江苏长电科技股份有限公司 | Direct-coupled chip package structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101174614A (en) | 2008-05-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101330068B (en) | Molded reconfigured wafer, stack package using the same, and method for manufacturing the stack package | |
| US6476474B1 (en) | Dual-die package structure and method for fabricating the same | |
| TWI327365B (en) | Zigzag-stacked chip package structure | |
| US20110227217A1 (en) | Semiconductor package with stacked chips and method for manufacturing the same | |
| CN105023900A (en) | Embedded silicon substrate fan-out type packaging structure and manufacturing method thereof | |
| US20190287939A1 (en) | Semiconductor device and fabricating method of the same | |
| CN107634049A (en) | FC chip systems stack fan-out packaging structure and preparation method thereof | |
| CN111554672A (en) | Chip stacking structure and chip stacking method | |
| CN100543982C (en) | Multi-chip stacking packaging structure with asymmetric lead frame | |
| CN103594447B (en) | IC chip stacked packaging piece that the big high frequency performance of packaging density is good and manufacture method | |
| US20080061411A1 (en) | Chip-stacked package structure for lead frame having bus bars with transfer pads | |
| CN100505247C (en) | Stacked chip packaging structure with metal welding pad on inner pin of lead frame | |
| CN205723498U (en) | The system-level wafer level packaging structure of multi-chip | |
| CN101364593A (en) | Staggered offset stacking packaging structure with multi-section bus bar in lead frame | |
| CN101170103B (en) | Stack type chip packaging structure with bus frame in lead frame | |
| TWI352416B (en) | Stacked chip package structure with unbalanced lea | |
| CN101170104B (en) | Stacked chip packaging structure with multi-section bus bar in lead frame | |
| CN101378048A (en) | Multi-chip stacked packaging structure | |
| US20020084519A1 (en) | Semiconductor chip stack package and fabrication method thereof | |
| US20080283981A1 (en) | Chip-On-Lead and Lead-On-Chip Stacked Structure | |
| CN101131993A (en) | Packaging structure of lead frame on multi-chip stack structure | |
| CN101604684B (en) | Staggered stacked chip package structure with metal pads on the inner leads of the lead frame | |
| CN101393908B (en) | Packaging structure and packaging method of multi-chip stack | |
| CN204885147U (en) | Bury silicon substrate fan -out type packaging structure | |
| CN208608197U (en) | Package-on-package structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |