CN101604503B - Display device and display driving method - Google Patents

Abstract

A display device and a display driving method thereof, the display device includes: the pixel structure comprises a plurality of pixels, a first gate line, a second gate line, a third gate line and a data line. The pixels include a first pixel, a second pixel and a third pixel. The first gate line, the second gate line and the third gate line are electrically coupled with the first pixel, the second pixel and the third pixel respectively for determining whether to start the first pixel, the second pixel and the third pixel. The first pixel is electrically coupled to the data line to receive the display data provided by the data line, the second pixel is electrically coupled to the first pixel to receive the display data provided by the data line through the first pixel, and the third pixel is electrically coupled to the second pixel to receive the display data provided by the data line through the first pixel and the second pixel. The invention can save 2/3 and above data lines, to reduce the cost; and also can achieve better display effect.

Description

Display device and display driving method

technical field

The present invention relates to the field of display technology, and in particular to a display device and a display driving method.

Background technique

An active matrix display device generally includes a substrate, a gate driver, a source driver and a plurality of pixels disposed on the substrate. Wherein, the gate driver is used to generate a driving signal, and provide the driving signal to a plurality of gate lines through a gate fan-out line to determine whether to turn on the pixels electrically coupled to these gate lines. The source driver is used to provide display data to these pixels through a plurality of data lines arranged on the substrate, so as to achieve the purpose of displaying images.

In an active matrix display device, because the cost of the source driver is relatively high, the prior art proposes a display device with a half-source driving (Half-Source Driving, HSD) architecture, which uses two pixels connected in series In this way, the number of data lines of the display device is halved to reduce the number of source drivers or the area of an integrated circuit (Integrated Circuit), so as to achieve the purpose of reducing the cost to a certain extent.

However, the above-mentioned display device with a half-source drive architecture uses two pixels as a cycle, and since the three primary color pixels RGB are arranged in a cycle of three pixels, it is not easy to adjust the gamma curve (Gamma Curve) for a single color. A special driving means for driving the left and right pixels of the data line alternately must be used, otherwise color unevenness (for example, straight line stripes) will easily be caused and the display effect will be poor.

Contents of the invention

One of the objectives of the present invention is to provide a display device to further reduce the cost and improve the display effect.

Another object of the present invention is to provide a display driving method to further reduce the cost and improve the display effect.

To achieve one or part or all of the above objectives or other objectives, an embodiment of the present invention provides a display device, which includes: a plurality of pixels, a first gate line, a second gate line, and a third gate line and data lines; these pixels include a first pixel, a second pixel and a third pixel. The first gate line, the second gate line and the third gate line are respectively electrically coupled to the first pixel, the second pixel and the third pixel, and are used to determine whether to turn on the first pixel, the second pixel and the third pixel. three pixels. Wherein, the first pixel is electrically coupled to the data line to receive the display data provided by the data line, the second pixel is electrically coupled to the first pixel to receive the display data provided by the data line via the first pixel, and the third pixel is electrically coupled to the first pixel to receive the display data provided by the data line. The pixel is electrically coupled to the second pixel to receive display data provided by the data line through the first pixel and the second pixel.

In an embodiment of the present invention, the plurality of pixels of the display device are color pixels, and at least two of the first pixel, the second pixel and the third pixel display different colors. Further, these color pixels may be arranged in a strip or in a mosaic (Delta).

In an embodiment of the present invention, the first pixels, the second pixels and the third pixels are respectively arranged in different columns, and these columns generally extend along the extending direction of the data lines. Alternatively, the first pixel, the second pixel and the third pixel are arranged in two columns.

In an embodiment of the present invention, the third pixel of the display device includes a pixel transistor and a pixel electrode; the pixel electrode is electrically coupled to the pixel transistor, and is separated from the pixel transistor on both sides of the third gate line.

In an embodiment of the present invention, the second gate line is adjacent to the first gate line and the third gate line, and is located between the first gate line and the third gate line.

In an embodiment of the present invention, the display device further includes another data line adjacent to the aforementioned data line, and the first pixel, the second pixel and the third pixel are located between the two data lines. Further, two gate fan-out lines can be further arranged between the two data lines.

Furthermore, an embodiment of the present invention also provides a display driving method implemented in the aforementioned display device, the display driving method includes the steps of: sequentially providing a driving signal to the third gate line, the second gate line and the first gate The driving signal includes a first pulse, a second pulse and a third pulse generated in sequence, the pulse widths of the first pulse, the second pulse and the third pulse increase sequentially and the time intervals decrease sequentially. Wherein, the first pulse of the driving signal supplied to the first gate line, the third pulse of the driving signal supplied to the third gate line, and the second pulse of the driving signal supplied to the second gate line exist temporally. partially overlapping; the second pulse of the driving signal supplied to the first gate line is located after the third pulse of the driving signal supplied to the third gate line, and is identical to the third pulse of the driving signal supplied to the second gate line There is a partial overlap in time; the third pulse of the drive signal supplied to the first gate line follows the third pulse of the drive signal supplied to the second gate line. Further, the display driving method may further include a step of: providing display data with different polarities to two adjacent data lines of the aforementioned display device respectively.

In order to achieve one or part or all of the above objectives or other objectives, another embodiment of the present invention provides a display device, which includes: a plurality of pixels, a first gate line, a second gate line, a third gate lines and data lines; these pixels include a first pixel, a second pixel, and a third pixel, and the first pixel, the second pixel, and the third pixel respectively include a pixel transistor and a first source/drain electrically coupled to the pixel transistor the pixel electrode; the first gate line is electrically coupled to the gate of the pixel transistor of the first pixel, the second gate line is electrically coupled to the gate of the pixel transistor of the second pixel, and the third gate The line is electrically coupled to the gate of the pixel transistor of the third pixel. Wherein, the second source/drain of the pixel transistor of the first pixel is electrically coupled to the data line, and the second source/drain of the pixel transistor of the second pixel is electrically coupled to the first pixel transistor of the first pixel. The source/drain, the second source/drain of the pixel transistor of the third pixel is electrically coupled to the first source/drain of the pixel transistor of the second pixel.

Further, a display driving method implemented in the aforementioned display device is also provided, the display driving method includes the steps of: sequentially supplying driving signals to the third gate line, the second gate line and the first gate line, the The driving signal includes a first pulse, a second pulse and a third pulse generated in sequence, the pulse widths of the first pulse, the second pulse and the third pulse increase sequentially and the time intervals decrease sequentially. Wherein, the first pulse of the driving signal supplied to the first gate line, the third pulse of the driving signal supplied to the third gate line, and the second pulse of the driving signal supplied to the second gate line exist temporally. partially overlapping; the second pulse of the driving signal supplied to the first gate line is located after the third pulse of the driving signal supplied to the third gate line, and is identical to the third pulse of the driving signal supplied to the second gate line There is a partial overlap in time; the third pulse of the drive signal supplied to the first gate line follows the third pulse of the drive signal supplied to the second gate line. Further, the display driving method may further include a step of: providing display data with different polarities to two adjacent data lines of the aforementioned display device respectively.

In order to achieve one or part or all of the above objectives or other objectives, another embodiment of the present invention proposes a display device, which includes: a substrate, a plurality of pixels, a plurality of gate lines and a plurality of data lines; these pixels are arranged on the substrate; the gate lines are arranged on the substrate to determine whether to turn on the pixels; the data lines are arranged on the substrate and intersect with the gate lines to provide display data to the pixels. Wherein, a plurality of gate fan-out lines are arranged between every two adjacent ones of at least some of the data lines, and each of the gate fan-out lines is electrically coupled to a corresponding one of the gate lines. Furthermore, these pixels can be color pixels and arranged in a straight strip or mosaic.

In an embodiment of the present invention, the pixels include a first pixel and a plurality of second pixels connected in series, and the first pixel is electrically coupled to a specific data line among the data lines to receive the data from the specific data line. For the display data provided, one of the second pixels is electrically coupled to the first pixel so that the second pixels receive the display data provided by the specific data line through the first pixel.

In an embodiment of the present invention, the first pixels and the second pixels are respectively arranged in different columns, and the columns generally extend along the extending direction of the specific data line. Alternatively, the first pixels and the second pixels are arranged in two columns.

In an embodiment of the present invention, the first pixel and the second pixels are color pixels, and at least two of the first pixel and the second pixels display different colors.

In an embodiment of the invention, the gate fan-out lines are located in the opaque area of the display device.

In the aforementioned embodiments of the present invention, by using at least three pixels connected in series, the display device can save 2/3 or more of the number of data lines, so that the cost of the display device can be further reduced. Furthermore, the aforementioned embodiments of the present invention can also achieve better display effects. For example, when the display device uses three pixels as a cycle, since the three primary color pixels RGB are also arranged with three pixels as a cycle, there is no need to use interleaved driving data lines The driving method of the left and right pixels (hereinafter referred to as the ZigZag driving method) can also complete the display driving, and it is easy to adjust the gamma curve for a single color. What's more, since the number of data lines can be saved by 2/3 or more, all gate fan-out lines can be placed in the display area, and the border outside the display area can be completely free of gate fan-out lines. It can be designed with a narrow frame, and at the same time, there will be no problem of uneven brightness caused by the fact that the gate fan-out lines cannot be completely placed in the display area.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below and described in detail with accompanying drawings.

Description of drawings

FIG. 1 is a partial schematic diagram of a display device related to an embodiment of the present invention.

FIG. 2 is a timing diagram of driving signals sequentially provided to a plurality of gate lines and display data provided to a plurality of data lines in a display driving method related to an embodiment of the present invention.

FIG. 3 is a partial schematic diagram of another display device related to an embodiment of the present invention.

FIG. 4 is a partial schematic diagram of another display device related to an embodiment of the present invention.

FIG. 5 is a partial schematic diagram of another display device related to an embodiment of the present invention.

FIG. 6 is a partial schematic diagram of another display device related to the embodiment of the present invention.

FIG. 7 shows the relative positional relationship of a plurality of gate lines, a plurality of gate fan-out lines and a plurality of data lines related to an embodiment of the present invention.

The reference numerals in the above-mentioned accompanying drawings are explained as follows:

10: Display device

12: Substrate

11, 31: pixel transistor

13, 33: pixel electrode

R, G, B: pixels

P11, P12, P13, P21, P22, P23, P31, P32, P33: Pixels

GLm, GLm+1, GLm+2, GLm+3: gate lines

DLn, DLn+1, DLn+2: data lines

P1, P2, P3: Pulse

W1, W2, W3: pulse width

T1, T2: time interval

GFLq, GFLq+1, GFLq+2, GFLq+3: Gate fan-out lines

Detailed ways

The foregoing and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as: up, down, left or right, etc., are only referring to the directions of the drawings. Accordingly, the directional terms are used to illustrate and not to limit the invention.

Referring to FIG. 1 , it is a partial schematic diagram of a display device proposed by an embodiment of the present invention. The display device 10 includes a substrate 12, and a plurality of gate lines Gm, Gm+1, Gm+2, Gm+3 arranged on the substrate 12, a plurality of data lines DLn, DLn+1, and a plurality of pixels R, G , B; these pixels R, G, B are color pixels and are arranged in a straight strip. The gate lines Gm, Gm+1, Gm+2, and Gm+3 are used to determine whether to turn on the pixels R, G, and B; the data lines DLn, DLn+1 are used to provide display data to the pixels R, G, and B to achieve a picture display purpose. To simplify the description, the pixel arrangement of the display device 10 proposed by the embodiment of the present invention will be described in detail below by taking three serially connected pixels P11 , P12 and P13 as an example.

As shown in FIG. 1, the gate line GLm+1 is adjacent to the gate line GLm and the gate line GLm+2 and is located between the gate line GLm and the gate line GLm+2; The electrode line GLm+1 and the gate line GLm are electrically coupled to the pixel P11, the pixel P12, and the pixel P13 respectively, and are used to determine whether to turn on the pixel P11, the pixel P12, and the pixel P13; the pixel P11 is electrically coupled to the data line DLn To receive the display data provided by the data line DLn, the pixel P12 is electrically coupled to the pixel P11 to receive the display data provided by the data line DLn via the pixel P11, and the pixel P13 is electrically coupled to the pixel P12 to communicate with the pixel P11 via the pixel P11. P12 receives the display data provided by the data line DLn.

More specifically, the pixels P11, P12, and P13 are located between two adjacent data lines DLn, DLn+1, and respectively include a pixel transistor 11 and a pixel electrode 13 electrically coupled to the drain of the pixel transistor 11; The line GLm+2 is electrically coupled to the gate of the pixel transistor 11 of the pixel P11, the gate line GLm+1 is electrically coupled to the gate of the pixel transistor 11 of the pixel P12, and the gate line GLm is electrically coupled to the gate of the pixel P13. The gate of the pixel transistor 11 is electrically coupled; the source of the pixel transistor 11 of the pixel P11 is electrically coupled to the data line DLn, and the source of the pixel transistor 11 of the pixel P12 is electrically coupled to the pixel transistor 11 of the pixel P11 The drain of the pixel transistor 11 of the pixel P13 is electrically coupled to the drain of the pixel transistor 11 of the pixel P12.

Based on the above, the pixels P11, P12 and P13 display three different colors, such as red (R), green (G) and blue (B); the pixels P11, P12 and P13 are respectively arranged in different columns, and these columns are approximately It extends along the extending direction of the data line DLn, that is, the vertical direction in FIG. 1 .

A display driving method suitable for the display device 10 will be described in detail below in conjunction with FIG. 2. FIG. Timing diagram of display data of DLn+1. It can be seen from FIG. 2 that the driving signals sequentially provided to the gate lines GLm, GLm+1, and GLm+2 respectively include sequentially generated pulses P1, pulse P2, and pulse P3; pulses P1, pulse P2, and pulse P3 The pulse width increases sequentially, that is, W3>W2>W1, and the time interval decreases sequentially, that is, T2<T1. Wherein, the pulse P1 of the driving signal supplied to the gate line GLm+2 overlaps with the pulse P3 of the driving signal supplied to the gate line GLm and the pulse P2 of the driving signal supplied to the gate line Gm+1 in time. ; The pulse P2 of the driving signal provided to the gate line GLm+2 is located after the pulse P3 of the driving signal provided to the gate line GLm, and exists temporally with the pulse P3 of the driving signal provided to the gate line GLm+1 Partially overlapping; the pulse P3 of the driving signal supplied to the gate line GLm+2 is located after the pulse P3 of the driving signal supplied to the gate line GLm+1. The display data provided to the two adjacent data lines DLn and DLn+1 have different polarities.

Furthermore, referring to FIG. 3 , in the display device 10 proposed by the embodiment of the present invention, two gate fan-out lines GFLq, GFLq+1 can be arranged between two adjacent data lines DLn, DLn+1; gate fan-out lines GFLq, GFLq+1 is electrically coupled to the gate lines GLm and GLm+1 respectively, and is disposed in an opaque area of the display device 10 , such as a black matrix area.

In addition, referring to FIG. 4 , the plurality of pixels R, G, and B of the display device 10 proposed by the embodiment of the present invention are not limited to the above-mentioned arrangement in straight stripes, but may also be arranged in a mosaic as shown in FIG. 4 . As shown in FIG. 4 , three pixels P11 , P12 and P13 connected in series display two different colors, such as red (R) and blue (B). These pixels P11 , P12 and P13 are respectively arranged in different columns, and these columns generally extend along the extending direction of the data line DLn. Here, although the data line DLn has a bent portion, its extending direction is still roughly the vertical direction in FIG. 4 .

Further, other designs can also be adopted for the pixel arrangement of the display device 10. For example, as shown in FIG. The three adjacent pixels P21 , P22 and P23 are arranged in two columns, and the two columns generally extend along the extending direction of the data line DLn, that is, the vertical direction in FIG. 5 . Pixels P21, P22, and P23 display two different colors, such as red (R) and green (G). Or as shown in FIG. 6, a plurality of pixels R, G, and B of the display device 10 are arranged in straight strips; three pixels P31, P32, and P33 connected in series among these pixels R, G, and B are arranged on two sides. Among the columns, these columns generally extend along the extending direction of the data line DLn, that is, the vertical direction in FIG. 6 . The pixels P31, P32, and P33 display two different colors, such as red and green; and the pixel transistor 31 and the pixel electrode 33 of the pixel P33 are separately disposed on two sides of the gate line GLm.

Referring to FIG. 7 , it shows the relative positional relationship of multiple gate lines, multiple gate fan-out lines and multiple data lines related to the embodiment of the present invention. As shown in FIG. 7 , a plurality of data lines DLn, DLn+1, DLn+2 disposed on the substrate 12 of the display device 10 intersect with the gate lines GLm, GLm+1, GLm+2, GLm+3, and Two gate fan-out lines are arranged between every two adjacent data lines DLn, DLn+1, DLn+2. More specifically, two gate fan-out lines GFLq and GFLq+1 are arranged between the data line DLn and the data line DLn+1, and the gate fan-out lines GFLq and GFLq+1 are electrically connected to the gate lines GLm and GLm+1 respectively. Sexually coupled to provide driving signals to the gate lines GLm and GLm+1; two gate fan-out lines GFLq+2 and GFLq+3 are arranged between the data line DLn+1 and the data line DLn+2, and the gate The fan-out lines GFLq+2 and GFLq+3 are electrically coupled to the gate lines GLm+2 and GLm+3 respectively for providing driving signals to the gate lines GLm+2 and GLm+3.

It should be noted that the multiple data lines of the display device 10 shown in FIG. 7 are not limited to having two gate fan-out lines between every two adjacent ones. One or more gate fanout lines are arranged between adjacent ones.

In addition, the display device 10 proposed in the embodiment of the present invention is not limited to the aforementioned RGB three-primary-color pixels, and can also use four-primary-color pixels or more primary-color pixels, and correspondingly, a pixel arrangement in which four or more pixels are connected in series can be adopted . Correspondingly, three or more gate fan-out lines may be disposed between every two adjacent ones of at least some of the data lines of the display device.

To sum up, the aforementioned embodiments of the present invention can save 2/3 or more of the number of data lines in the display device by using at least three pixels connected in series, so that the cost of the display device can be further reduced. Furthermore, the aforementioned embodiments of the present invention can also achieve better display effects. For example, when the display device uses three pixels as a cycle, since the three primary color pixels RGB are also arranged with three pixels as a cycle, it is easy to adjust the gamma curve for a single color . What's more, since 2/3 or more of the number of data lines can be saved, all gate fan-out lines can be placed in the display area (such as shown in the dotted line box in Figure 7), which can make the frame outside the display area (Border) has no grid fan-out lines at all, so it can be designed with narrow borders, and there will be no problem of uneven brightness caused by the grid fan-out lines not being able to fit all into the display area.

In addition, those skilled in the art can also make appropriate changes to the display device and display driving method proposed in the foregoing embodiments of the present invention, such as appropriately changing the pixel arrangement, exchanging the electrical connection relationship between the source and drain of each pixel transistor, etc. wait.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore The scope of protection of the present invention should be determined by the scope defined by the appended claims.

Claims (32)

1. A display device comprising: a plurality of pixels, the plurality of pixels comprising a first pixel, a second pixel and a third pixel; a first gate line electrically coupled to the first pixel for determining whether to turn on the first pixel; a second gate line electrically coupled to the second pixel for determining whether to turn on the second pixel; a third gate line electrically coupled to the third pixel for determining whether to turn on the third pixel; and a data line; Wherein, the first pixel is electrically coupled to the data line to receive display data provided by the data line, and the second pixel is electrically coupled to the first pixel to receive the data line via the first pixel The display data provided by the third pixel is electrically coupled to the second pixel to receive the display data provided by the data line via the first pixel and the second pixel. 2. The display device as claimed in claim 1, wherein the plurality of pixels are color pixels, at least two of the first pixel, the second pixel and the third pixel display different colors. 3. The display device as claimed in claim 2, wherein the plurality of color pixels are arranged in a straight strip. 4. The display device as claimed in claim 2, wherein the plurality of color pixels are arranged in a mosaic. 5. The display device as claimed in claim 1, wherein the first pixel, the second pixel and the third pixel are respectively arranged in different columns, and the columns extend substantially along the extending direction of the data line. 6. The display device as claimed in claim 1, wherein the first pixel, the second pixel and the third pixel are arranged in two columns, and the columns generally extend along the extending direction of the data line. 7. The display device according to claim 1, wherein the third pixel comprises a pixel transistor and a pixel electrode; the pixel electrode is electrically coupled to the pixel transistor, and is separated from the pixel transistor at the third gate both sides of the line. 8. The display device according to claim 1, wherein the second gate line is adjacent to the first gate line and the third gate line, and is located between the first gate line and the third gate line. between lines. 9. The display device according to claim 1, further comprising another data line adjacent to the data line, and the first pixel, the second pixel and the third pixel are located between the two data lines . 10. The display device according to claim 9, wherein two gate fan-out lines are further arranged between the two data lines. 11. A display driving method, implemented in a display device as claimed in claim 1, the display driving method comprising the following steps: providing a drive signal to the third gate line, the second gate line and the first gate line in sequence, the drive signal including a first pulse, a second pulse and a third pulse generated in sequence , and the pulse widths of the first pulse, the second pulse and the third pulse are sequentially increased and the time intervals are sequentially decreased; Wherein, the first pulse of the driving signal supplied to the first gate line and the third pulse of the driving signal supplied to the third gate line and the driving signal supplied to the second gate line The second pulse presents a partial overlap in time, The second pulse of the drive signal supplied to the first gate line is located after the third pulse of the drive signal supplied to the third gate line, and is identical to the drive signal supplied to the second gate line. There is a partial overlap in time of this third pulse of the signal, The third pulse of the driving signal supplied to the first gate line is located after the third pulse of the driving signal supplied to the second gate line. 12. The display driving method according to claim 11, wherein the display device further comprises another data line adjacent to the data line, the display driving method further comprising the steps of: Provide display data with different polarities to the two data lines respectively. 13. A display device comprising: A plurality of pixels, the pixels include a first pixel, a second pixel and a third pixel, the first pixel, the second pixel and the third pixel respectively include a pixel transistor and a pixel electrically coupled to the a pixel electrode of the first source/drain of the pixel transistor; a first gate line electrically coupled to the gate of the pixel transistor of the first pixel; a second gate line electrically coupled to the gate of the pixel transistor of the second pixel; a third gate line electrically coupled to the gate of the pixel transistor of the third pixel; and a data line; Wherein, the second source/drain of the pixel transistor of the first pixel is electrically coupled to the data line, and the second source/drain of the pixel transistor of the second pixel is electrically coupled to the first pixel The first source/drain of the pixel transistor, the second source/drain of the pixel transistor of the third pixel is electrically coupled to the first source/drain of the pixel transistor of the second pixel. 14. The display device as claimed in claim 13, wherein the plurality of pixels are color pixels, at least two of the first pixel, the second pixel and the third pixel display different colors. 15. The display device as claimed in claim 14, wherein the plurality of color pixels are arranged in a straight strip. 16. The display device according to claim 14, wherein the plurality of color pixels are arranged in a mosaic. 17. The display device as claimed in claim 13, wherein the first pixel, the second pixel and the third pixel are respectively arranged in different columns, and the columns generally extend along the extending direction of the data line. 18. The display device as claimed in claim 13, wherein the first pixel, the second pixel and the third pixel are arranged in two columns, and the columns generally extend along the extending direction of the data line. 19. The display device as claimed in claim 13, wherein the pixel transistor and the pixel electrode of the third pixel are separately disposed on two sides of the third gate line. 20. The display device according to claim 13, wherein the second gate line is adjacent to the first gate line and the third gate line, and is located between the first gate line and the third gate line. between lines. 21. The display device as claimed in claim 13, further comprising another data line adjacent to the data line, and the first pixel, the second pixel and the third pixel are located between the two data lines. 22. The display device according to claim 21, wherein one or more gate fan-out lines are further arranged between the two data lines. 23. A display driving method, implemented in a display device as claimed in claim 13, the display driving method comprising the following steps: providing a drive signal to the third gate line, the second gate line and the first gate line in sequence, the drive signal including a first pulse, a second pulse and a third pulse generated in sequence , and the pulse widths of the first pulse, the second pulse and the third pulse are sequentially increased and the time intervals are sequentially decreased; Wherein, the first pulse of the driving signal supplied to the first gate line and the third pulse of the driving signal supplied to the third gate line and the driving signal supplied to the second gate line The second pulse presents a partial overlap in time, The second pulse of the drive signal supplied to the first gate line is located after the third pulse of the drive signal supplied to the third gate line, and is identical to the drive signal supplied to the second gate line. There is a partial overlap in time of this third pulse of the signal, The third pulse of the driving signal supplied to the first gate line is located after the third pulse of the driving signal supplied to the second gate line. 24. The display driving method according to claim 23, wherein the display device further comprises another data line adjacent to the data line, the display driving method further comprising the steps of: Provide display data with different polarities to the two data lines respectively. 25. A display device comprising: a substrate; Multiple pixels are arranged on the substrate; a plurality of gate lines arranged on the substrate for determining whether to turn on the plurality of pixels; A plurality of data lines, arranged on the substrate and intersecting with the plurality of gate lines, the plurality of data lines are used to provide display data to the plurality of pixels; Wherein, one or more gate fan-out lines are arranged between every two adjacent ones of at least part of the plurality of data lines, and each of the gate fan-out lines and one of the plurality of gate lines The corresponding phases are electrically coupled. 26. The display device according to claim 25, wherein the plurality of pixels comprises a first pixel and a plurality of second pixels connected in series; the first pixel is electrically coupled to the plurality of data lines a specific data line to receive a display data provided by the specific data line; one of the plurality of second pixels is electrically coupled to the first pixel so that the second pixel is connected to the first pixel through the first pixel A display data provided by the specific data line is received. 27. The display device as claimed in claim 26, wherein the first pixel and the plurality of second pixels are respectively arranged in different columns, and the columns generally extend along the extending direction of the specific data line. 28. The display device as claimed in claim 26, wherein the first pixel and the plurality of second pixels are arranged in two columns, and the columns generally extend along the extending direction of the specific data line. 29. The display device according to claim 26, wherein the first pixel and the plurality of second pixels are color pixels, and at least two of the first pixel and the plurality of second pixels display a color different. 30. The display device as claimed in claim 25, wherein the gate fan-out line is located in an opaque area of the display device. 31. The display device as claimed in claim 25, wherein the plurality of pixels are color pixels arranged in a straight line. 32. The display device as claimed in claim 25, wherein the plurality of pixels are color pixels arranged in a mosaic.

Images