CN101588126A - ZVZCS Three-level DC-DC Converter with Wide Load Characteristics - Google Patents

Abstract

A ZVZCS three-level DC-DC converter with wide load characteristics relates to a three-level converter. It is proposed to solve the problem of large switching loss and large voltage spikes in the existing three-level converter, which may easily cause damage to the switch tube and serious electromagnetic interference. The positive pole of the voltage source is connected with one end of the first and fifth capacitors, the drain terminal of the first insulated gate field effect transistor, the cathode of the first and fifth diodes, and the collector terminal of the fifth triode; the negative pole of the voltage source is simultaneously It is connected with one end of the fourth and sixth capacitors, the source terminal of the fourth insulated gate field effect transistor, the anode of the fourth and sixth diodes and the emitter terminal of the sixth triode (S6); it also increases the auxiliary rectification circuit and active clamp circuit. It has the advantages of fast return to zero current on the primary side and no voltage overshoot on the secondary side, and solves the problems of duty cycle loss, primary side circulating current, parasitic oscillation, etc., improves the efficiency of the converter, and reduces switching losses and electromagnetic interference.

Description

ZVZCS Three-level DC-DC Converter with Wide Load Characteristics

technical field

The invention relates to a three-level DC-DC converter, in particular to a ZVZCS three-level converter.

Background technique

In some occasions, such as arc welding power supply, etc., it will often run in an open circuit state and cannot be shut down. In this case, the ZVS (Zero-Voltage Switching) condition of the ordinary three-level converter disappears, and the switching tube works in a hard switching state, with large switching losses and low efficiency, and will generate large voltage spikes, which may easily cause the switching tube At the same time, the electromagnetic interference (Electro Magnetic Interference, referred to as EMI) is a serious problem, which affects the normal operation of the surrounding electronic equipment.

Contents of the invention

In order to solve the problems of large switching losses and excessive voltage peaks in the existing three-level converters, which may easily cause damage to the switch tube and serious electromagnetic interference, the present invention proposes a ZVZCS three-level with wide load characteristics DC-DC converter.

ZVZCS three-level DC-DC converter with wide load characteristics, which includes the first diode to the eighth diode, the first capacitor to the sixth capacitor, the first insulated gate field effect transistor to the fourth insulated gate type Field effect transistor, fifth transistor, sixth transistor, flying capacitor, resonant inductor, first inductor, filter capacitor, load resistor, first rectifier diode, second rectifier diode and main transformer; the fifth capacitor One terminal is simultaneously connected with the positive voltage terminal, the drain terminal of the first insulated gate field effect transistor, the cathode of the first diode, one terminal of the first capacitor, the collector terminal of the fifth triode and the cathode of the fifth diode The other end of the fifth capacitor is connected to the anode of the seventh diode, the cathode of the eighth diode and one end of the sixth capacitor at the same time, and the other end of the sixth capacitor is connected to the negative voltage end and the fourth insulated gate type The source terminal of the field effect transistor, the anode of the fourth diode, one end of the fourth capacitor, the emitter terminal of the sixth transistor and the anode of the sixth diode are connected; the cathode of the seventh diode is connected to the flying-span One end of the capacitor, the source terminal of the first IGSFET, the drain terminal of the second IGSFET, the anode of the first diode, the cathode of the second diode, and the other end of the first capacitor It is connected to one end of the second capacitor; the anode of the eighth diode is simultaneously connected to the other end of the flying capacitor, the source terminal of the third insulated gate field effect transistor, the drain terminal of the fourth insulated gate field effect transistor, the third The anode of the diode, the cathode of the fourth diode, one end of the third capacitor and the other end of the fourth capacitor are connected; the source terminal of the second insulated gate field effect transistor is connected with the third insulated gate field effect transistor The drain terminal, the anode of the second diode, the cathode of the third diode, the other end of the second capacitor, and the other end of the third capacitor are connected to the same-named end of the primary winding of the main transformer; The terminal with the same name is connected to one end of the resonant inductor; the other end of the resonant inductor is simultaneously connected to the emitter terminal of the fifth triode, the collector terminal of the sixth triode, the anode of the fifth diode and the cathode of the sixth diode connected; the non-identical terminal of the secondary winding of the main transformer is connected to the anode of the first rectifier diode, the terminal of the same name of the secondary winding of the main transformer is connected to the anode of the second rectifier diode, and the cathode of the first rectifier diode is simultaneously connected to one end of the first inductor It is connected to the cathode of the second rectifier diode, and the other end of the first inductor is connected to one end of the filter capacitor and one end of the load resistor at the same time; the other end of the filter capacitor is connected to the other end of the load resistor and the middle tap of the secondary winding of the main transformer at the same time ; It also includes an auxiliary transformer, a third rectifier diode, a fourth rectifier diode, a second inductor, a seventh insulated gate field effect transistor and a clamping capacitor; the source end of the seventh insulated gate field effect transistor is simultaneously connected to the first rectifier The cathode of the diode and the cathode of the second rectifying diode are connected to one end of the first inductance; the drain terminal of the seventh insulated gate field effect transistor is connected to one end of the clamp capacitor and one end of the second inductance at the same time, and the other end of the second inductance At the same time, it is connected to the cathode of the third rectifier diode and the cathode of the fourth rectifier diode; the anode of the third rectifier diode is connected to the non-identical end of the secondary winding of the auxiliary transformer, and the anode of the fourth rectifier diode is connected to the auxiliary transformer The terminal of the same name of the secondary winding of the transformer is connected; the other terminal of the clamping capacitor is connected to the other terminal of the filter capacitor at the same time, the middle tap of the secondary winding of the auxiliary transformer, and the middle tap of the secondary winding of the main transformer are connected to the other terminal of the load resistor; The terminal with the same name of the primary winding of the transformer is simultaneously connected with the other terminal of the fifth capacitor, one terminal of the sixth capacitor, the anode of the seventh diode and the cathode of the eighth diode; the non-identical terminal of the primary winding of the auxiliary transformer is connected with the The source terminal of the second insulated gate field effect transistor, the drain terminal of the third insulated gate field effect transistor, the anode of the second diode, the cathode of the third diode, the other end of the second capacitor, and the third capacitor The other end is connected to the same name end of the primary winding of the main transformer.

The invention has the advantages of low switching loss, no excessive voltage peak and low electromagnetic interference. An auxiliary transformer is added between the midpoint of the voltage dividing capacitor and the midpoint of the three-level bridge arm, and the charging and discharging of the junction capacitance of the switch tube of the three-level bridge arm is completed by means of the excitation current of the primary side of the auxiliary transformer, realizing zero voltage at no-load switch; at the same time, the auxiliary transformer provides energy for the clamp capacitor, maintains the clamp voltage at a high level, and makes the current quickly return to zero after being reflected to the primary side, thereby realizing zero-current switching of the two-level bridge arm switch tube. Compared with traditional zero-current switching converters, the new topology has the advantages of fast primary-side current return to zero and no voltage overshoot on the secondary side, and at the same time solves the problems of duty cycle loss, primary-side circulating current, parasitic oscillation, etc., and improves The efficiency of the converter is improved, and its application range is expanded.

Description of drawings

Fig. 1 is a schematic circuit diagram of the present invention; Fig. 2 is a main working waveform diagram of the present invention; Fig. 3 is a schematic circuit diagram of switch mode 1; Fig. 4 is a schematic circuit diagram of switch mode 2; Fig. 5 is a switch mode 3; Fig. 6 is a circuit schematic diagram of switch mode 4; Fig. 7 is a circuit schematic diagram of switch mode 5; Fig. 8 is a circuit schematic diagram of switch mode 6; Fig. 9 is a switch mode 7 Circuit schematic diagram; Figure 10 is a circuit schematic diagram of switch mode 8; Figure 11 is a circuit schematic diagram of switch mode 9; Figure 12 is a circuit schematic diagram of switch mode 10; Figure 13 is a circuit schematic diagram of switch mode 11 Figure 14 is the driving and drain-source voltage waveform diagram of the first insulated gate field effect transistor S1 at rated load, and the waveform curve 1 is the driving of the first insulated gate field effect transistor S1 under 10V/grid, 5μs/grid Waveform, waveform curve 2 is 100V/grid, the drain-source voltage waveform of the first IGSFET S1 under 5μs/grid; Figure 15 shows the driving and drain-source voltage of the second IGSFET S2 at rated load Waveform diagram, waveform curve 1 is the driving waveform of the second IGSFET S2 at 10V/division, 5μs/division, and waveform curve 2 is the drain of the second IGSFET S2 at 100V/division, 5μs/division Source voltage waveform; Figure 16 is the driving waveform of the fifth triode S5 at rated load and the primary side current waveform of the main transformer Tr1, the waveform curve 1 is 10V/division, the driving waveform of the fifth triode S5 under 5μs/division, Waveform curve 2 is 2V/division, the current waveform of the primary side of the main transformer Tr1 under 5μs/division; Figure 17 is the voltage waveform diagram of the midpoint Vab of the two bridge arms, and waveform curve 1 is 100V/division, and the midpoint Vab of the two bridge arms is under 5μs/division Figure 18 is the voltage waveform diagram of the midpoint voltage Vab of the three-level bridge arm and the two-level bridge arm. The voltage waveform of the point voltage Vab; Figure 19 is the driving and drain-source voltage waveform diagram of the first IGSFET S1 at no-load, the waveform curve 1 is 10V/grid, and the first IGSFET under 5μs/grid The driving waveform of the tube S1, the waveform curve 2 is 100V/grid, the drain-source voltage waveform of the first IGSFET S1 under 5μs/grid; Figure 20 is the driving of the second IGSFET S2 at no-load And drain-source voltage waveform diagram, waveform curve 1 is the driving waveform of the second IGSFET S2 at 10V/grid, 5μs/grid, and waveform curve 2 is the second IGSFET at 100V/grid, 5μs/grid The drain-source voltage waveform of the tube S2; FIG. 21 is an efficiency curve diagram of the present invention.

Detailed ways

Specific implementation mode 1: This implementation mode is described with reference to FIG. 1. This implementation mode includes first diode D1 to eighth diode D8, first capacitor C1 to sixth capacitor C6, first insulated gate field effect transistor S1 To the fourth insulated gate field effect transistor S4, the fifth transistor S5, the sixth transistor S6, the flying capacitor Css, the resonant inductor Lr, the first inductor Lf1, the filter capacitor C0, the load resistor R0, the first rectifier Diode DR1, second rectifier diode DR2 and main transformer Tr1; one end of the fifth capacitor C5 is simultaneously connected to the positive voltage end, the drain end of the first insulated gate field effect transistor S1, the cathode of the first diode D1, and the first capacitor One end of C1, the collector end of the fifth triode S5 and the cathode of the fifth diode D5 are connected; the other end of the fifth capacitor C5 is simultaneously connected to the anode of the seventh diode D7 and the cathode of the eighth diode D8 The cathode is connected to one end of the sixth capacitor C6, and the other end of the sixth capacitor C6 is simultaneously connected to the negative voltage terminal, the source terminal of the fourth insulated gate field effect transistor S4, the anode of the fourth diode D4, and the terminal of the fourth capacitor C4. One end, the emitter end of the sixth triode S6 is connected to the anode of the sixth diode D6; the cathode of the seventh diode D7 is simultaneously connected to one end of the flying capacitor Css, the source of the first insulated gate field effect transistor S1 terminal, the drain terminal of the second insulated gate field effect transistor S2, the anode of the first diode D1, the cathode of the second diode D2, the other end of the first capacitor C1 and one end of the second capacitor C2; The anodes of the eight diodes D8 are simultaneously connected to the other end of the flying capacitor Css, the source terminal of the third insulated gate field effect transistor S3, the drain terminal of the fourth insulated gate field effect transistor S4, and the terminal of the third diode D3. The anode, the cathode of the fourth diode D4, one end of the third capacitor C3 and the other end of the fourth capacitor C4 are connected; the source terminal of the second insulated gate field effect transistor S2 is connected with the third insulated gate field effect transistor S3 at the same time The drain terminal of the second diode D2, the cathode of the third diode D3, the other end of the second capacitor C2, and the other end of the third capacitor C3 are connected to the same-named end of the primary winding of the main transformer Tr1; the main The non-identical end of the primary winding of the transformer Tr1 is connected to one end of the resonant inductance Lr; the other end of the resonant inductance Lr is simultaneously connected to the emitter end of the fifth triode S5, the collector end of the sixth triode S6, and the fifth diode The anode of the tube D5 is connected to the cathode of the sixth diode D6; the non-identical terminal of the secondary winding of the main transformer Tr1 is connected to the anode of the first rectifier diode DR1, and the terminal of the same name of the secondary winding of the main transformer Tr1 is connected to the second rectifying diode DR2 The anode of the first rectifier diode DR1 is connected to the cathode of the first rectifier diode DR1 and one end of the first inductor Lf1 and the cathode of the second rectifier diode DR2, and the other end of the first inductor Lf1 is connected to one end of the filter capacitor C0 and one end of the load resistor R0 at the same time ; The other end of the filter capacitor C0 is connected to the other end of the load resistor R0 and the middle tap of the secondary winding of the main transformer Tr1; it also includes the auxiliary transformer Tr2, the third rectifier diode DR3, the fourth rectifier diode DR4, and the second inductor L f2, the seventh insulated gate field effect transistor S7 and the clamp capacitor Cc; the source terminal of the seventh insulated gate field effect transistor S7 is simultaneously connected with the cathode of the first rectifier diode DR1, the cathode of the second rectifier diode DR2 and the first inductance One end of Lf1 is connected; the drain end of the seventh insulated gate field effect transistor S7 is simultaneously connected with one end of the clamping capacitor Cc and one end of the second inductance Lf2, and the other end of the second inductance Lf2 is simultaneously connected with the cathode of the third rectifier diode DR3 It is connected to the cathode of the fourth rectifier diode DR4; the anode of the third rectifier diode DR3 is connected to the non-identical terminal of the secondary winding of the auxiliary transformer Tr2, and the anode of the fourth rectifying diode DR4 is connected to the terminal of the same name of the secondary winding of the auxiliary transformer Tr2; The other end of the bit capacitor Cc is connected to the other end of the filter capacitor C0 at the same time, the middle tap of the secondary winding of the auxiliary transformer Tr2, the middle tap of the secondary winding of the main transformer Tr1 is connected to the other end of the load resistor R0; the primary winding of the auxiliary transformer Tr2 The terminal with the same name is connected to the other terminal of the fifth capacitor C5, one terminal of the sixth capacitor C6, the anode of the seventh diode D7 and the cathode of the eighth diode D8; the non-identical terminal of the primary winding of the auxiliary transformer Tr2 is simultaneously and the source terminal of the second insulated gate field effect transistor S2, the drain terminal of the third insulated gate field effect transistor S3, the anode of the second diode D2, the cathode of the third diode D3, and the second capacitor C2 The other end, the other end of the third capacitor C3 is connected to the end with the same name of the primary winding of the main transformer Tr1. Working principle of the present invention:

Before analyzing its working mode, make the following assumptions: (1) All switches, diodes, inductors, and capacitors are ideal components; (2) C5 and C6 share the input voltage equally, which can be equivalent to two V _in /2 voltage source; (3) The flying capacitor Css is properly controlled, and the voltage on it remains unchanged at V _in /2; (4) The junction capacitance of each switch tube is Cp, and the transformer ratio is K.

In one cycle, it is divided into 22 modes. The main circuit waveform in the first half of the working cycle is shown in Figure 2. The working mode analysis is as follows:

(1) Switch mode 1 [t ₀ , t ₁ ]. Referring to Fig. 3, before t ₀ , the third insulated gate field effect transistor S3 and the fifth triode S5 are turned on, the primary side of the main transformer Tr1 supplies energy to its secondary side, and the voltages of the primary side and the secondary side of the main transformer Tr1 are respectively is V _in /2, V _in /(2k ₁ ), the primary current i _p is I _o /k ₁ , where k ₁ is the transformation ratio of the main transformer.

Turn off the third insulated gate field effect transistor S3 at time t ₀ , and the output current Io _is reflected to the primary side of the main transformer Tr1 and the excitation current of the primary side of the auxiliary transformer Tr2 to jointly discharge the second capacitor C2 and charge the third capacitor C3 , v _C2 decreases linearly, v _C3 begins to increase linearly, and v _ab increases linearly.

$v_{C3}\left(t\right)=\frac{\frac{I_o}{{\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">k</figure-callout>}}_1}+I_{\mathrm{<figure-callout\; id="2"\; label="m\; max\; C"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">m</figure-callout>}\max }}{C_{}}(t-t_0)$ Formula 1

$v_{C2}\left(t\right)=\frac{V_{\mathrm{in}}}{2}-\frac{\frac{I_o}{{\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">k</figure-callout>}}_1}+I_{\mathrm{<figure-callout\; id="2"\; label="m\; max\; C"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">m</figure-callout>}\max }}{C_{}}(t-t_0)$ Formula 2

$v_{\mathrm{ab}}\left(t\right)=\frac{\frac{I_o}{{\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">k</figure-callout>}}_1}+I_{\mathrm{<figure-callout\; id="2"\; label="m\; max\; C"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">m</figure-callout>}\max }}{C_{}}(t-t_0)-\frac{V_{\mathrm{in}}}{2}$ Formula 3

At time _t1 , v _C2 drops to zero, v _C3 rises to V _in /2, the third insulated gate field effect transistor S3 is turned off at zero voltage, and v _ab is zero. In this mode, i _p is maintained at I _o /k ₁ . The duration of this modal is

${\mathrm{<figure-callout\; id="0"\; label="t"\; filenames="A2009100723650025H1.png"\; state="\{\{state\}\}"><figure-callout\; id="1"\; label="t"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">t</figure-callout></figure-callout>}}_{0,1}=\frac{V_{\mathrm{in}}({\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+C_3)}{2(\frac{I_o}{{\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">k</figure-callout>}}_1}+I_{m\max })}$ Formula 4

(2) Switch mode 2 [t ₁ , t ₂ ]. Referring to Fig. ₄ , at time t1, the first diode D1 and the second diode D2 connected in parallel to the first insulated gate field effect transistor S1 and the second insulated gate field effect transistor S2 are naturally turned on, and the first insulated gate The potentials of the first IGSFET S1 and the second IGSFET S2 are clamped to zero, and the first IGSFET S1 and the second IGSFET S2 are turned on at zero voltage. In this mode, v _ab =0, i _p is maintained at I _o /k ₁ .

(3) Switch mode 3 [t ₂ , t ₃ ]. Referring to Fig. 5, the first IGSFET _S1 , the second IGSFET S2 and the seventh IGSFET S7 are turned on at time _t2 , the clamping capacitor Cc starts to discharge, and the clamping voltage V _Cc is reflected to the primary side through the main transformer Tr1, and acts on the resonant inductance Lr, so that the primary current i _p returns to zero quickly, and a part of the load current _Io flows through the clamping capacitor Cc, and its discharge current i _Cc increases linearly.

$i_p\left(t\right)=\frac{k_1{V}_{\mathrm{CC}}}{L_r}(t-t_2)-\frac{I_o}{{\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">k</figure-callout>}}_1}$ Formula 5

$i_{\mathrm{Cc}}\left(t\right)=\frac{k^2{V}_{\mathrm{CC}}}{L_r}(t-t_2)$ Formula 6

At time t ₃ , i _p rises to zero, i _Cc rises to I _o , and the duration of this mode is

${\mathrm{<figure-callout\; id="2"\; label="t"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}"><figure-callout\; id="3"\; label="t"\; filenames="A2009100723650016H1.png,A2009100723650019H1.png"\; state="\{\{state\}\}">t</figure-callout></figure-callout>}}_{\mathrm{2,3}}=\frac{I_o{\mathrm{<figure-callout\; id="1"\; label="L\; r\; K"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">L</figure-callout>}}_r}{{K_{}}^{}}$ Formula 7

(4) Switch mode 4 [t ₃ , t ₄ ]. Referring to Figure 6, in this mode, the primary current _ip of the main transformer Tr1 is zero, the clamping capacitor Cc is in the conduction state, the current I _o of the load resistor R0 is freewheeling through the clamping capacitor Cc, and the first rectifier diode Dr1 , and the second rectifier diode Dr2 are in a cut-off state.

(5) Switch mode 5 [t ₄ , t ₅ ]. Referring to Fig. 7, the seventh insulated gate field effect transistor S7 is turned off at time _t4 , the rectified voltage _Vr drops to zero rapidly, the first rectifier diode Dr1 and the second rectifier diode Dr2 release the reverse bias, and the current I _o of the load resistor R0 After freewheeling through the first rectifier diode Dr1 and the second rectifier diode Dr2, both v _ab and i _p are maintained at zero. The auxiliary transformer Tr2 starts to charge the clamp capacitor Cc. The duration of this mode is determined by the phase shift value.

(6) Switching mode 6 [t ₅ , t ₆ ]. Referring to Fig. 8, the fifth triode S5 is turned off at time _t5 , since the i _p is zero, all the minority carriers of the fifth triode S5 have been recombined, so the fifth triode S5 is turned off with zero current, solving The current tailing phenomenon when the IGBT is turned off is eliminated. In this mode, v _ab =0, the auxiliary transformer Tr2 continues to charge the clamp capacitor Cc. The duration of this mode is determined by the dead time between the fifth transistor S5 and the sixth transistor S6 of the hysteresis tube.

(7) Switch mode 7[t ₆ , t ₇ ]. Referring to Fig. 9, the sixth triode S6 is turned on at time _t6 , at this time, the first rectifier diode Dr1 and the second rectifier diode Dr2 are in the conduction freewheeling state, the primary and secondary winding voltages of the main transformer Tr1 are zero, and the voltage The source Vin is added to the resonant inductance Lr, and the primary current i _p rises linearly from zero.

$i_p\left(t\right)=\frac{V_{\mathrm{in}}}{L_r}(t-t_6)$ Formula 8

At time _t7 , i _p rises to I _o /k ₁ (k ₁ is the transformation ratio of transformer T ₁ ), the second rectifier diode Dr2 is turned off, and the first rectifier diode Dr1 is turned on. In this mode, v _ab =V _in , the auxiliary transformer Tr2 charges the clamp capacitor Cc. The duration of this modal is

${\mathrm{<figure-callout\; id="6"\; label="t"\; filenames="A2009100723650014H1.png,A2009100723650016H1.png"\; state="\{\{state\}\}"><figure-callout\; id="7"\; label="t"\; filenames="A2009100723650014H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">t</figure-callout></figure-callout>}}_{\mathrm{6,7}}=\frac{L_r{I}_o}{k_1{V}_{\mathrm{in}}}$ Formula 9

(8) Switch mode 8 [t ₇ , t ₈ ]. Referring to Fig. 10, in this mode, the first IGSFET S1, the second IGSFET S2 and the sixth triode S6 are turned on, v _ab =V _in , and the load current flows through the rectifier diode DR1, the primary side starts to provide energy to the load. In this mode, v _ab =V _in , i _p is maintained at I _o /k ₁ , and the auxiliary transformer Tr2 continues to charge the clamp capacitor Cc. At time _t8 , the charging of the clamp capacitor Cc ends.

(9) Switch mode 9 [t ₈ , t ₉ ]. Referring to Fig. 11, in this mode, the first insulated gate field effect transistor S1, the second insulated gate field effect transistor S2 and the sixth triode S6 continue to conduct, v _ab =V _in , and the load current flows through The primary side of the first rectifier diode DR1 starts to provide energy to the load. In this mode, v _ab =V _in , i _p is maintained at I _o /k ₁ .

(10) Switching mode 10[t ₉ , t ₁₀ ]. Referring to Fig. 12, the first insulated gate field effect transistor S1 is turned off at time _t9 , and the output current I _o is reflected to the primary side of the main transformer and the excitation current of the primary side of the auxiliary transformer Tr2 is used to charge the first capacitor C1, and to charge the first capacitor C1. The four capacitors C4 are discharged, v _C1 starts to rise linearly, v _C4 drops linearly, and v _ab drops linearly.

$v_{C1}\left(t\right)=\frac{\frac{I_{\mathrm{<figure-callout\; id="1"\; label="o\; k"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">o</figure-callout>}}}{k_{}}+I_{m\max }}{({\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">C</figure-callout>}}_1+C_4)}(t-t_9)$ Formula 10

$v_{C4}\left(t\right)=\frac{V_{\mathrm{in}}}{2}-\frac{\frac{{\mathrm{<figure-callout\; id="1"\; label="I\; o\; k"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">I</figure-callout>}}_o}{k_{}}+I_{m\max }}{({\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">C</figure-callout>}}_1+C_4)}(t-t_9)$ Formula 11

$v_{\mathrm{ab}}\left(t\right)=V_{\mathrm{in}}-\frac{\frac{{\mathrm{<figure-callout\; id="1"\; label="I\; o\; k"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">I</figure-callout>}}_o}{k_{}}+I_{m\max }}{({\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">C</figure-callout>}}_1+C_4)}(t-t_9)$ Formula 12

At time t ₁₀ , v _C1 rises to V _in /2, v _C4 drops to zero, v _ab drops to V _in /2, and the first insulated gate field effect transistor S1 turns off at zero voltage. In this mode, i _p is maintained at I _o /k ₁ . The duration of this modal is

$t_{\mathrm{9,10}}=\frac{V_{\mathrm{in}}({\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">C</figure-callout>}}_1+C_4)}{2(\frac{{\mathrm{<figure-callout\; id="1"\; label="I\; o\; k"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">I</figure-callout>}}_o}{k_{}}+I_{m\max })}$ Formula 13

(11) Switching mode 11 [t ₁₀ , t ₁₁ ]. Referring to Fig. 13, at time _t10 , the eighth diode D8 is naturally turned on, and since the flying capacitor Css can be approximately regarded as a constant voltage source with a voltage of V _in /2, the voltage of the fourth insulated gate field effect transistor S4 Clamped to 0, v _ab =V _in /2, i _p maintained at I _o /k ₁ , the primary side continues to provide energy to the load.

At this point, the half working cycle ends, S2 is turned off at time _t11 , and the second half cycle starts, which are the same as the above 11 modes, and will not be described again.

The condition that the present invention ZVZCS (zero voltage zero current switch) realizes

At rated load, since the output current participates in the charging and discharging of the junction capacitance of the switch tube of the three-level bridge arm, ZVS is easier to realize. The junction capacitance of the first insulating gate field effect transistor S1 is connected in series with the junction capacitance of the second insulating gate field effect transistor S2 at no load, the junction capacitance of the third insulating gate field effect transistor S3 is connected with the junction capacitance of the fourth insulating gate field effect transistor S4 The capacitors are connected in parallel after being connected in series, and the equivalent capacitance value is the junction capacitance value Cj of the switch tube of the three-level bridge arm. In order to realize the ZVS of the three-level bridge arm at no-load, the charge and discharge of the junction capacitance of the switch tube of the three-level bridge arm must be completed within the dead time t _DB , that is,

t _DB ≥ C _j V _p2 /i _m Formula 14

In the formula, _im is the excitation current of the primary side of the auxiliary transformer, and V _p2 is the voltage of the primary side of the auxiliary transformer, which is 150V. In addition, the setting of the dead time is limited by the maximum duty cycle of the primary side voltage.

The ZCS of the converter is realized with the help of resonant inductor and active clamp. At the initial stage of primary side circulation, turn on the seventh insulated gate field effect transistor S7, so that the clamping voltage V _Cc is reflected to the primary side of the main transformer Tr1, and acts on the resonant inductance, so that the current i _p of the primary side of the main transformer Tr1 returns to zero, so that Realize zero voltage turn off. Therefore, the turn-on time of the seventh insulated gate field effect transistor S7 should be greater than the reset time of the primary current, that is

${\mathrm{<figure-callout\; id="7"\; label="t\; S"\; filenames="A2009100723650014H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">t</figure-callout>}}_S\&Greater\; Equal;\frac{L_r{\mathrm{<figure-callout\; id="1"\; label="I\; o\; k"\; filenames="A2009100723650016H1.png,A2009100723650017H1.png"\; state="\{\{state\}\}">I</figure-callout>}}_o}{{k_{}}^{}}$ Formula 15

At the same time, t _S7 cannot be too large, otherwise more current will pass through the seventh IGSFET S7, the auxiliary rectifier circuit and the clamping capacitor Cc, thereby increasing loss and reducing efficiency. Therefore, under the premise of ensuring the hysteresis tube ZCS, t _S7 should be as small as possible. In addition, in order to ensure ZCS, the minimum dead interval of the hysteresis tube should be greater than or equal to the IGBT minority carrier recombination time. The maximum dead-time interval is limited by the maximum duty cycle of the primary voltage.

Specific embodiment 2: This embodiment is described with reference to the figure. The difference between this embodiment and specific embodiment 1 is that the main power parameters of the converter in the present invention are: U _in = 240V ~ 320V, U _o = 24V, and the rated output current is 6A with a switching frequency of 50kHz. The first insulated gate field effect transistor S1 to the fourth insulated gate field effect transistor S4 and the seventh insulated gate field effect transistor S7 adopt the model IRF740, and the first capacitor C1 to the fourth capacitor C4 are the junction capacitances of the switch tubes, The fifth triode S5 to the sixth triode S6 adopt the model HGTP20N60C3, the clamp capacitor Cc=2.2μF, the main transformer Tr1 transformation ratio k ₁ =63:9, the auxiliary transformer Tr2 transformation ratio k ₂ =36:12 , the model of the first rectifier diode DR1 to the fourth rectifier diode DR4 is MUR1520, the first inductor Lf1=50 μH, and the filter capacitor Co=2200 μF.

Figure 14 and Figure 15 are the driving and drain-source voltage waveforms of the chopper tube S1 and the lead tube S2 at rated load. The magnitude of the drain-source voltage is about 150V, which is half of the input voltage, and has dropped to zero before the drive voltage rises. In the turn-off phase, the junction capacitance limits the rise rate of the drain-source voltage, realizing ZVS. Figure 16 is the drive and primary current waveforms of the hysteresis tube S5 at rated load. When the falling edge of the driving signal arrives, the drain current has dropped to zero, and then the drain-source voltage gradually increases to realize zero current shutdown; after the rising edge of the driving signal arrives, the drain current gradually rises due to the effect of the resonant inductance. It realizes zero current turn-on and solves the current tailing phenomenon of IGBT. FIG. 17 is a waveform of the midpoint voltage V _ab of the two bridge arms, which includes five levels of ±V _in , ±V _in /2 and 0.

At no-load, the chopper tube and the lead tube are turned on and off at the same time, and the converter operates in the two-level mode. At this time, the phase shift angle reaches the maximum, and the lag tube naturally realizes ZCS. The chopper tube and the lead tube rely on the principle of the auxiliary transformer. The side excitation current is used to complete the charging and discharging between the junction capacitances, thereby realizing ZVS. Figure 18 shows the experimental waveforms of the midpoint voltage v _ab of the three-level bridge arm and the two-level bridge arm. It only contains three levels of ±V _in and 0, and it maintains the stability of the output voltage when it is no-load. Figure 19 and Figure 20 are the driving and drain-source voltage waveforms of the chopper tube and the lead tube at no-load conditions. At this time, the chopper tube and the lead tube operate synchronously. It can be seen from the figure that ZVS is realized. When the transformer is no-loaded, the primary current is only the excitation current, and ZCS is naturally realized. Figure 21 is the measured efficiency curve. It can be seen from the figure that the efficiency reaches 87.2% at rated load. Other compositions and connection methods are the same as those in Embodiment 1.

Claims (1)

1. ZVZCS three-level DC-DC converter with wide load characteristics, which includes the first diode (D1) to the eighth diode (D8), the first capacitor (C1) to the sixth capacitor (C6), The first insulated gate field effect transistor (S1) to the fourth insulated gate field effect transistor (S4), the fifth triode (S5), the sixth triode (S6), the flying capacitor (Css), resonance Inductor (Lr), first inductor (Lf1), filter capacitor (C0), load resistor (R0), first rectifier diode (DR1), second rectifier diode (DR2) and main transformer (Tr1); fifth capacitor ( One end of C5) is simultaneously connected to the positive voltage end, the drain end of the first insulated gate field effect transistor (S1), the cathode of the first diode (D1), one end of the first capacitor (C1), and the fifth transistor The collector terminal of (S5) is connected with the cathode of the fifth diode (D5); the other end of the fifth capacitor (C5) is connected with the anode of the seventh diode (D7) and the eighth diode (D8) simultaneously. The cathode of the sixth capacitor (C6) is connected to one end of the sixth capacitor (C6), and the other end of the sixth capacitor (C6) is simultaneously connected to the negative voltage terminal, the source terminal of the fourth insulated gate field effect transistor (S4), the fourth diode (D4) ), one end of the fourth capacitor (C4), the emitter terminal of the sixth triode (S6) and the anode of the sixth diode (D6); the cathode of the seventh diode (D7) is connected to the flying One end of the transcapacitor (Css), the source end of the first IGSFET (S1), the drain end of the second IGSFET (S2), the anode of the first diode (D1), and the second The cathode of the second diode (D2), the other end of the first capacitor (C1) is connected to one end of the second capacitor (C2); the anode of the eighth diode (D8) is connected to the other end of the flying capacitor (Css) simultaneously. One end, the source terminal of the third insulated gate field effect transistor (S3), the drain terminal of the fourth insulated gate field effect transistor (S4), the anode of the third diode (D3), the fourth diode (D4 ) of the cathode, one end of the third capacitor (C3) and the other end of the fourth capacitor (C4); the source terminal of the second insulated gate field effect transistor (S2) is connected to the third insulated gate field effect transistor (S3) at the same time ), the anode of the second diode (D2), the cathode of the third diode (D3), the other end of the second capacitor (C2), the other end of the third capacitor (C3) and the main transformer ( Tr1) is connected to the same-named end of the primary winding; the non-identical end of the primary winding of the main transformer (Tr1) is connected to one end of the resonant inductance (Lr); the other end of the resonant inductance (Lr) is simultaneously connected to the fifth triode (S5) The emitter terminal of the sixth transistor (S6), the anode of the fifth diode (D5) and the cathode of the sixth diode (D6) are connected; the non-secondary winding of the main transformer (Tr1) The terminal with the same name is connected to the anode of the first rectifier diode (DR1), the terminal with the same name of the secondary winding of the main transformer (Tr1) is connected to the anode of the second rectifier diode (DR2), and the cathode of the first rectifier diode (DR1) is connected to the first One of the inductance (Lf1) The terminal is connected to the cathode of the second rectifier diode (DR2), and the other terminal of the first inductor (Lf1) is connected to one terminal of the filter capacitor (C0) and one terminal of the load resistor (R0) at the same time; the other terminal of the filter capacitor (C0) is simultaneously The other end of the load resistor (R0) is connected to the center tap of the secondary winding of the main transformer (Tr1); it is characterized in that it also includes an auxiliary transformer (Tr2), a third rectifier diode (DR3), a fourth rectifier diode (DR4) , the second inductance (Lf2), the seventh insulated gate field effect transistor (S7) and the clamp capacitor (Cc); the source terminal of the seventh insulated gate field effect transistor (S7) is simultaneously connected with the first rectifier diode (DR1) The cathode of the second rectifier diode (DR2) is connected to one end of the first inductor (Lf1); the drain end of the seventh insulated gate field effect transistor (S7) is simultaneously connected to one end of the clamp capacitor (Cc) and the second One end of the inductor (Lf2) is connected, and the other end of the second inductor (Lf2) is connected to the cathode of the third rectifier diode (DR3) and the cathode of the fourth rectifier diode (DR4); the anode of the third rectifier diode (DR3) is connected to The non-identical terminal of the secondary winding of the auxiliary transformer (Tr2) is connected, and the anode of the fourth rectifier diode (DR4) is connected with the terminal of the same name of the secondary winding of the auxiliary transformer (Tr2); the other terminal of the clamping capacitor (Cc) is simultaneously connected with the filter capacitor The other end of (C0) is connected, the middle tap of the secondary winding of the auxiliary transformer (Tr2), the middle tap of the secondary winding of the main transformer (Tr1) is connected with the other end of the load resistor (R0); the primary winding of the auxiliary transformer (Tr2) The end of the same name is connected with the other end of the fifth capacitor (C5), one end of the sixth capacitor (C6), the anode of the seventh diode (D7) and the cathode of the eighth diode (D8); the auxiliary transformer ( Tr2) The non-identical end of the primary winding is simultaneously connected to the source terminal of the second insulated gate field effect transistor (S2), the drain terminal of the third insulated gate field effect transistor (S3), and the second diode (D2) The anode, the cathode of the third diode (D3), the other end of the second capacitor (C2), the other end of the third capacitor (C3) are connected to the end with the same name of the primary winding of the main transformer (Tr1).

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