CN101551988A - Method for operating display in DPMS mode - Google Patents

Abstract

A method for operating a display in a DPMS mode is suitable for the display to finish a working mode and enter the DPMS mode, under the DPMS mode, a signal processor of the display detects whether a connecting interface has no signal input, the signal processor enters a power-off state and informs a microcontroller to start a signal detection function to detect whether the connecting interface has the signal input, and when the microcontroller does not detect the signal input within a period of time, the microcontroller enters a sleep state to achieve the purpose of saving power of the display.

Description

A method for a display to operate in DPMS mode

technical field

The invention relates to a method for reducing display power consumption, especially a method for reducing display power consumption in DPMS mode.

Background technique

At present, the display power saving function usually follows the "Energy Star" specification of the US Environmental Protection Agency and the "Display Power Management Standard (DPMS; Display Power Management Standard)" developed by the International Video Electronics Standards Association (VESA; ManagementStandard)" to qualify. Among them, the Display Power Management Standard (DPMS) provides a display power management function. When the display does not have any input signal, this function will protect the screen and enter a power saving mode to reduce the power consumed by the display.

General display power management is divided into four modes: normal (Normal), standby (Standby), DPMS and off (Off) mode. As shown in Table 1, in these four modes, the signal processor and microcontroller in the display have different states, and the power consumption of the display in these four modes is also different.

Table I

The general mode is the working mode in which the monitor has picture output. The monitor, such as the monitor for LCD TV, has different working modes in the general mode, such as TV mode and computer mode. Different working modes have different signal sources. Among them, the standby mode is to turn off all signal sources. Therefore, the existing signal processor responsible for signal detection is also in a power-off state to save power. In addition, when the display switches from one of the working modes to another, the display must switch the signal source. During the switching process, the display enters the DPMS mode. At this time, the display detects the signal source. When no signal is detected, the display usually has no picture output, and if a signal is detected, the display enters the switched working mode and outputs a picture.

In the prior art, the signal processor is used to detect the signal. Therefore, in the DPMS mode, the signal processor is still in a sleep state, and in order to speed up the output of the picture after the signal is detected, the microcontroller therefore keeps In the working state, even in the above mode, the display still consumes a certain amount of power. Once the signal processor continues to detect no signal, the power consumption in the DPMS mode is very considerable. In view of this point, how to reduce the power consumption of the display in the DPMS mode is a problem that those familiar with this technology want to solve first.

Contents of the invention

In order to solve the above problems, the present invention discloses a method for a display to operate in the DPMS mode, which uses a microcontroller and logic gates to allow the display to consume the same power as the standby mode in the DPMS mode.

The steps included in the method disclosed by the present invention are as follows: in DPMS mode, the signal processor first detects whether there is a signal input on the connection interface, if there is no signal input, the signal processor notifies the microcontroller to open the signal detection function to detect The signal input of the connection interface; the signal processor executes the shutdown program to enter the power-off state, and notifies the microcontroller to enter the power-off state; the microcontroller turns on the signal detection function, and detects the connection interface, whether there is a signal input; The controller checks whether the pin of the logic gate connected to the microcontroller has a potential change, and the microcontroller detects that there is no signal input to the connection interface based on the potential change of the pin; There is no potential change within a predetermined time; if the pin has no potential change within the predetermined time, the microcontroller enters a sleep state and waits for the potential change of the pin.

It can be seen that the technical means of the present invention is that in the DPMS mode, if there is no signal input, the signal processor enters the power-off state, and uses a microcontroller to replace the signal processor to detect whether there is a signal input at the connection interface, and continuously When there is no signal input for a period of time, the microcontroller enters a sleep state, thereby achieving the purpose of saving power.

The above description of the content of the present invention and the following description of the implementation are used to demonstrate and explain the spirit and principle of the present invention, and to provide further explanation of the patent application scope of the present invention.

Description of drawings

Fig. 1 is a block diagram of a display system of the present invention;

FIG. 2A is a flow chart of the DPMS mode operation of the display of the present invention; and

FIG. 2B is a flow chart of the DPMS mode operation of the display of the present invention.

Description of main component symbols:

10.................................Display

101...................................Connection interface

102....................................Logic gates

103 ................................. Microcontrollers

104....................................Signal Processor

Step 201 The user switches the display from the first working mode of the normal mode to the second working mode

Step 202 The display ends the first working mode and enters the DPMS mode

Step 203 In DPMS mode, the signal processor detects whether there is a signal input to the connection interface

Step 204 If there is a signal input, the display ends the DPMS mode and enters the second working mode

Step 205 No signal input, the signal processor notifies the microcontroller to enable the signal detection function

Step 206 The signal processor executes the shutdown program to enter the power-off state, and notifies the microcontroller to enter the power-off state

Step 207 The microcontroller turns on the signal detection function, and detects whether there is a signal input on the connection interface

Step 208 The microcontroller checks whether the logic gate is connected to the pin of the microcontroller for potential change

Step 209 If there is a potential change, the microcontroller checks whether the number of potential changes reaches a predetermined value

Step 210 If the number of potential changes reaches the predetermined value, the microcontroller starts the signal processor

Step 211 If there is no potential change, the microcontroller checks whether the pin has no potential change within a predetermined time

Step 212 If the pin has no potential change within the predetermined time, the microcontroller enters the sleep state and waits for the pin to have a potential change

Detailed ways

The detailed features and advantages of the present invention are described in detail below in the embodiments, the content of which is sufficient to enable any person familiar with the relevant art to understand the technical content of the present invention and implement it accordingly, and according to the content disclosed in this specification, the scope of the patent application and the drawings , anyone skilled in the relevant art can easily understand the related objects and advantages of the present invention.

Inheriting the characteristics of the prior art, the display of the present invention supports four modes of display power management: general, standby, DPMS and off modes, and the technical means of the present invention is to reduce the operation of the display in the DPMS mode by changing the mode. Power consumption. Please refer to FIG. 1 , which is a system block diagram of a display 10 of the present invention. As shown in the figure, the display 10 includes electronic components such as a connection interface 101, a logic gate 102, a microcontroller 103 and a signal processor 104, wherein the connection interface 101 is coupled to The microcontroller 103 is coupled to the logic gate 102 and the signal processor 104 , and at least one electrical signal is transmitted between each coupled electronic component.

In the present invention, in the DPMS mode, the microcontroller 103 is used instead of the signal processor 104 to detect whether there is a signal input to the connection interface 101, so as to achieve the purpose of power saving of the display 10 . Please refer to FIG. 2A and FIG. 2B for the DPMS mode operation process of the display 10 of the present invention. At the beginning, the user switches the display 10 from the first working mode of the normal mode to the second working mode (step 201), and the display 10 will first End the first working mode and enter the DPMS mode (step 202). During the DPMS mode, the signal processor 104 first detects the signal source of the second working mode, that is, the connection interface 101, whether there is a signal input (step 203), if there is Signal input, display 10 then ends DPMS mode and enters the second working mode, and signal processor 104 processes the picture display of the second working mode (step 204); Continue step 203, if there is no signal input, signal processor 104 notifies microcontroller 103 turns on the signal detection function to detect the signal input of the connection interface 101 (step 205), the signal processor 104 executes the shutdown program to enter the power-off state, and notifies the microcontroller 103 that it enters the power-off state (step 206). Continuing with the procedure A of FIG. 2A , the microcontroller 103 starts the signal detection function, and detects the signal source of the second working mode, that is, the connection interface 101, whether there is a signal input (step 207), the present invention utilizes the logic gate 102 to connect The microcontroller 103 is connected to the connection interface 101, and the microcontroller 103 checks whether the pin of the logic gate 102 connected to the microcontroller 103 has a potential change to detect whether there is a signal input to the connection interface 101 (step 208), if there is a potential change , the microcontroller 103 checks whether the number of potential changes reaches a predetermined value (step 209), if the number of potential changes reaches the predetermined value, the microcontroller 103 turns on the signal processor 104, and the subsequent operation process is as described in step 203 ( Step 210); Subsequent to step 209, if the number of potential changes does not reach this predetermined value, then the continuous operation process is as described in step 208; Subsequent to step 208, if there is no potential change, microcontroller 103 checks whether the pin position is within a predetermined time There is no potential change (step 211) inside, if the pin position has no potential change within this predetermined time, then microcontroller 103 enters the sleep state, and waits for the pin position to have a potential change (step 212); If the potential of the bit changes within the predetermined time, the subsequent operation process is as described in step 208 .

According to a specific embodiment of the present invention, the display 10 can be a display of a liquid crystal television, and the first working mode supported by it can be a TV mode, and the second working mode can be a computer mode, and the signal source of the second working mode is connected to Interface 101, which can be a D-type (D-sub) connection port, digital video interface (DVI; Digital Visual Interface), high-definition multimedia transmission interface (HDMI; High-DefinitionMultimedia Interface) or unified display interface (UDI; Unified One of the types of Display Interface).

Taking the D-type connection port as an example, the present invention pulls signal lines from the tenth, eleventh, thirteenth and fourteenth pins of the D-type connection port to connect to the pins of the logic gate 102 and the signal processor 104, Among them, the tenth and eleventh pins belong to the signal ground of horizontal synchronization (H-Sync) and vertical synchronization (V-Sync); the thirteenth and fourteenth pins are respectively responsible for transmitting horizontal synchronization and vertical synchronization signals. In this embodiment, the logic gate 102 is connected to a general purpose input/output (GPIO; General Purpose Input/Output) pin of the microcontroller 103 and outputs a signal to this pin, if the general purpose input/output pin is enabled with a low potential , then the logic gate 102 can be a NOR-type logic gate, that is, when the D-type connection port has no signal input, the thirteenth and fourteenth pins are at low potential, and are connected to the micro output of the NOR-type logic gate 102. The general-purpose input/output pins of the controller 103 are high potential; on the other hand, when the D-type connection port has a signal input, the thirteenth and fourteenth pins are high potential, and the NOR logic gate outputs low potential. , the microcontroller 103 is enabled.

At the beginning, the user switches the display 10 from the TV mode to the computer mode (such as step 201 ), and the display 10 will first end the TV mode and enter the DPMS mode (such as step 202 ). In the DPMS mode, the signal processor 104 first detects whether the D-type connection port has horizontal synchronization and vertical synchronization signal input, that is, detects whether the potential of the D-type connection port connected to the signal processor 104 has a high or low potential change ( As in step 203), if the signal processor 104 detects that there is horizontal synchronization and vertical synchronization signal input, the display 10 ends the DPMS mode and enters the computer mode, and the signal processor 104 processes the picture display of the computer mode (such as step 204); if The signal processor 104 does not detect the signal input, and the signal processor 104 notifies the microcontroller 103 to enable the signal detection function to detect the signal input of the D-type connection port (eg step 205 ).

Afterwards, the signal processor 104 executes the shutdown procedure to enter the power-off state, and notifies the microcontroller 103 that it enters the power-off state (eg step 206 ). The microcontroller 103 turns on the signal detection function, and detects the signal input of the D-type connection port through the output of the NOR logic gate (such as step 207), and the microcontroller 103 checks that the NOR logic gate is connected to the microcontroller 103 Whether the potential level of the pin position changes (as in step 208), if the NOR type logic gate outputs a low potential, it means that the D-type connection port has horizontal synchronization and vertical synchronization signal input, and the microcontroller 103 checks whether the number of times of potential level changes reaches one Predetermined value (such as step 209), if the number of times the potential level changes reaches this predetermined value, then the microcontroller 103 turns on the signal processor 104, and the subsequent operation process is as described in step 203 (such as step 210); as in step 209, If the number of changes in the potential level does not reach the predetermined value, the subsequent operation process is as described in step 208; as in step 208, if there is no potential level change, the microcontroller 103 checks whether the pin has no potential level within a predetermined time Change (step 211), if there is no potential level change in the pin position within this predetermined time, the microcontroller 103 enters the sleep mode from the working mode, and waits for the pin position to have a potential level change (such as step 212); proceed to step 211, If the potential level of the pin changes within the predetermined time, the subsequent operation process is as described in step 208 .

Although the present invention is disclosed above with the foregoing embodiments, they are not intended to limit the present invention. Without departing from the spirit and scope of the present invention, all changes and modifications made belong to the scope of patent protection of the present invention. For the scope of protection defined by the present invention, please refer to the appended claims.

Claims (7)

1. a display is in the method for DPMS mode operating, be applicable to that switching described display as a user desires to enter one second mode of operation from one first mode of operation, and described display finishes described first mode of operation and the running when entering described DPMS pattern, it is characterized in that, comprise the following steps:

A connecting interface that utilizes a signal processor to detect described second mode of operation has the no signal input;

If described connecting interface no signal input, described signal processor is notified a microcontroller start signal detecting function;

The shutdown programm of carrying out described signal processor closes electricity condition to enter one;

Open the signal detection function of described microcontroller;

A pin position of checking described microcontroller has or not potential change;

If described pin position does not have potential change, described microcontroller checks whether described pin position does not all have potential change in a schedule time; And

If described pin position does not all have potential change in the described schedule time, then described microcontroller enters a sleep pattern, and waits for that potential change takes place in described pin position.

2. display as claimed in claim 1 is in the method for DPMS mode operating, it is characterized in that, described method is the described pin position that connects described connecting interface and described microcontroller with a logic gate, described logic gate is responded the signal input of described connecting interface, to produce the potential change of described pin position.

3. display as claimed in claim 1 is in the method for DPMS mode operating, it is characterized in that, the described connecting interface of detecting described second mode of operation at described signal processor has in the step of no signal input, if described connecting interface has the signal input, described display finishes described DPMS pattern and enters described second mode of operation, and the picture of described second mode of operation of described signal processor processes shows.

4. display as claimed in claim 1 is characterized in that in the method for DPMS mode operating, has or not the step of potential change in the described pin position of checking described microcontroller, also includes:

If there is potential change described pin position, described microcontroller checks whether the potential change number of times reaches a preset value; And

If the potential change number of times reaches described preset value, described microcontroller is opened described signal processor, and described signal processor is detected the step that described connecting interface has the no signal input.

5. display as claimed in claim 4 is characterized in that in the method for DPMS mode operating if the potential change number of times does not reach described preset value, described microcontroller checks that described pin position has or not the step of potential change.

6. display as claimed in claim 1 is in the method for DPMS mode operating, it is characterized in that, check at described microcontroller whether described pin position does not all have in the step of potential change in the described schedule time, if there is potential change described pin position in the described schedule time, described microcontroller checks that described pin position has or not the step of potential change.

7. display as claimed in claim 2 is characterized in that in the method for DPMS mode operating described logic gate is a NOR type logic gate.

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