CN101533817B - Semiconductor packaging structure with pins on bearing seat - Google Patents
Semiconductor packaging structure with pins on bearing seat Download PDFInfo
- Publication number
- CN101533817B CN101533817B CN 200810084956 CN200810084956A CN101533817B CN 101533817 B CN101533817 B CN 101533817B CN 200810084956 CN200810084956 CN 200810084956 CN 200810084956 A CN200810084956 A CN 200810084956A CN 101533817 B CN101533817 B CN 101533817B
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- CN
- China
- Prior art keywords
- pins
- lead frame
- chip
- pin
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention provides a semiconductor packaging structure with pins on a bearing seat, which mainly comprises two or more lead frame pins, a chip, a pin bearing seat, adhesive and a sealing adhesive body for sealing the components, wherein the pin bearing seat is provided with a bearing surface and an exposed surface. The first chip is attached to the surfaces of the lead frame pins. The adhesive is adhered to the opposite surfaces of the lead frame pins and the bearing surface of the pin bearing seat so that the lead frame pins are combined with the pin bearing seat, and the adhesive covers the pin gaps of the lead frame pins and can be controlled not to pollute the exposed surface. The exposed surface of the lead bearing seat is exposed from the sealing colloid. Therefore, the lead frame pins are well supported, the sealed parts of the lead frame pins cannot be displaced or/and exposed out of the sealing colloid during molding, no sealing colloid bubbles are generated between the lead frame pins and the lead bearing seats, and the heat dissipation efficiency can be improved.
Description
Technical field
The present invention is particularly to the semiconductor packaging structure of a kind of pin on bearing relevant for a kind of semiconductor device, can be applicable to multi-chip stack.
Background technology
In the known semiconductor packaging structure, the lead frame pin can be simultaneously as the chip carrier and the media of electrically transferring.For example, thin-type small-size encapsulation (TSOP, Thin Small Outline Package), pin (LOC on chip, Lead On Chip) or chip (COL on pin, Chip On Lead), it all is that chip is arranged on the lead frame pin, utilizes adhesive body sealing chip and lead frame pin again.The lead frame pin of above-mentioned encapsulated type can be sticked so that chip to be provided in order to replace chip bearing (die pad).Yet it only supports the chip that is arranged at its top by the lead frame pin, often has the supportive deficiency to cause the problem of mould envelope displacement.
In the process of mould envelope injecting glue, be subjected to the influence of mould flowing pressure, can cause the lead frame pin to produce and rock or displacement because of the supportive deficiency of lead frame pin, so the situation that routing, lead frame pin or chip expose outside adhesive body takes place most probably, makes the encapsulation fraction defective improve more.In order to reduce the improper probability that exposes of intraware, can increase the distance of lead frame pin to the adhesive body edge, so that routing, lead frame pin or chip are unlikely to expose outside adhesive body because of slight displacement, cause package dimension to become big, but but also therefore shortened the stack height of chip, and can't the more chip of storehouse.In addition, the chip that frequency or power are high more also relatively sends more heats when computing, and chip and lead frame pin are high more to the big more then thermal resistance of distance at adhesive body edge, so radiating effect is limited.When heat energy that chip produced can't be passed to the external world and make the temperature of chip too high, can produce thermal phenomena, then cause the problem of chip failure easily.
Summary of the invention
Main purpose of the present invention is to provide a kind of semiconductor packaging structure of pin on bearing that makes the lead frame pin obtain excellent support and have the effect of promoting heat dissipation and increase chip stack space.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to the semiconductor packaging structure of a kind of pin provided by the present invention on bearing, mainly comprise two or more lead frame pins, first chip, pin bearing, viscose and adhesive body.Each lead frame pin has first surface, opposing second surface and two or more sides between first surface and second surface.This first chip is attached at the first surface of described lead frame pin.This pin bearing has loading end and exposed face.This loading end of this this pin bearing of viscose gluing and the second surface of described lead frame pin, so that this pin bearing is attached at described lead frame pin, this viscose more covers to the side of described lead frame pin.This adhesive body seals the periphery of the loading end of the interior pin of this first chip, this viscose, this lead frame pin and this pin bearing, and this exposed face that makes this pin bearing is for appearing.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
In above-mentioned semiconductor packaging structure, this adhesive body coats this viscose fully.
In above-mentioned semiconductor packaging structure, the periphery of this exposed face of this pin bearing forms and makes the breach of the area of this exposed face less than the area of this loading end.
In above-mentioned semiconductor packaging structure, this adhesive body fills up this breach.
In above-mentioned semiconductor packaging structure, this breach is rectangular or be square.
In above-mentioned semiconductor packaging structure, described semiconductor packaging structure includes two or more first bonding wires in addition, and described first bonding wire electrically connects this first chip to described lead frame pin.
In above-mentioned semiconductor packaging structure, this viscose seals described first bonding wire.
In above-mentioned semiconductor packaging structure, this viscose comprises the insulating resin with stress buffer characteristic.
In above-mentioned semiconductor packaging structure, this first chip has two or more first silicon through holes that electrically conducts, and the described first silicon through hole is electrically connected to described lead frame pin.
In above-mentioned semiconductor packaging structure, described semiconductor packaging structure includes at least one second chip in addition, and described second chip is stacked at this first chip also relatively away from described lead frame pin.
In above-mentioned semiconductor packaging structure, this second chip has two or more second silicon through holes that electrically conducts.
In above-mentioned semiconductor packaging structure, described semiconductor packaging structure includes two or more first bonding wires in addition, and described first bonding wire electrically connects this second chip to described lead frame pin.
The semiconductor packaging structure of pin of the present invention on bearing makes the lead frame pin obtain excellent support, pin the inner when mould seals (by the sealing position) can displacement with expose, and can not produce the sealing bubble between lead frame pin and the pin bearing.In addition, but have the effect of promoting heat dissipation and increase chip stack space.And the semiconductor packaging structure of pin of the present invention on bearing can avoid aqueous vapor to invade.
In addition, the semiconductor packaging structure of pin of the present invention on bearing, the may command viscose is spread and is covered to the side of lead frame pin and can not spread the exposed face of pin bearing, guarantee viscose by covered effect, increase the pull-out capacity of adhesive body simultaneously in conjunction with the pin bearing.
The semiconductor packaging structure of pin of the present invention on bearing can also effectively be electrically connected to the lead frame pin at the chip of limited package dimension storehouse greater number.
Description of drawings
Fig. 1 is the schematic cross-section according to the semiconductor packaging structure of pin on bearing of first specific embodiment of the present invention;
Fig. 2 is the vertical view according to this semiconductor packaging structure of first specific embodiment of the present invention;
Fig. 3 is the schematic partial cross-sectional view according to these two or more lead frame pins of semiconductor packaging structure crosscut of first specific embodiment of the present invention;
Fig. 4 is for using the vertical view of different exposed face shape pin bearings according to this semiconductor packaging structure of first specific embodiment of the present invention;
Fig. 5 is for using the vertical view of different exposed face shape pin bearings according to this semiconductor packaging structure of first specific embodiment of the present invention;
Fig. 6 is for using the vertical view of different exposed face shape pin bearings according to this semiconductor packaging structure of first specific embodiment of the present invention;
Fig. 7 is for using the vertical view of different exposed face shape pin bearings according to this semiconductor packaging structure of first specific embodiment of the present invention;
Fig. 8 is the schematic cross-section according to the semiconductor packaging structure of another kind of pin on bearing of second specific embodiment of the present invention;
Fig. 9 is the schematic partial cross-sectional view according to these two or more lead frame pins of semiconductor packaging structure crosscut of second specific embodiment of the present invention.
Description of reference numerals
100 semiconductor packaging structures
110 lead frame pins, 111 first surfaces, 112 second surfaces
113 sides
120 first chips, 121 first silicon through holes
130 pin bearings, 131 loading ends, 132 exposed faces
133 breach, 134 marks
130A pin bearing 132A exposed face 133A breach
130B pin bearing 132B exposed face 133B breach
130C pin bearing 132C exposed face 133C breach
130D pin bearing 132D exposed face 133D breach
140 viscoses, 150 adhesive bodies
160 second chips, 161 second silicon through holes
170 bonding wires, 180 glutinous crystal layers
200 semiconductor packaging structures
210 first lead frame pins, 211 first surfaces
212 second surfaces, 213 sides
220 first chips, 221 first silicon through holes
230 pin bearings, 231 loading ends, 232 exposed faces
233 breach
240 viscoses, 250 adhesive bodies
260 second chips, 261 second silicon through holes
271 first bonding wires, 272 second bonding wires, 280 glutinous crystal layers
290 second lead frame pins
292 the 4th surfaces, 291 the 3rd surfaces
Embodiment
According to first specific embodiment of the present invention, provide the semiconductor packaging structure of a kind of pin on bearing.See also Figure 1 and Figure 2, the semiconductor packaging structure 100 of a kind of pin on bearing mainly comprises two or more lead frame pins 110, first chip 120, pin bearing 130, viscose 140 and adhesive body 150.See also Fig. 1 and shown in Figure 3, each lead frame pin 110 has first surface 111, opposing second surface 112 and two or more sides 113 (as shown in Figure 3) between first surface 111 and second surface 112, wherein this side 113 is towards the side of adjacent wires frame pin 110, to constitute the pin gap.Side and bending that those lead frame pins 110 can extend this adhesive body 150 outward are the outer pin of sea-gull pin or other shape, so that this semiconductor packaging structure 100 can be engaged to external printed circuit board (not drawing among the figure).
As Fig. 1 and shown in Figure 3, this first chip 120 is attached at the first surface 111 of those lead frame pins 110.Can utilize pasting of glutinous crystal layer 180, for example polyimides (PI) adhesive tape etc. makes this first chip, 120 glutinous those lead frame pins 110 of being located at.This semiconductor packaging structure 100 can include two or more first bonding wires 170 in addition, and it electrically connects this first chip 120 to those lead frame pins 110.One end of those first bonding wires 170 is connected to two or more electrodes of this first chip 120, and the interior termination that the other end of those first bonding wires 170 can be connected to those lead frame pins 110 refers to (finger) and is positioned at this second surface 112.In the present embodiment, the interior termination finger-type of those lead frame pins 110 is formed on this chip 120, with by clamping between this first chip 120 and this pin bearing 130, in conjunction with those lead frame pins 110, and make those first bonding wires 170 between this first chip 120 and this pin bearing 130 so as to firmly.In addition, this first chip 120 can have two or more first silicon through holes 121 that electrically conducts, and other stack chip also can be electrically connected to those lead frame pins 110 by those first bonding wires 170 in order to electrically conduct.
As shown in Figure 1 to Figure 3, this pin bearing 130 has loading end 131 and exposed face 132.This pin bearing 130 can be selected from one of them of sheet metal, potsherd and empty chip (dummy chip).Preferably, this pin bearing 130 has good heat radiating.As Fig. 1 and shown in Figure 3, the size of this pin bearing 130 can be slightly larger than the size of this first chip 120, but is slightly less than the top surface area of this adhesive body 150, to provide those lead frame pins 110 preferable support effect.This loading end 131 can be for the setting of those lead frame pins 110, and this exposed face 132 is relatively away from those lead frame pins 110, and can be revealed in outside this adhesive body 150.In the present embodiment, the periphery of this exposed face 132 of this pin bearing 130 can form breach 133, so that the area of this exposed face 132 is less than the area of this loading end 131.See also shown in Figure 2, this exposed face 132 can be used as marked region, be formed with mark 134 above it, this mark 134 can be in order to name of an article specification (as: PTI TSOP (I) 48L 43nm 32G ABL12062007 Taiwan), build date or the place of production etc. that indicate this semiconductor packaging structure 100.The formation method of this mark 134 can be selected from one of them of radium-shine mode and ink printing.
See also shown in Figure 1ly, this loading end 131 of this this pin bearing 130 of viscose 140 gluings and the second surface 112 of those lead frame pins 110 are so that this pin bearing 130 is attached at those lead frame pins 110.See also shown in Figure 3ly, this viscose 140 more covers those sides 113 to those lead frame pins 110, to increase the area of pasting of this viscose 140, strengthens the adhesion of those lead frame pins 110 and this pin bearing 130.This viscose 140 can be selected liquid state colloid or the thick attitude colloid of glue for use, and the thick attitude B of liquid-state epoxy resin or glue rank viscose (B-stage adhesive) for example is with the coverage effect of those sides 113 of increasing those lead frame pins 110.Preferably, this viscose 140 can comprise the insulating resin with stress buffer characteristic, so that the function of stress absorption and buffering to be provided.In the present embodiment, as shown in Figure 1, these viscose 140 salable those first bonding wires 170.After pasting this first chip 120, the mode that this viscose 140 can print is formed on the second surface 112 of those pins 110, and this viscose 140 can more be inserted the gap (as shown in Figure 3) between those lead frame pins 110.Perhaps, this viscose 140 can be pre-formed this loading end 131 in this pin bearing 130.Therefore, in the process that this adhesive body 150 forms, filled up by this viscose 140 between this pin bearing 130 and those lead frame pins 110, can not produce bubble, this adhesive body 150 can not need to insert again.Because the area of this exposed face 132 of this pin bearing 130 forms the breach 133 that these pin bearing 130 peripheral thicknesses are reduced less than the area of this loading end 131 and at the periphery of this exposed face 132, spread covering can not spread this pin bearing 130 to those sides 113 of those lead frame pins 110 this exposed face 132 and side thereof so can control this viscose 140, guarantee the covered effect of this viscose 140.
See also shown in Figure 1, these adhesive body 150 these first chips 120 of sealing, this viscose 140, a position of those lead frame pins 110 and a position of this pin bearing 130, and this exposed face 132 that makes this pin bearing 130 is for appearing, wherein those lead frame pin 110 sealed positions are interior pin, and these pin bearing 130 sealed positions comprise the periphery of this loading end 131.Therefore, this adhesive body 150 can coat this viscose 140 fully, to avoid causing layering (delamination) because of the aqueous vapor intrusion.Preferably, this adhesive body 150 can fill up this breach 133, increases the pull-out capacity of this adhesive body 150 in conjunction with this pin bearing 130.
Therefore, those lead frame pins 110 obtain excellent support, its pin the inner can displacement with expose to outside this adhesive body 150.When sealing by the support of this pin bearing 130, make those lead frame pins 110 can firmly be arranged at this pin bearing 130 with this first chip 120, so those lead frame pins 110 and this first chip 120 can be because of the influences of mould flowing pressure, rock or the phenomenon of displacement and have.And can make between those lead frame pins 110 and this pin bearing 130 by this viscose 140 and can not produce the sealing bubble.In addition, because this exposed face 132 of this pin bearing 130 is revealed in this adhesive body 150, so the heat energy that this first chip 120 is produced when computing can be passed to the external world with this pin bearing 130 by this viscose 140, to promote heat dissipation and can increase the chip stack space.
For in response to other functional requirement or in order to increase memory size, can be on this first chip 120 another chip of storehouse.See also shown in Figure 1ly, this semiconductor packaging structure 100 can include at least one second chip 160 in addition, and it is stacked at this first chip 120 and relatively away from those lead frame pins 110.In the present embodiment, this second chip 160 can have two or more second silicon through holes 161 that electrically conducts, and can electrically connect two or more storehouse second chips 160.In one embodiment, those second silicon through holes 161 can be vertical corresponding connection with those first silicon through holes 121, being electrically connected to first chip 120, even can be electrically connected to those lead frame pins 110 by those first bonding wires 170.
In one embodiment, see also shown in Figure 2ly, this exposed face 132 of this pin bearing 130 can be rectangle, and this breach 133 can be the rectangle continuous circular shape and covered by this adhesive body 150.In different embodiment, see also shown in Figure 4ly, the exposed face 132A of another kind of pin bearing 130A can be circle, and the breach 133A of this pin bearing 130A is the continuous loop of complementary shape and is covered by this adhesive body 150.In another embodiment, see also shown in Figure 5ly, the exposed face 132B of a kind of pin bearing 130B can be ellipse, and the breach 133B of this pin bearing 130B also can be continuous circular shape and covered by this adhesive body 150.In another embodiment, see also shown in Figure 6ly, the exposed face 132C of a kind of pin bearing 130C is a rectangle, and the breach 133C of this pin bearing 130C can be formed at two relative sides of this pin bearing 130C, can be strip and is covered by this adhesive body 150.In another embodiment, see also shown in Figure 7ly, the breach 133D of a kind of pin bearing 130D can be formed at four jiaos of this pin bearing 130D, can be square and is covered by this adhesive body 150.
In second specific embodiment of the present invention, provide the semiconductor packaging structure of another kind of pin on bearing.See also shown in Figure 8, this semiconductor packaging structure 200 mainly comprises two or more first lead frame pins 210, first chip 220, pin bearing 230, viscose 240 and adhesive body 250, and the above primary clustering and first specific embodiment are described roughly the same.See also Fig. 8 and shown in Figure 9, each first lead frame pin 210 has first surface 211, opposing second surface 212 and two or more sides 213 (as shown in Figure 9) between first surface 211 and second surface 212.This first chip 220 is attached at the first surface 211 of those first lead frame pins 210.As Fig. 8 and shown in Figure 9, can utilize pasting of glutinous crystal layer 280, make this first chip 220 be attached at those first lead frame pins 210, should glutinous crystal layer 280 more can local those sides 213 that cover those first lead frame pins 210, to increase the area of pasting of this glutinous crystal layer 280, strengthen the adhesion of those first lead frame pins 210 and this first chip 220.In the present embodiment, this semiconductor packaging structure 200 can comprise two or more second lead frame pins 290, it is shorter than those first lead frame pins 210, and do not attached by this first chip 220, wherein each second lead frame pin 290 has the 291 and the 4th surface 292, the 3rd surface.Those second lead frame pins 290 are carried on this pin bearing 230 as those first lead frame pins 210 by this viscose 240.This pin bearing 230 has loading end 231 and exposed face 232.This first chip 220 can have two or more first silicon through holes 221 that electrically conducts, and can be used as electrically conducting of chip stack.The periphery of this exposed face 232 of this pin bearing 230 can form breach 233, so that the area of this exposed face 232 is less than the area of this loading end 231 and avoid these viscose 240 pollution load of overflow to produce to this exposed face 232 exposing and the mould envelope glue that overflows.Please consult shown in Figure 9 again, this loading end 231 of this this pin bearing 230 of viscose 240 gluings and the second surface 212 of those first lead frame pins 210, so that those first lead frame pins 210 are attached at this pin bearing 230, this viscose 240 more covers those sides 213 to those first lead frame pins 210.In the present embodiment, but this viscose 240 the 4th surface 292 of this pin bearing of gluing 230 and those second lead frame pins 290 more, so that those second lead frame pins 290 can be attached at this pin bearing 230.These adhesive body 250 these first chips 220 of sealing, this viscose 240, a position of those first lead frame pins 210, a position of those second lead frame pins 290 and a position of this pin bearing 230, and this exposed face 232 that makes this pin bearing 230 is for appearing, to increase radiating effect.
Therefore, the syntagmatic of this pin bearing 230 can provide this first chip 220 and this second chip 260 effective pin support effect in the process that forms this adhesive body 250, the displacement and the tilt problem that those first lead frame pins 210, those second lead frame pins 290, this first chip 220 take place to avoid being subjected to the influence of mould flowing pressure.
In the present embodiment, at least one second chip 260 is stacked at this first chip 220 also relatively away from those first lead frame pins 210.In the present embodiment, this semiconductor packaging structure 200 can include two or more first bonding wires 271 and two or more second bonding wires 272 in addition, and it electrically connects this second chip 260 respectively to those first lead frame pins 210 and to those second lead frame pins 290.See also shown in Figure 8, this second chip 260 can have two or more second silicon through holes 261 that electrically conducts, itself and those first silicon through hole 221 is vertically to connect, and this first chip 220 also can be electrically connected to those first bonding wires 271 and those second bonding wires 272 in order to electrically conduct.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction, and the technical solution of the present invention scope is when being as the criterion according to claims.Any those skilled in the art can utilize the technology contents of above-mentioned announcement to make a little change or be modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, technical spirit according to the present invention all still belongs in the scope of technical solution of the present invention any simple modification, equivalent variations and modification that above embodiment did.
Claims (12)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810084956 CN101533817B (en) | 2008-03-10 | 2008-03-10 | Semiconductor packaging structure with pins on bearing seat |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810084956 CN101533817B (en) | 2008-03-10 | 2008-03-10 | Semiconductor packaging structure with pins on bearing seat |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101533817A CN101533817A (en) | 2009-09-16 |
| CN101533817B true CN101533817B (en) | 2010-09-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810084956 Expired - Fee Related CN101533817B (en) | 2008-03-10 | 2008-03-10 | Semiconductor packaging structure with pins on bearing seat |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104505380A (en) * | 2014-12-19 | 2015-04-08 | 日月光封装测试(上海)有限公司 | Semiconductor packaging body and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5708295A (en) * | 1995-04-28 | 1998-01-13 | Matsushita Electronics Corporation | Lead frame and method of manufacturing the same, and resin sealed semiconductor device and method of manufacturing the same |
| CN101118893A (en) * | 2006-08-02 | 2008-02-06 | 南茂科技股份有限公司 | Semiconductor package structure with common die pad |
| CN101136386A (en) * | 2006-08-28 | 2008-03-05 | 力成科技股份有限公司 | Chip packaging structure and manufacturing method thereof |
-
2008
- 2008-03-10 CN CN 200810084956 patent/CN101533817B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5708295A (en) * | 1995-04-28 | 1998-01-13 | Matsushita Electronics Corporation | Lead frame and method of manufacturing the same, and resin sealed semiconductor device and method of manufacturing the same |
| CN101118893A (en) * | 2006-08-02 | 2008-02-06 | 南茂科技股份有限公司 | Semiconductor package structure with common die pad |
| CN101136386A (en) * | 2006-08-28 | 2008-03-05 | 力成科技股份有限公司 | Chip packaging structure and manufacturing method thereof |
Non-Patent Citations (1)
| Title |
|---|
| JP昭62-203358A 1987.09.08 |
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| CN101533817A (en) | 2009-09-16 |
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