CN101521500B - Data Latch Circuit Using Phase Selector - Google Patents

Abstract

The invention provides a data latch circuit. The data latch circuit includes: a first data latch unit for latching a first input data according to a first clock signal and outputting a first output data; a second data latch unit for latching the first output data according to a second clock signal and outputting a second output data; a third data latch unit for latching the second output data according to a third clock signal and outputting an output data; and a phase selector, coupled to the second data latch unit, for generating the second clock signal to the second data latch unit according to a phase relationship between the first and third clock signals.

Description

The data-latching circuit of adopting phase selector

Technical field

The present invention relates to a kind of data sink and method, particularly a kind of data-latching circuit of adopting phase selector and method.

Background technology

In the perhaps more large-scale chip of some interface systems; Keeping each local clock of chip identical is to the maximum challenge of system; Usually all can comprise digital circuit part and artificial circuit part in the existing chip; And the digital circuit part has almost accounted for the main area more than 80% of chip; So; Circuit designers is normally gone to estimate the driving force and the capacity effect that the circuit layout cabling is produced of the clock partly exported from digital circuit by the Design of Digital Circuit aspect when the sequence problem of the whole integrated circuit of planning, and via analyzing and estimating the retardation between the clock of last arrival artificial circuit part and clock that original clock source is exported; Partly solve the problem of clock phase mistake at last via digital circuit; A kind of in addition situation that sequence problem can take place is for when having two clock generators in the system, and these two clock generator institute clock signals are under nonsynchronous situation, and the problem (Timing Violation) on the sequential can take place for trigger or data latching element.

In general circuit design, will avoid clock inconsistent, prior art is to use two continuous D flip-flops to be used as the data latching element, goes the data that input is come in are carried out repeated sampling, to guarantee the correctness of data sampling.As shown in Figure 1, available data latch cicuit 100 includes the trigger 102,104,106 of three serial connections, wherein, receives input data D _InTrigger 102 be by one first clock CLK _iTrigger, two follow-up continuous trigger devices 104,106 are then by another second clock CLK ₂Trigger, the data output end by trigger 106 latchs a dateout D at last _OutYet if the setting-up time (setup time) of trigger and data duration (hold time) are not enough, lock circuit 100 still can have the problem of error in data, and is as shown in Figure 2, as trigger 104 sampled data D ₁Obtain data D ₂The time, the input data D if trigger 102 is being taken a sample _In, then because data D ₁Logical value just on the turn, so trigger 104 resulting data D ₂Just can't guarantee correctly, thereby can further influence the dateout D of last generation _OutCorrectness.In other words, latch the correctness that element (that is trigger 104,106) promotes sampled data even available data latch cicuit 100 is used two continuous datas, yet it still can receive the first clock CLK ₁With second clock CLK ₂Between improper phase relation influence and have the probability of missampling.

Summary of the invention

Therefore one of main purpose of the present invention is to provide a kind of data-latching circuit of adopting phase selector and method to solve the problems referred to above.

According to embodiments of the invention, it discloses a kind of data-latching circuit.This data-latching circuit includes: one first data latch unit is used for importing data according to one first clock signal to latch one first, and exports one first dateout; One second data latch unit is used for according to a second clock signal latching this first dateout, and exports one second dateout; One the 3rd data latch unit is used for according to one the 3rd clock signal latching this second dateout, and exports a dateout; And a phase selector, be coupled to this second data latch unit, be used for producing this second clock signal to this second data latch unit according to the phase relation of this first, the 3rd clock signal.

Description of drawings

Fig. 1 is the sketch map of available data latch cicuit.

Fig. 2 is the time sequential routine figure of data-latching circuit shown in Figure 1.

Fig. 3 is the sketch map of an embodiment of data-latching circuit of the present invention.

Fig. 4 is the circuit diagram of an embodiment of phase selector shown in Figure 3.

Fig. 5 is the phase difference of first, second clock signal and the first corresponding relation sketch map of voltage.

Fig. 6 is the phase difference of first, second clock signal and the second corresponding relation sketch map of voltage.

Fig. 7 is the circuit diagram of another embodiment of phase selector shown in Figure 3.

Fig. 8 is the flow chart of an embodiment of data latching method of the present invention.

The reference numeral explanation

100、300	Data-latching circuit
		102、104、106、302、304、306	Trigger
308	Phase selector
		402	Phase detectors
404	Filter
		406	Hysteresis buffer
408	Multiplexer

410	Inverter
		412	Delay cell

Embodiment

See also Fig. 3, Fig. 3 is the sketch map of an embodiment of data-latching circuit 300 of the present invention.In the present embodiment, data-latching circuit 300 includes trigger (for example D flip-flop) 302,304,306 and one phase selector 308 of three serial connections, wherein, receives input data D _InTrigger 302 be by one first clock CLK ₁Trigger, the trigger 306 that produces dateout at last is then by another the 3rd clock CLK ₃Trigger.For the trigger 304 in the middle of the place, position, it is by a second clock CLK ₂Trigger and second clock CLK ₂Be according to the first clock CLK by phase selector 308 ₁With the 3rd clock CLK ₃Between phase relation produce, in the present embodiment, phase selector 308 is according to the first clock CLK ₁With the 3rd clock CLK ₃Between phase relation come optionally to use the 3rd clock CLK ₃Or the 3rd clock CLK ₃Inversion signal be used as second clock CLK ₂Yet,, the present invention is not exceeded with inversion signal, also can adopt the 3rd clock CLK ₃Delay clock signals as inventive embodiment.

See also Fig. 4, Fig. 4 is the circuit diagram of an embodiment of phase selector 308 shown in Figure 3.Phase selector 308 includes phase detectors 402, a filter 404, a magnetic hysteresis (hysteresis) buffer 406, a multiplexer 408 and an inverter 410.Among this embodiment; Phase detectors 402 are to be implemented by an xor logic door, and filter 404 is the low pass filters that are made up of a resistance R and a capacitor C, and magnetic hysteresis (hysteresis) buffer 406 is to be implemented by Schmidt trigger (Schmitt trigger); Please note; Above-mentioned xor logic door, low pass filter and Schmidt trigger only are used as phase detectors 402, filter 404 explains that with the example of hysteresis buffer 406 in addition, inverter 410 also can be replaced by delay circuit; To produce needed clock phase, those elements are not to be necessary restrictive condition of the present invention.As shown in the figure, phase detectors 402 are the first clock CLK relatively ₁With the 3rd clock CLK ₃Phase relation export a detection signal S _d, then, filter 404 can be to detection signal S _dCarry out Filtering Processing (that is LPF) and come smoothing detection signal S _dWaveform to produce a filtering signal S _f, wherein, an end of capacitor C can be set up filtering signal S _fCorresponding voltage V _aBecause hysteresis buffer 406 has hysteresis characteristic, supposes that hysteresis characteristic is by two critical value V _TH_ 01 and V _TH_ 10 (V _TH_ 01＞V _TH_ 10) define, that is, as the hysteresis buffer 406 present control signal S that export _cLogic level be " 0 " and voltage V _aRise to and meet or exceed critical value V _TH_ 01 o'clock, then hysteresis buffer 406 can make control signal S _cBy logic level " 0 " transition to logic level " 1 "; On the other hand, as the hysteresis buffer 406 present control signal S that export _cLogic level be " 1 " and voltage V _aDrop to and reach or subcritical value V _TH_ 10 o'clock, then hysteresis buffer 406 can make control signal S _cBy logic level " 1 " transition to logic level " 0 ".In the present embodiment, use hysteresis buffer 406 can avoid multiplexer 408 because voltage V _aSlight fluctuations promptly at the 3rd clock signal clk ₃With its inversion signal CLK ₃Constantly switch between _ the B, thereby cause the output of phase selector 308 unstable, possibly cause missampling at last.Yet, note that hysteresis buffer 406 can be omitted (optional) element if the slight output pulsation of phase selector 308 can not cause under the situation of system mistake.

See also Fig. 5 and Fig. 6, Fig. 5 is the first, the 3rd clock signal clk ₁, CLK ₃Phase difference and voltage V _aThe first corresponding relation sketch map, and Fig. 6 is the first, the 3rd clock signal clk ₁, CLK ₃Phase difference and voltage V _aThe second corresponding relation sketch map.If the first, the 3rd clock signal clk ₁, CLK ₃Have identical cycle (period) and work period (duty cycle), then when the first, the 3rd clock signal clk ₁, CLK ₃(positive edge differs from 180 degree) can make voltage V when inverting each other _aCorrespond to maximum V _Dd(V _DdBe detection signal S _dThe counterlogic level " 1 " time voltage level), and when the first, the 3rd clock signal clk ₁, CLK ₃Same phase time (positive edge alignment) can make voltage V _aCorrespond to minimum value 0, wherein, phase difference PA, the equal corresponding critical value V of PD _TH_ 10, and phase difference PB, the equal corresponding critical value V of PC _TH_ 01.In addition, if the first, the 3rd clock signal clk ₁, CLK ₃Have the identical cycle, but have different duty cycles, then the first, the 3rd clock signal clk respectively ₁, CLK ₃Phase difference and voltage V _aRelation just as shown in Figure 6, suppose the first, the 3rd clock signal clk ₁, CLK ₃Cycle be T, and in the period of one-period T, first clock signal clk ₁The time span and the 3rd clock signal clk of logic level " 1 " ₃Time difference of time span of logic level " 1 " be T _DcSo,, when the first, the 3rd clock signal clk ₁, CLK ₃(positive edge differs 180 degree) can be because time difference T when inverting each other _DcA direct current side-play amount (T who is caused _Dc/ T) * V _DdAnd make voltage V _aOnly can rise to V _Dd-(T _Dc/ T) * V _DdBut not aforementioned maximum V _Dd, and when the first, the 3rd clock signal clk ₁, CLK ₃Same phase time (positive edge alignment) can be because time difference T _DcDc offset (the T that is caused _Dc/ T) * V _DdAnd make voltage V _aOnly can drop to (T _Dc/ T) * V _DdBut not aforementioned minimum value 0.In sum, via suitable critical value V _TH_ 01, V _TH_ 10 set, and hysteresis buffer 406 just can normal operation under the different clocks condition.

At last, two inputs of multiplexer 408 can receive the 3rd clock signal clk respectively ₃And correspondence the 3rd clock signal clk of being exported by inverter 410 ₃Inversion signal CLK ₃_ B, and multiplexer 408 is just according to control signal S _cLogic level export inversion signal CLK ₃_ B or the 3rd clock signal clk ₃With as triggering the required second clock CLK of trigger 304 ₂

See also Fig. 7, Fig. 7 is the circuit diagram of another embodiment of phase selector 308 shown in Figure 3.Except element shown in Figure 4, the phase selector 308 in the present embodiment includes a delay cell 412 in addition, is coupled to the output of multiplexer 408, is used for applying a retardation T _dGive output signal (the 3rd clock signal clk of inverter 410 ₃Or corresponding to the 3rd clock signal clk ₃Inversion signal CLK ₃_ B), just export desired second clock signal CLK at last ₂The setting of delay cell 412 is to be used for further finely tuning the phase relation between trigger 302,304 employed clock signals, that is lets first clock signal clk ₁With second clock signal CLK ₂The desirable rp state of convergence more, with further improvement because the data sampling problem that caused of the setting-up time (setup time) of trigger and data duration (hold time), in brief, the retardation T that delay cell 412 is provided _dCan increase margin (margin) to avoid the generation of data sampling mistake.How to set the retardation T that delay cell 412 is applied _dTo detail down.

For the ease of explanation retardation T _dSetting, below only with the first, the 3rd clock signal clk ₁, CLK ₃Having identical cycle and work period is example.Please consult Fig. 5 and Fig. 7 simultaneously, when the first, the 3rd clock signal clk ₁, CLK ₃Between phase difference be promoted to above PB or be reduced to and be lower than PC, control signal S then _cCan by logic level be " 0 " transition to logic level " 1 ", in addition, as control signal S _cPresent logic level is " 1 ", and the first, the 3rd clock signal clk ₁, CLK ₃Between phase difference drop in the scope of PA-PD control signal S then _cLogic level still can remain " 1 ".As control signal S _cLogic level when being " 1 ", expression the first, the 3rd clock signal clk ₁, CLK ₃Than convergence anti-phase relation, therefore, multiplexer 408 can be selected output the 3rd clock signal clk ₃By on can know, select output the 3rd clock signal clk at multiplexer 408 ₃Situation under, retardation T _dThis moment, maximum only can a corresponding phase difference (360-PD), so, at control signal S _cLogic level be under the mode of operation of " 1 ", retardation T _dJust have like limit:

$T_d\≤\frac{T\·V_{\mathrm{TH}\_10}}{2V_{\mathrm{Dd}}}$ Formula (1)

On the other hand, when the first, the 3rd clock signal clk ₁, CLK ₃Between phase difference be reduced to and be lower than PA or be promoted to, control signal S then above PD _cCan by logic level be " 1 " transition to logic level " 0 ", in addition, as control signal S _cPresent logic level is " 0 ", and the first, the 3rd clock signal clk ₁, CLK ₃Between phase difference do not drop in the scope of PB-PC control signal S then _cLogic level still be maintained " 0 ".As control signal S _cLogic level when being " 0 ", expression the first, the 3rd clock signal clk ₁, CLK ₃Than the same phase relation of convergence, therefore, multiplexer 408 can be selected output inversion signal CLK ₃_ B.By on can know, select output inversion signal CLK at multiplexer 408 ₃Under the situation of _ B, because the running of inverter 410 is equivalent to the delay that applies the 180 degree phase deviations of a correspondence, so retardation T _dThis moment, maximum only can a corresponding phase difference (180-PB), so, at control signal S _cLogic level be under the mode of operation of " 0 ", retardation T _dJust have like limit:

$T_d\≤\frac{T\·(V_{\mathrm{Dd}}-V_{\mathrm{TH}\_01})}{2V_{\mathrm{Dd}}}$ Formula (2)

In sum, for delay circuit 412 of the present invention, retardation T _dSetting must meet following formula:

$T_d\≤\mathrm{Min}\{\frac{T\·V_{\mathrm{TH}\_10}}{2V_{\mathrm{Dd}}},\frac{T\·(V_{\mathrm{Dd}}-V_{\mathrm{TH}\_01})}{2V_{\mathrm{Dd}}}\}$ Formula (3)

In formula (3), min{} gets minimum operation.

See also Fig. 8, Fig. 8 is the flow chart of an embodiment of data latching method of the present invention.Data latching method of the present invention is to be implemented by above-mentioned data-latching circuit 300, and its running is summarized as follows.Note that defined step execution sequence only is for the ease of explanation in the flow chart shown in Figure 8, is not to be restrictive condition of the present invention, and for example, under the prerequisite that obtains identical result, its execution order can carried out or exchange to some step synchronously.

Step 800: phase relation and the 3rd clock signal according to the first, the 3rd clock signal produce the second clock signal;

Step 802: carry out the phase place fine setting? If then carry out step 804; Otherwise, carry out step 806;

Step 804: apply a retardation and give the second clock signal and adjust its phase place, then execution in step 806;

Step 806: use first clock signal to trigger first data latch unit and with input data latching that its data input pin received at its data output end;

Step 808: use second clock signal triggering second data latch unit and with input data latching that its data input pin received at its data output end; And

Step 810: use the 3rd clock signal to trigger the 3rd data latch unit and with input data latching that its data input pin received at its data output end.

In above-mentioned steps, first, second, third clock signal is corresponding above-mentioned CLK respectively ₁, CLK ₂, CLK ₃, first, second, third data latch unit is then distinguished corresponding above-mentioned trigger 302,304,306.Note that because the running of data-latching circuit 300 is detailed as above, so its performed corresponding data latching method gets the running of thin portion and does not just give unnecessary details in addition.

Data-latching circuit of the present invention has many different application categories in the application of reality, with data-latching circuit 300, the first clock CLK of first embodiment ₁With the 3rd clock CLK ₃Can be produced or different clock generators produces by same clock generator, perhaps in this data-latching circuit 300, trigger 302 is arranged in the analog circuit; 304,306 on trigger is arranged in the digital circuit, and opposite, trigger 302 also can be arranged in the digital circuit; Then 304,306 on trigger is arranged in the analog circuit, and in addition, data-latching circuit 300 also possibly be arranged on the different chips; For example; Trigger 302 is the outputs that are set at a chip, and trigger 304,306 and phase selector 308 then are set at the input of another chip, when trigger 302 outputting data signals; 304 a certain pin positions (Pin) that see through chip of trigger receive this data-signal, accomplish latching of data.

The above is merely preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims (15)

1. A data latch circuit, comprising: The first data latch unit is used to latch a first input data according to a first clock signal, and output a first output data; The second data latch unit is used to latch the first output data according to a second clock signal, and output a second output data; and a phase selector, coupled to the second data latch unit, for generating the second clock signal to the second data latch unit according to the phase relationship between the first clock signal and a third clock signal; where the phase selector contains a phase detector, coupled to the first and third clock signals, for detecting the phase relationship between the first and third clock signals to generate a detection signal; an inverter, coupled to the third clock signal, for generating an inverted signal of the third clock signal according to the third clock signal; a filter, coupled to the phase detector, for filtering the detection signal to generate a filtered signal; a hysteresis buffer, coupled to the filter, for converting the filtered signal into a control signal according to a hysteresis characteristic, and outputting the control signal; and a selection unit, coupled to the inverter, the third clock signal and the hysteresis buffer, for selectively outputting the third clock signal or an inverted signal of the third clock signal as the third clock signal according to the control signal Second clock signal. 2. The data latch circuit as claimed in claim 1, wherein the phase detector is an XOR logic gate for performing an XOR logic operation on the first and third clock signals to generate the detection signal. 3. The data latch circuit as claimed in claim 1, wherein the hysteresis buffer is a Schmitt trigger. 4. A data latch circuit, comprising: The first data latch unit is used to latch a first input data according to a first clock signal, and output a first output data; The second data latch unit is used to latch the first output data according to a second clock signal, and output a second output data; The third data latch unit is used to latch the second output data according to a third clock signal, and output an output data; and A phase selector, coupled to the second data latch unit, is used to generate the second clock signal to the second data latch unit according to the phase relationship between the first clock signal and a third clock signal: Wherein, the first clock signal and the third clock signal are respectively generated by different clock generators; where the phase selector contains a phase detector, coupled to the first and third clock signals, for detecting the phase relationship between the first and third clock signals to generate a detection signal; a phase adjustment unit, coupled to the third clock signal, for generating a fourth clock signal according to the third clock signal, wherein there is a phase difference between the fourth clock signal and the third clock signal; a filter, coupled to the phase detector, for filtering the detection signal to generate a filtered signal; a hysteresis buffer, coupled to the filter, for converting the filtered signal into a control signal according to a hysteresis characteristic, and outputting the control signal; and a selection unit, coupled to the phase adjustment unit, the third clock signal and the hysteresis buffer, for selectively outputting the third clock signal or the fourth clock signal as the second clock according to the control signal Signal. 5. The data latch circuit as claimed in claim 4, wherein the first, second and third data latch units are flip-flops. 6. The data latch circuit according to claim 4, wherein the data output terminal of the first data latch unit is connected in series with the data input terminal of the second data latch unit, and the second data latch unit The data output terminal of the unit is connected in series with the data input terminal of the third data latch unit. 7. The data latch circuit as claimed in claim 4, wherein the phase detector is an XOR logic gate for performing an XOR logic operation on the first and third clock signals to generate the detection signal. 8. The data latch circuit as claimed in claim 4, wherein the phase selector further comprises: The delay unit, coupled to the selection unit, is used to add a delay to the output of the selection unit. 9. The data latch circuit as claimed in claim 4, wherein the phase adjustment unit is an inverter, and the inverter is used to receive the third clock signal to output the fourth clock signal, wherein the There is substantially a 180° phase difference between the fourth clock signal and the third clock signal. 10. The data latch circuit as claimed in claim 4, wherein the hysteresis buffer is a Schmitt trigger. 11. The data latch circuit as claimed in claim 4, wherein the first data latch unit is provided in a digital circuit, and the second data latch unit is provided in an analog circuit. 12. The data latch circuit as claimed in claim 4, wherein the first data latch unit is provided in an analog circuit, and the second data latch unit is provided in a digital circuit. 13. A data latch circuit for latching an input data, comprising: The first data latch unit is used to latch the input data according to a clock signal A, and output a first output data; The second data latch unit is used to latch the first output data according to a second clock signal, and output an output data; and A phase selector, coupled to the first data latch unit, is used to generate the clock signal A to the first data latch unit according to the phase relationship between a first clock signal and the second clock signal: Wherein, the first clock signal and the second clock signal are generated by different clock generators; Among them, the phase selector contains: a phase detector, coupled to the first and second clock signals, for detecting the phase relationship between the first and second clock signals to generate a detection signal; a phase adjustment unit, coupled to the second clock signal, for generating a third clock signal according to the second clock signal, wherein there is a phase difference between the third clock signal and the second clock signal; a filter, coupled to the phase detector, for filtering the detection signal to generate a filtered signal; a hysteresis buffer, coupled to the filter, for converting the filtered signal into a control signal according to a hysteresis characteristic, and outputting the control signal; and The selection unit is coupled to the phase adjustment unit and the hysteresis buffer, and is used for selectively outputting the second clock signal or the third clock signal as the clock signal A according to the control signal. 14. The data latch circuit as claimed in claim 13, wherein the phase adjustment unit is an inverter, and the inverter is used to receive the second clock signal to output the third clock signal, wherein the There is substantially a 180° phase difference between the second clock signal and the third clock signal. 15. The data latch circuit as claimed in claim 13, wherein the input data is input through a pin of a chip.

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