CN101520998B - Liquid crystal display capable of improving image flicker and related driving method - Google Patents

Abstract

The invention provides a liquid crystal display capable of improving flicker of pictures and a related driving method. The method adjusts the chamfering amplitude of the grid driving signal to reduce the picture flicker, and comprises the steps of respectively providing a first grid driving signal and a second grid driving signal according to parasitic capacitance values of a first pixel and a second pixel. The first gate driving signal includes a waveform falling edge from a high potential to a first potential, and the second gate driving signal includes a waveform falling edge from a high potential to a second potential. When the parasitic capacitance value of the first pixel is larger than that of the second pixel, the first potential is lower than the second potential; when the parasitic capacitance value of the first pixel is substantially equal to the parasitic capacitance value of the second pixel, the first potential is substantially equal to the second potential; when the parasitic capacitance value of the first pixel is smaller than that of the second pixel, the first potential is higher than the second potential. The invention can effectively eliminate the situation of picture flicker by adjusting the common voltage and improve the display quality.

Description

Liquid crystal display capable of improving screen flicker and related driving method

technical field

The invention relates to a liquid crystal display and a related driving method, in particular to a liquid crystal display capable of improving screen flicker and a related driving method.

Background technique

Liquid crystal display (liquid crystal display, LCD) has the advantages of low radiation, small size and low energy consumption, and has gradually replaced the traditional cathode ray tube display (cathode ray tube display, CRT), so it is widely used in notebook computers, personal Information products such as digital assistants (personal digital assistant, PDA), flat-screen TVs, or mobile phones. The driving method of the traditional liquid crystal display is to use the source driver circuit (source driver) and the gate driver circuit (gate driver) to drive the pixels on the panel to display images. Since the cost of the source driver circuit is higher than that of the gate driver circuit, in order to To reduce the usage of the source driving circuit, a half source driving circuit (half source driver, HSD) driving method in which the pixels share the data line structure is derived. In other words, for the same number of pixels, the data lines of the source driving circuit are halved, and the gate lines of the gate driving circuit are doubled, so that the production cost can be reduced.

Please refer to FIG. 1 , which is a schematic diagram of a liquid crystal display device 100 using an HSD driving structure in the prior art. The liquid crystal display device 100 includes a timing control circuit 130, a source driving circuit 110, a gate driving circuit 120, a plurality of data lines DL ₁ -DL _m , a plurality of gate lines GL ₁ -GL _n , and a pixel matrix . The pixel matrix includes a plurality of pixel units PX _L and PX _R , each pixel unit includes a thin film transistor (thin film transistor, TFT) switch TFT, a liquid crystal capacitor C _LC and a storage capacitor C _ST , respectively coupled to the corresponding The data lines, the corresponding gate lines, and a common voltage. The timing control circuit 130 can generate control signals YOE, YV1C, input clock pulse signals CK, CKB or output enable signal OE, etc. required for the operation of the source driver circuit 110 and the gate driver circuit 120 . The source driving circuit 110 can generate data driving signals SD ₁ -SD _m corresponding to display images. If the gate drive circuit 120 is an external drive circuit, it will generate the gate drive signals SG ₁ -SG _n required to turn on the transistor switches according to the control signals YOE and YV1C; on array (GOA) technology, the gate drive signals SG ₁ -SG _n needed to turn on the transistor switches are generated according to the input clock pulse signals CK, CKB and the output enable signal OE.

When the thin film transistor TFT is turned off, the pixel electrode is not connected to any voltage source, but is in a floating state. At this time, if there is any voltage change around the pixel electrode, it will be coupled to the pixel electrode through its parasitic capacitance. And change its voltage, so that the voltage applied to the liquid crystal capacitor C _LC and the storage capacitor C _ST will deviate from the original set value. This kind of voltage variation caused by parasitic capacitance is called feed-through voltage, and its value V _FD can be expressed as:

V _FD ＝[C _GD /(C _LC +C _ST +C _GD )]*ΔV _G

=K*ΔV _G

Among them, C _GD represents the parasitic capacitance between the gate and the drain of the thin film transistor switch TFT, K represents the ratio of C _GD to the total capacitance, and ΔV _G represents the gate drive signal when the thin film transistor switch TFT is turned off. The voltage drop caused by its gate. The feed-through voltage V _FD will cause image flicker. Since the thin film transistor switch TFT inevitably has parasitic capacitance, the general driving method will try to reduce the value of ΔV _G , and at the same time adjust the common voltage Vcom of the common terminal. Compensation, so as to effectively reduce screen flicker.

Please refer to FIG. 2 and FIG. 3 . FIG. 2 and FIG. 3 are schematic diagrams of a driving method of the liquid crystal display device 100 in the prior art. FIG. 2 shows the waveforms of the control signal YOE and gate drive signals SG ₁ to SG ₄ when the gate drive circuit 120 is an external drive circuit; FIG. 3 shows the clock Waveforms of the pulse signals CK, CKB, CK and CKB, the output enable signal OE, and the gate driving signals SG ₁ -SG ₄ .

In the driving method shown in FIG. 2 , the length of the enable period in the gate driving signals SG ₁ to SG ₄ is determined by the pulse width of the control signal YOE, and the gate driving signals SG ₁ to SG ₄ when their waveforms fall The time length is determined by the start time point of the control signal YOE and YV1C waveform falling. The time length of the control signal YOE having a high potential in each cycle is fixed, and the start time point of the control signal YV1C waveform falling in each cycle is the same. Therefore, when the corresponding thin film transistor switch TFT is turned off, the voltage difference caused by the gate driving signals SG ₁ -SG ₄ at the gates thereof is ΔV _G ′. As mentioned above, the value of the feedthrough voltage is proportional to the gate voltage difference. Since the ΔV _G ′ after the voltage shaving is smaller than the ΔV _G without the voltage shaving, the effect of the feedthrough voltage can be reduced.

In the driving method shown in FIG. 3 , the clock pulse signals CK and CKB have opposite phases and switch between high and low potentials with a predetermined cycle, and the predetermined cycle determines the enabling cycle of the gate drive signals SG ₁ -SG ₄ length. When the output enable signal OE has a high potential, the gate drive circuit 120 will output clock pulse signals CK and CKB to provide corresponding clock pulse signals O_CK and O_CKB; when the output enable signal OE has a low potential, the gate drive The circuit 120 stops outputting. At this time, charge sharing will be performed between the clock pulse signals O_CK and O_CKB, thereby achieving the effect of chamfering at the falling edge of the waveform, and then providing gate driving signals SG ₁ -SG according to the clock pulse signals O_CK and O_CKB ₄ . Since the output enable signal OE has a low potential for a period of time T in each cycle, the gate driving signals SG ₁ -SG ₄ will have the same clipping amplitude. Therefore, when the corresponding thin film transistor switch TFT is turned off, the voltage difference caused by the gate driving signals SG ₁ -SG ₄ at the gates thereof is ΔV _G ′. As mentioned above, the value of the feedthrough voltage is proportional to the gate voltage difference. Since the ΔV _G ′ after the voltage shaving is smaller than the ΔV _G without the voltage shaving, the effect of the feedthrough voltage can be reduced.

In the prior art liquid crystal display device 100, pixels are arranged on both sides of each data line, wherein the pixel unit PX _L is arranged on the left side of the data line and the gate driving signal SG ₁ transmitted from an odd number of gate lines _{, SG 3 , .} SG _n to control. The two types of pixel units PX _L and PX _R usually have different designs, and the values of C _LC , C _ST , C _GS or C _GD will also be different, thus generating different feedthrough voltages V _FD . Even if the two types of pixel units PX _L and PX _R have the same design, it is easy to cause different performances due to process deviation (for example, the deviation of the first metal layer Metal 1 and the second metal layer Metal 2 will cause the pixel units PX L and PX _R PX _R has different C _GD ), still will produce different feedthrough voltage V _FD .

In the prior art driving method shown in Fig. 2 and Fig. 3, the gate cross-voltage is reduced by the same magnitude, although the effect of the feed-through voltage can be reduced, but the feed-through voltage of each pixel unit will still be different, so it cannot be effectively By adjusting the common voltage Vcom to eliminate the screen flickering situation.

Contents of the invention

The object of the present invention is to provide a liquid crystal display capable of improving screen flicker and a related driving method, so as to overcome the defects of the prior art.

The present invention provides a liquid crystal display capable of improving screen flicker, comprising a first gate line for transmitting a first gate drive signal; a second gate line adjacent to and parallel to the first gate line , used to transmit a second gate drive signal; a data line, perpendicular to the first and second gate lines, used to transmit a data drive signal; a first pixel, arranged on the data line and the first The intersection of the gate line and the first side of the data line are used to display the picture according to the first gate driving signal and the received data driving signal; a second pixel is arranged on the data line and the data line The intersection of the second gate line and located on the second side of the data line is used to display a picture according to the second gate driving signal and the received data driving signal; a chamfering circuit is used according to the said second gate driving signal. The parasitic capacitance values of the first and second pixels are used to generate a clipping signal; and a gate circuit is used to adjust the characteristics of a gate pulse signal at the falling edge of the waveform according to the clipping signal to generate the first and second pixels. Two gate drive signals, wherein the first gate drive signal includes a falling edge of a waveform falling from a high potential to a first potential, and the second gate drive signal includes a wave falling from the high potential to a second potential Waveform falling edge.

The present invention also provides a method for driving a liquid crystal display, the liquid crystal display comprising a data line, two adjacent first and second gate lines, a set at the intersection of the data line and the first gate line and a first pixel on a first side of the data line, and a second pixel on a second side of the data line at the intersection of the data line and the second gate line, the method comprising providing a gate Pole pulse signal; adjust the gate pulse signal according to the parasitic capacitance value of the first pixel to generate a first gate drive signal, wherein the first gate drive signal includes a voltage that drops from a high potential to a first potential The falling edge of the waveform; adjusting the gate pulse signal according to the parasitic capacitance value of the second pixel to generate a second gate driving signal, wherein the second gate driving signal includes falling from the high potential to a second potential a falling edge of the waveform; and outputting the first and second gate driving signals to the first and second gate lines respectively to drive the first and second pixels.

According to the capacitance ratio values K ₁ -K _n of the pixel units, the present invention can flexibly adjust the time length or the falling slope of the waveforms of the gate driving signals G ₁ -G _n when the waveforms fall. Different parasitic capacitance values are compensated by different voltage differences ΔV _G1 ~ ΔV _Gn , so that the feed-through voltage of each type of pixel unit has the same value, so the flickering of the screen can be effectively eliminated by adjusting the common voltage Vcom, and the display quality can be improved. .

Description of drawings

FIG. 1 is a schematic diagram of a liquid crystal display device using an HSD driving structure in the prior art.

2 and 3 are schematic diagrams of a driving method of a liquid crystal display device in the prior art.

4 and 5 are schematic diagrams of a liquid crystal display device adopting an HSD driving structure in the present invention.

FIG. 6 is a schematic diagram of a method for driving a liquid crystal display device in the first embodiment of the present invention.

FIG. 7 is a schematic diagram of a chamfering circuit capable of implementing the driving method according to the first embodiment of the present invention.

FIG. 8 is a schematic diagram of a method for driving a liquid crystal display device in the second embodiment of the present invention.

FIG. 9 is a schematic diagram of a chamfering circuit that can realize the driving method according to the second embodiment of the present invention.

FIG. 10 is a schematic diagram of a chamfering circuit capable of implementing the driving method according to the third embodiment of the present invention.

Wherein, the reference signs are explained as follows:

R1 resistor 74, 94 slope adjustment circuit

R2 variable resistor 110, 210 source drive circuit

C _LC liquid crystal capacitor 130, 230 timing control circuit

C _ST storage capacitor QP, QN transistor switch

70 Transformer S1, S2 switch

72 potential converter DL ₁ ~ DL _m data line

240 chamfering circuit GL ₁ ~ GL _n gate line

TFT thin film transistor switch 120, 220 gate drive circuit

100, 200, 300 liquid crystal display device

PX _L , PX _R , PX _LU , PX _LB , PX _RU , PX _RB pixel units

YOE, YV1C, CK, CKB, O_CK,

O_CKB, OE, OE _TRIM , V _TRIM ,

SD ₁ ～SD _m , SG ₁ ～SG _n signals

Detailed ways

Please refer to FIG. 4 and FIG. 5 . FIG. 4 and FIG. 5 are schematic diagrams of liquid crystal display devices 200 and 300 respectively adopting the HSD driving structure in the present invention. The liquid crystal display devices 200 and 300 each include a source drive circuit 210, a gate drive circuit 220, a timing control circuit 230, a chamfering circuit 240, a plurality of data lines DL ₁ -DL _m , and a plurality of gate lines GL ₁ ˜GL _n , and a pixel matrix. The pixel matrix of the liquid crystal display device 200 includes a plurality of pixel units PX _L and PX _R , the pixel matrix of the liquid crystal display device 300 includes a plurality of pixel units PX _LU , PX _LB , PX _RU and PX _RB , and each pixel unit includes a thin film The transistor switch TFT, a liquid crystal capacitor C _LC and a storage capacitor C _ST are respectively coupled to a corresponding data line, a corresponding gate line, and a common terminal. The timing control circuit 230 can generate control signals YOE, YV1C, clock pulse signals CK, CKB or an output enable signal OE and the like required for the operation of the source driver circuit 210 and the gate driver circuit 220 . The source driving circuit 210 can generate data driving signals SD ₁ -SD _m corresponding to display images. If the gate driving circuit 220 is an external driving circuit, the trimming circuit 240 will generate a trimming signal V _TRIM according to the control signal YV1C and the parasitic capacitance value of the pixel unit, and the gate driving circuit 220 will then generate a trimming signal V TRIM according to the control signal YOE and the trimming signal V _TRIM is used to generate the gate drive signals SG ₁ -SG _n required to turn on the transistor switches; if the gate drive circuit 220 is manufactured using GOA technology, the chamfering circuit 240 will be based on the output enable signal OE and the parasitic capacitance of the pixel unit value to generate a trimming signal OE _TRIM , and the gate driving circuit 220 generates gate driving signals SG ₁ -SG _n required to turn on the transistor switches according to the clock pulse signals CK, CKB and the trimming signal OE _TRIM .

In the liquid crystal display device 200 of the present invention, different types of pixel units are arranged on both sides of each data line, wherein the first type of pixel unit PX _L is arranged on the left side of the data line and transmitted by an odd number of gate lines. The gate drive signals SG ₁ , SG ₃ , ..., SG _n-1 are controlled by the gate drive signals SG 1 , SG 3 , ..., SG n-1, and the second type of pixel unit PX _R is set on the right side of the data line and is driven by the gate drive signal from the even number of gate lines. Signals SG ₂ , SG ₄ , . . . , SG _n are used to control (assuming n is an even number). These two types of pixel units PX _L and PX _R usually have different designs, and the values of C _LC , C _ST , C _GS or C _GD will also be different, thus generating different magnitudes of the feed-through voltage V _FD . Even if the two types of pixel units PX _L and PX _R have the same design, it is easy to cause different magnitudes of the feedthrough voltage V _FD due to process deviation.

In the liquid crystal display device 300 of the present invention, different types of pixel units are respectively arranged on both sides of each data line, wherein the first type of pixel unit PX _LU is arranged on the left side of the data line and connected by the gate lines GL ₁ , GL ₅ , ..., GL _n-3 to control the gate driving signals SG ₁ , SG ₅ , ..., SG _n-3 , the second type of pixel unit PX _RB is set on the right side of the data line and is controlled by Controlled by the gate drive signals SG ₂ , SG ₆ , ..., SG _n-2 from the gate lines GL ₂ , GL ₆ , ..., GL _n-2 , the third type of pixel unit PX _RU is set on the right side of the data line and controlled by the gate driving signals SG ₃ , SG ₇ , ..., SG _n-1 transmitted from the gate lines GL ₃ , GL ₇ , ..., GL _n-1 , and the first The four types of pixel units PX _LB are arranged on the left side of the data lines and are driven by gate driving signals SG ₄ , SG ₈ , ..., SG _n from the gate lines GL ₄ , GL ₈ , ..., GL _n Control (assuming n is a multiple of 4). These four types of pixel units PX _LU , PX _LB , PX _RU and PX _RB usually have different designs, and the values of C _LC , C _ST , C _GS or C _GD will also be different, thus resulting in different sizes of feedthrough voltage V _FD . Even if the four types of pixel units PX _LU , PX _LB , PX _RU and PX _RB have the same design, it is easy to cause different magnitudes of the feedthrough voltage V _FD due to process deviation.

The present invention uses the gate drive signals SG ₁ -SG _n with the falling edges of the chamfered waveforms to reduce the gate voltage difference, and at the same time changes the waveforms of the gate drive signals SG ₁ -SG _n according to the parasitic capacitance values of different types of pixel units. The cutting angle of the falling edge is such that when the corresponding thin film transistor switch TFT is turned off, the gate driving signals SG ₁ -SG _n can cause different voltage differences ΔV _G1 -ΔV _Gn at the gates. Taking the liquid crystal display device 300 as an example, the present invention uses the gate driving signals SG ₁ -SG ₄ with different amplitudes of chamfering at the falling edge of the waveform to drive four types of pixel units, so that different transistors can be caused when the corresponding transistor switches are turned off. The gate voltage difference ΔV _G1 ～ΔV _G4 is large or small to compensate for the influence of the different capacitance ratio values K ₁ ～K ₄ of the four types of pixel units on the feed-through voltage, so that the feed-through voltage V _FD1 of the four types of pixel units ~V _FD4 is about the same, so the screen flicker can be effectively reduced by adjusting the common voltage Vcom.

Please refer to FIG. 6 . FIG. 6 is a driving method of a liquid crystal display device in the first embodiment of the present invention, which can be used to drive the liquid crystal display device 200 or 300 when the source driving circuit 310 is an external driving circuit. FIG. 4 shows the waveforms of the control signals YOE, YV1C, the trimming signal V _TRIM and the gate driving signals SG ₁ -SG ₄ . In the driving method shown in FIG. 6 , the control signal YOE has a high potential for a fixed period of time in each cycle, and its pulse width determines the length of the enabling cycle of the gate driving signals SG ₁ -SG ₄ . The starting time point of the waveform drop of the control signal YV1C in each cycle is different according to the parasitic capacitance value of the pixel unit, and the total time length T1~T4 of the waveform drop of the gate driving signals SG ₁ ~ SG ₄ is determined by The control signal YOE and YV1C are determined by the start time point of their waveform falling within the corresponding period. The trimming circuit 340 firstly generates the trimming signal V _TRIM with different falling time points of the waveforms in the corresponding period according to the control signal YV1C and the capacitance proportional values K ₁ -K ₄ . The gate driving circuit 320 then generates gate driving signals SG ₁ -SG ₄ with different trimming amplitudes according to the control signal YOE and the trimming signal V _TRIM , which respectively cause the gates to Extreme pressure difference ΔV _G1 ~ ΔV _G4 . Assuming that the magnitude relationship of the proportional value of the parasitic capacitance is K ₁ <K ₂ <K ₃ <K ₄ , the total time length of the gate drive signal waveform falling has a magnitude relationship of T1<T2<T3<T4, so the gate voltage difference The size relationship is ΔV _G1 >ΔV _G2 >ΔV _G3 >ΔV _G4 . As mentioned above, the value of the feedthrough voltage is proportional to the product of the capacitance ratio value of the pixel unit and the gate voltage difference. In the case of K ₁ <K ₂ <K ₃ <K ₄ , the gate of the first embodiment of the present invention The polar drive signals SG ₁ ~ SG ₄ provide a voltage difference with a relationship of ΔV _G1 > ΔV _G2 > ΔV _G3 > ΔV _G4 , so that the feed-through voltage of each type of pixel unit has the same value, so the common voltage can be adjusted effectively Vcom to eliminate screen flickering.

Please refer to FIG. 7 , which is a schematic diagram illustrating a chamfering circuit 340 that can implement the driving method of the first embodiment of the present invention. The trimming circuit 340 of FIG. 7 includes an inverter 70, a level shifter 72, a slope adjustment circuit 74, and transistor switches QP and QN, which can generate the trimming signal V _TRIM according to the control signal YV1C . When the control signal YV1C has a high potential, the transistor switch QP is turned on and the transistor switch QN is turned off, at this time the trimming signal V _TRIM has a high potential VGH; when the control signal YV1C has a low potential, the transistor switch QP is turned off and the transistor switch QN is turned off. The switch QN is turned on, and at this moment, the potential of the trimming signal V _TRIM will be pulled to a low potential by the resistor R1 in the slope adjustment circuit 74 . Therefore, in the embodiments shown in FIG. 6 and FIG. 7 , the angle-cutting circuit 340 receives the control signal YV1C with different waveform falling start time points, and then provides the angle-cutting signal V with a slope on the falling edge of the waveform through the slope adjustment circuit 74. _TRIM , wherein the slope adjustment circuit 74 can be an impedance element, such as a resistor or a variable resistor.

Please refer to FIG. 8 . FIG. 8 is a driving method of a liquid crystal display device in a second embodiment of the present invention, which can be used to drive the liquid crystal display device 200 or 300 when the source driving circuit 310 is an external driving circuit. FIG. 6 shows the waveforms of the control signals YOE, YV1C, the trimming signal V _TRIM and the gate driving signals SG ₁ -SG ₄ . In the driving method shown in FIG. 8 , the time length of the high potential of the control signal YOE in each period is fixed, and the pulse width thereof determines the length of the enabling period of the gate driving signals SG ₁ -SG ₄ . The waveforms of the control signal YV1C start at the same time, so the waveforms of the gate drive signals SG ₁ to SG ₄ have a falling time length of T, and the waveforms of the gate drive signals SG ₁ to SG ₄ have a slope of m ₁ to m ₄ Then it is controlled by chamfering circuit 340 . The clipping circuit 340 first generates clipping signals V _TRIM with different falling slopes according to the control signal YV1C and the capacitance ratios K ₁ -K ₄ . The gate driving circuit 320 then generates gate driving signals SG ₁ -SG ₄ with different trimming amplitudes according to the control signal YOE and the trimming signal V _TRIM , which respectively cause the gates to Extreme pressure difference ΔV _G1 ~ ΔV _G4 . Assuming that the magnitude relationship of the parasitic capacitance value is K ₁ <K ₂ <K ₃ <K ₄ , the magnitude relationship of the falling slope of the gate drive signal waveform is m ₁ <m ₂ <m ₃ <m ₄ , so the gate voltage drop The size relationship is ΔV _G1 >ΔV _G2 >ΔV _G3 >ΔV _G4 . As mentioned above, the value of the feedthrough voltage is proportional to the product of the parasitic capacitance of the pixel unit and the gate voltage difference. In the case of K ₁ <K ₂ <K ₃ <K ₄ , the gate of the second embodiment of the present invention The driving signals SG ₁ ~ SG ₄ provide a voltage difference with a relationship of ΔV _G1 > ΔV _G2 > ΔV _G3 > ΔV _G4 , so that the feedthrough voltage of each type of pixel unit has the same value, so it can effectively adjust the common voltage Vcom to eliminate screen flickering.

Please refer to FIG. 9 , a schematic diagram of FIG. 9 illustrates a chamfering circuit 340 capable of implementing the driving method according to the second embodiment of the present invention. The trimming circuit 340 in FIG. 9 includes a transformer 70 , a voltage converter 72 , a slope adjustment circuit 94 , and transistor switches QP and QN, and can generate a trimming signal V _TRIM according to a control signal YV1C. When the control signal YV1C has a high potential, the transistor switch QP is turned on and the transistor switch QN is turned off, at this time the trimming signal V _TRIM has a high potential VGH; when the control signal YV1C has a low potential, the transistor switch QP is turned off and the transistor switch QN is turned off. The switch QN is turned on, and at this moment, the potential of the trimming signal V _TRIM will be pulled to a low potential by the slope adjustment circuit 94 . The slope adjustment circuit 94 includes a resistor R1, a variable resistor R2, and switches S1 and S2, so that different equivalent resistances can be provided according to the parasitic capacitance values K ₁ -K ₄ , so that the slope adjustment circuit 94 can pull The potential of the low clipping signal V _TRIM . Therefore, in the embodiment of FIG. 8 and FIG. 9, the trimming circuit 340 receives the control signal YV1C having the same waveform falling start time point, and then provides the trimming signal V _TRIM with different slopes on the falling edge of the waveform through the slope adjustment circuit 94. .

Please refer to FIG. 10 . FIG. 10 is a driving method of a liquid crystal display device in a third embodiment of the present invention, which can be used to drive the liquid crystal display device 200 or 300 when the source driving circuit 310 is manufactured by GOA technology. FIG. 10 shows the waveforms of the clock pulse signals CK, CKB, O_CK and O_CKB, the output enable signal OE, and the gate driving signals SG ₁ -SG ₄ . In the driving method shown in FIG. 8 , the clock pulse signals CK and CKB generated by the timing control circuit 230 have opposite phases, and switch between high and low potentials with a predetermined period, and the predetermined period determines the gate drive signal _SG1 ~Length of the enabled cycle within SG ₄ . The trimming circuit 340 first generates trimming signals OE _TRIM with different disable time (with low potential) lengths T1 - T4 according to the output enable signal OE and the parasitic capacitances K ₁ -K ₄ . When the trimming signal OE _TRIM has a high potential, the gate driving circuit 220 will output clock pulse signals CK and CKB to provide corresponding clock pulse signals O_CK and O_CKB; when the trimming signal OE _TRIM has a low potential, the gate drive The circuit 220 stops outputting, and at this time, charge sharing will be performed between the clock pulse signals O_CK and O_CKB, thereby achieving the effect of cutting corners at the falling edge of the waveform. The gate drive circuit 320 then generates gate drive signals SG ₁ -SG ₄ with different chamfering amplitudes according to the clock pulse signals O_CK and O_CKB, which cause gate Extreme pressure difference ΔV _G1 ~ ΔV _G4 . Assuming that the ratio of the parasitic capacitance C _GD to the total capacitance value is K ₁ <K ₂ <K ₃ <K ₄ , then the relationship of the deactivation time of the trimming signal OE _TRIM is T1<T2<T3<T4, so the gate Extreme pressure difference ΔV _G1 >ΔV _G2 >ΔV _G3 >ΔV _G4 . As mentioned above, the value of the feedthrough voltage is proportional to the product of the parasitic capacitance of the pixel unit and the gate voltage difference. In the case of K ₁ <K ₂ <K ₃ <K ₄ , the gate of the third embodiment of the present invention The driving signals SG ₁ ~ SG ₄ provide a voltage difference with a relationship of ΔV _G1 > ΔV _G2 > ΔV _G3 > ΔV _G4 , so that the feed-through voltage of each type of pixel unit has the same value, so the common voltage Vcom can be adjusted effectively to eliminate screen flickering.

According to the capacitance ratio values K ₁ -K _n of the pixel units, the present invention can flexibly adjust the time length or the waveform falling slope of the gate driving signals G ₁ -G _n when the waveforms fall. Different parasitic capacitance values are compensated by different voltage differences ΔV _G1 ~ ΔV _Gn , so that the feed-through voltage of each type of pixel unit has the same value, so the flickering of the screen can be effectively eliminated by adjusting the common voltage Vcom, and the display quality can be improved. .

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the protection scope of the present invention.

Claims (20)

1. A liquid crystal display capable of improving picture flickering, comprising: a first gate line, used to transmit a first gate driving signal; a second gate line, adjacent to and parallel to the first gate line, for transmitting a second gate driving signal; a data line, perpendicular to the first and second gate lines, for transmitting data driving signals; A first pixel, located at the intersection of the data line and the first gate line and on the first side of the data line, is used for displaying according to the first gate driving signal and the received data driving signal screen; A second pixel, located at the intersection of the data line and the second gate line and on the second side of the data line, is used for displaying according to the second gate driving signal and the received data driving signal screen; a clipping circuit for generating a clipping signal according to the parasitic capacitance values of the first and second pixels; and A gate circuit, used to adjust the characteristics of a gate pulse signal at the falling edge of the waveform according to the chamfering signal to generate the first and second gate drive signals, wherein the first gate drive signal includes a high The potential drops to a waveform falling edge of a first potential, and the second gate drive signal includes a waveform falling edge falling from the high potential to a second potential, wherein, When the parasitic capacitance value of the first pixel is greater than the parasitic capacitance value of the second pixel, the first potential is lower than the second potential; When the parasitic capacitance value of the first pixel is substantially equal to the parasitic capacitance value of the second pixel, the first potential is substantially equal to the second potential; and When the parasitic capacitance of the first pixel is smaller than the parasitic capacitance of the second pixel, the first potential is higher than the second potential. 2. The liquid crystal display of claim 1, wherein: This first pixel contains: a first switch, comprising: a first end coupled to the data line; a second end; and a control terminal coupled to the first gate line; a first liquid crystal capacitor coupled between the second end of the first switch and a common end; and a first storage capacitor connected in parallel to the first liquid crystal capacitor; and This second pixel contains: a second switch, comprising: a first end coupled to the data line; a second end; and a control terminal coupled to the second gate line; a second liquid crystal capacitor coupled between the second end of the second switch and the common end; and A second storage capacitor is connected in parallel with the second liquid crystal capacitor. 3. The liquid crystal display as claimed in claim 2, wherein the first and second switches comprise thin film transistors, and the parasitic capacitance of the plurality of pixels is a gate-drain capacitance of the plurality of thin film transistors. 4. The liquid crystal display of claim 1, further comprising: a third gate line, adjacent to and parallel to the second gate line, for transmitting a third gate driving signal; a fourth gate line, adjacent to and parallel to the third gate line, for transmitting a fourth gate driving signal; A third pixel, located at the intersection of the data line and the third gate line and on the first side of the data line, is used for displaying according to the third gate driving signal and the received data driving signal screen; and A fourth pixel, located at the intersection of the data line and the fourth gate line and on the second side of the data line, is used for displaying according to the fourth gate driving signal and the received data driving signal screen; Wherein the corner-cutting circuit also generates the corner-cutting signal according to the parasitic capacitance values of the third and fourth pixels, and the gate circuit also adjusts the characteristics of the gate pulse signal at the falling edge of the waveform according to the corner-cutting signal to generate the third and fourth gate drive signals, wherein the third gate drive signal includes a waveform falling edge from the high potential to a third potential, and the fourth gate drive signal includes a drop from the high potential The potential drops to a falling edge of the waveform of the fourth potential. 5. The liquid crystal display of claim 4, wherein: This third pixel contains: a third switch, comprising: a first end coupled to the data line; a second end; and a control terminal coupled to the third gate line; a third liquid crystal capacitor coupled between the second end of the third switch and a common end; and a third storage capacitor connected in parallel to the third liquid crystal capacitor; and This fourth pixel contains: a fourth switch, comprising: a first end coupled to the data line; a second end; and a control terminal coupled to the fourth gate line; a fourth liquid crystal capacitor coupled between the second terminal of the fourth switch and the common terminal; and A fourth storage capacitor is connected in parallel with the fourth liquid crystal capacitor. 6. The liquid crystal display as claimed in claim 5, wherein the third and fourth switches comprise thin film transistors, and the parasitic capacitance of the plurality of pixels is a gate-drain capacitance of the plurality of thin film transistors. 7. The liquid crystal display of claim 1, further comprising: a third gate line, adjacent to and parallel to the second gate line, for transmitting a third gate driving signal; a fourth gate line, adjacent to and parallel to the third gate line, for transmitting a fourth gate driving signal; A third pixel, located at the intersection of the data line and the third gate line and on the second side of the data line, is used for displaying according to the third gate driving signal and the received data driving signal screen; and A fourth pixel, located at the intersection of the data line and the fourth gate line and on the first side of the data line, is used for displaying according to the fourth gate driving signal and the received data driving signal picture; Wherein the corner-cutting circuit also generates the corner-cutting signal according to the parasitic capacitance values of the third and fourth pixels, and the gate circuit also adjusts the characteristics of the gate pulse signal at the falling edge of the waveform according to the corner-cutting signal to generating the third and fourth gate drive signals, wherein the third gate drive signal includes a falling edge of the waveform from the high potential to a third potential, and the fourth gate drive signal includes a drop from the high potential Falling edge of the waveform down to a fourth potential. 8. The liquid crystal display of claim 7, wherein: This third pixel contains: a third switch, comprising: a first end coupled to the data line; a second end; and a control terminal coupled to the third gate line; a third liquid crystal capacitor coupled between the second end of the third switch and a common end; and a third storage capacitor connected in parallel to the third liquid crystal capacitor; and This fourth pixel contains: a fourth switch, comprising: a first end coupled to the data line; a second end; and a control terminal coupled to the fourth gate line; a fourth liquid crystal capacitor coupled between the second terminal of the fourth switch and the common terminal; and A fourth storage capacitor is connected in parallel with the fourth liquid crystal capacitor. 9. The liquid crystal display as claimed in claim 8, wherein the third and fourth switches comprise thin film transistors, and the parasitic capacitance of the plurality of pixels is a gate-drain capacitance of the plurality of thin film transistors. 10. The liquid crystal display as claimed in claim 1, wherein the chamfering circuit comprises: A switch is used to control the starting time point of the falling edge of the waveform of the clipping signal in different periods. 11. The liquid crystal display as claimed in claim 1, wherein the chamfering circuit comprises: A resistor is used to control the slope of the clipping signal when its waveform falls in different periods. 12. The liquid crystal display as claimed in claim 1, wherein the chamfering circuit and the gate circuit are manufactured by integrated circuit technology integrated into the panel. 13. The liquid crystal display of claim 1, further comprising: A timing control circuit is used to provide the gate pulse signal. 14. A method for driving a liquid crystal display, the liquid crystal display comprising a data line, two adjacent first and second gate lines, a line located at the intersection of the data line and the first gate line and located at the A first pixel on a first side of a data line, and a second pixel disposed at an intersection of the data line and the second gate line and on a second side of the data line, the method comprising: providing a gate pulse signal; adjusting the gate pulse signal according to the parasitic capacitance value of the first pixel to generate a first gate driving signal, wherein the first gate driving signal includes a falling edge of a waveform falling from a high potential to a first potential; adjusting the gate pulse signal according to the parasitic capacitance value of the second pixel to generate a second gate driving signal, wherein the second gate driving signal includes a falling edge of a waveform falling from the high potential to a second potential; and Outputting the first and second gate driving signals to the first and second gate lines to drive the first and second pixels, respectively, wherein, When the parasitic capacitance value of the first pixel is greater than the parasitic capacitance value of the second pixel, the first potential is lower than the second potential; When the parasitic capacitance value of the first pixel is substantially equal to the parasitic capacitance value of the second pixel, the first potential is substantially equal to the second potential; and When the parasitic capacitance of the first pixel is smaller than the parasitic capacitance of the second pixel, the first potential is higher than the second potential. 15. The method of claim 14, wherein: generating the first gate drive signal includes dropping the first gate drive signal from the high potential for a first time length to reach the first potential; and Generating the second gate driving signal includes dropping the second gate driving signal from the high potential for a second time length to reach the second potential. 16. The method of claim 15, wherein: When the parasitic capacitance value of the first pixel is greater than the parasitic capacitance value of the second pixel, the first time length is greater than the second time length; When the parasitic capacitance value of the first pixel is substantially equal to the parasitic capacitance value of the second pixel, the first duration of time is substantially equal to the second duration of time; and When the parasitic capacitance of the first pixel is smaller than the parasitic capacitance of the second pixel, the first time length is shorter than the second time length. 17. The method of claim 14, wherein: generating the first gate drive signal includes decreasing the first gate drive signal from the high potential with a first slope to reach the first potential; and Generating the second gate driving signal includes decreasing the second gate driving signal from the high potential with a second slope to reach the second potential. 18. The method of claim 17, wherein: When the parasitic capacitance value of the first pixel is greater than the parasitic capacitance value of the second pixel, the first slope is greater than the second slope; When the parasitic capacitance value of the first pixel is substantially equal to the parasitic capacitance value of the second pixel, the first slope is substantially equal to the second slope; and The first slope is smaller than the second slope when the parasitic capacitance of the first pixel is smaller than the parasitic capacitance of the second pixel. 19. The method of claim 14, further comprising: providing a first clock signal and a second clock signal, wherein the polarities of the first and second clock signals are inverted at a predetermined period, and at the same time the first and second clock signals have opposite polarity; determining a first time length according to the parasitic capacitance value of the first pixel; determining a second time length according to the parasitic capacitance of the second pixel; performing charge sharing on the first and second clock pulse signals during the first time length during a period corresponding to the first pixel; charge sharing the first and second clock signals for the second length of time during a period corresponding to the second pixel; and The gate pulse signal is adjusted according to the first or second clock pulse signal after charge sharing to generate the first or the second gate driving signal. 20. The method of claim 19, wherein: When the parasitic capacitance value of the first pixel is greater than the parasitic capacitance value of the second pixel, the first time length is greater than the second time length; When the parasitic capacitance value of the first pixel is substantially equal to the parasitic capacitance value of the second pixel, the first duration of time is substantially equal to the second duration of time; and When the parasitic capacitance of the first pixel is smaller than the parasitic capacitance of the second pixel, the first time length is shorter than the second time length.

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