CN101510774B - Mixing voltage output circuit - Google Patents
Mixing voltage output circuit Download PDFInfo
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- CN101510774B CN101510774B CN2009100213539A CN200910021353A CN101510774B CN 101510774 B CN101510774 B CN 101510774B CN 2009100213539 A CN2009100213539 A CN 2009100213539A CN 200910021353 A CN200910021353 A CN 200910021353A CN 101510774 B CN101510774 B CN 101510774B
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- 229910052760 oxygen Inorganic materials 0.000 claims description 20
- 239000001301 oxygen Substances 0.000 claims description 20
- 238000013519 translation Methods 0.000 abstract description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 16
- 238000010586 diagram Methods 0.000 description 5
- 230000010355 oscillation Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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Abstract
The invention discloses a hybrid voltage output circuit which comprises a predrive circuit, an output stage and a level translator between an output end of the predrive circuit and the output stage. The hybrid voltage output circuit is characterized in that the level translator comprises a 1V electrical level generating circuit and an electrical level translation circuit which uses a thin gate oxide MOS transistor withstanding the voltage of 3.3V and converts 0V-3.3V to 1.7V-5V. The output stage comprises a first PMOS transistor and a second PMOS transistor which are connected in series and a first NMOS transistor and a second NMOS transistor which are connected in series, wherein, the grid electrode of the first PMOS transistor is connected with the output end of the electrical level translation circuit converting 0V-3.3V to 1.7V-5V, and the grid electrode of the second PMOS transistor is connected with the output end of the 1V electrical level generating circuit; the grid electrode of the first NMOS transistor is connected with a first power supply and the source electrode of the first PMOS transistor is connected with a second power supply; the grid electrode of the second NMOS transistor is connected with another output end of the pre-drive circuit, and the drain electrode of the second PMOS transistor is connected with the drain electrode of the first NMOS transistor to form an output node.
Description
Technical field
The present invention relates to semiconductor integrated circuit, be specifically related to a kind of mixing voltage output circuit that is used for digital circuit with signal level translation function.
Background technology
Reducing of integrated circuit characteristic size is one of power that promotes the semi-conductor industry development, for the performance that improves integrated circuit with reduce its power consumption, when characteristic size reduced, the gate oxide thickness of MOS transistor and supply voltage all progressively reduced in the integrated circuit.But chip is in the plate level work environment of complexity, often need with the chip of making under the earlier generations process conditions compatible mutually (they use high power supply voltage and output HIGH voltage level signal), and the operation level of special interface standard does not reduce (as the PCI-X bus voltage) along with the minimizing of single chip power voltage.So when the chip internal supply voltage descended gradually, the supply voltage of chip output circuit often needed to keep particular value for the consideration of compatibility.Such as, for 0.35umCMOS technology, the chip internal supply voltage is generally 3.3V, and for compatibility specific interface standard and earlier generations handicraft product, the supply voltage of output circuit often will be 5V.
0.35um in the CMOS technology, transistor for the normal thin gate oxide thickness, the absolute value of its reliable grid source, drain-to-gate voltage is 3.3V ± 10%, under the 5V supply voltage, can produce the grid oxygen reliability problem in the output circuit that is made of normal thin gate oxide thickness transistor.In order to solve the grid oxygen reliability problem, industrial quarters is generally used thick grid oxygen transistor in output circuit, improve transistorized withstand voltage.Fig. 1 is the schematic diagram of this mixing voltage output circuit, VDD is 3.3V among the figure, VDDH is 5V, can not directly be carried in the grid of MP1 by the 0-3.3V level of predrive circuit output, because this will cause MP1 to turn-off, need level translator that the 0-3.3V level signal is converted to the 0-5V level signal, output circuit could operate as normal.But sort circuit has used thick grid oxygen transistor, and its threshold voltage is big, gate capacitance is little, thereby its current driving ability is descended.What is more important, the photolithography plate and the processing step that use thick grid oxygen transistor to add, this has not only increased chip cost, has also prolonged the production time of chip.
In order to overcome above-mentioned shortcoming, can design and only use the thin transistorized output circuit of grid oxygen, and, carry out circuit stages and reinforce at its grid oxygen reliability problem.For only using the thin transistorized 3.3V of grid oxygen, 5V mixing voltage output circuit, as shown in Figure 2, its problem that will overcome mainly contains following four:
(1) as among Fig. 2 shown in 01, when output voltage was 5V, the grid voltage of M1 was 0V, and the drain-gate voltage of M1 is 5V like this, has surpassed the reliable drain-gate voltage of thin grid oxygen nmos device;
(2) as among Fig. 2 shown in 02, when output voltage was 0V, the grid voltage of M2 was 5V, and the drain-to-gate voltage of M2 is 5V like this, has surpassed the reliable drain-to-gate voltage of thin grid oxygen PMOS device;
(3) as among Fig. 2 shown in 03, when output voltage was 5V, the grid voltage of M2 was 0, and the source gate voltage of M2 is 5V like this, has surpassed the reliable source gate voltage of thin grid oxygen PMOS device;
(4) as among Fig. 2 shown in 04, the output voltage of predrive circuit is up to 3.3V, and the grid that the voltage of 3.3V is added in M2 can't end M2 fully when circuit output low level signal.
Summary of the invention
The purpose of this invention is to provide a kind of novel 3.3V/5V mixing voltage output circuit, this circuit only uses withstand voltage thin grid oxygen MOS transistor as 3.3V, in the process of circuit working, without any the grid oxygen reliability problem.
For reaching above purpose, the present invention takes following technical scheme to be achieved:
A kind of mixing voltage output circuit, comprise predrive circuit, output stage, output of predrive circuit and the level translator between the output stage, it is characterized in that, described level translator comprises that a 1V level produces circuit, one is used the 0-3.3V of withstand voltage thin grid oxygen MOS transistor as 3.3V to become the 1.7V-5V level shifting circuit, described output stage comprises first of series connection, the 2nd PMOS transistor, first of series connection, second nmos pass transistor, the transistorized grid of the one PMOS connects the output of 0-3.3V to the 1.7V-5V level shifting circuit, and the transistorized grid of the 2nd PMOS connects the output that the 1V level produces circuit; The grid of first nmos pass transistor connects first power supply, the transistorized source electrode of the one PMOS connects second source, the grid of second nmos pass transistor connects another output of predrive circuit, and the 2nd PMOS transistor drain links to each other with first nmos transistor drain and constitutes output node.
In the such scheme, described 0-3.3V becomes the 1.7V-5V level shifting circuit and comprises: source electrode is connected in the 3rd, the 4th PMOS transistor of second source, the the 3rd, the 4th nmos pass transistor of series connection, the 5th, the 6th nmos pass transistor of series connection, the 3rd to the 7th diode of series connection; The grid of the grid of described the 4th nmos pass transistor, the 6th nmos pass transistor (205) is connected first power supply with the positive pole of the 7th diode; The grid of the 3rd nmos pass transistor connects the predrive circuit output and connects the grid of the 5th nmos pass transistor by inverter; The drain electrode of described the 4th nmos pass transistor is connected with the 3rd PMOS transistor drain, the transistorized grid of the 4th PMOS; The drain electrode of described the 6th nmos pass transistor is connected with the 4th PMOS transistor drain, the transistorized grid of the 3rd PMOS and exports the transistorized grid of a PMOS to; The source electrode of described the 3rd, the 5th nmos pass transistor is connected with the tie point of the 3rd, the 4th diode after linking to each other again; The negative pole of described the 3rd diode produces circuit by the 1V level and exports the transistorized grid of the 2nd PMOS to.
Described 1V level produces first, second diode that circuit comprises series connection, and wherein the negative pole of first diode connects public ground, and the positive pole of second diode connects the negative pole of the 3rd diode, and is connected with the transistorized grid of the 2nd PMOS.
Advantage of the present invention is that when input was 0V, mixed-voltage change-over circuit output was 1.7V; When input was 3.3V, output was 5V.The 1V level produces circuit output end and is stabilized in about 1V in the circuit working process.With the amplitude of oscillation is that the internal signal of 0-3.3V is converted to the output signal that the amplitude of oscillation is 0-5V, has only used withstand voltage thin grid oxygen MOS transistor as 3.3V simultaneously, under the 3.3V/5V mixed-voltage without any the grid oxygen reliability problem.
Description of drawings
Fig. 1 is a kind of schematic diagram of conventional 3.3V/5V mixing voltage output circuit.
Fig. 2 is the schematic diagram that adopts the thin existing problem of the transistorized output circuit of grid oxygen.
Fig. 3 is a 3.3V/5V mixing voltage output circuit schematic diagram proposed by the invention.
Fig. 4 be the 0-3.3V among Fig. 1 become the 1.7V-5V level shifting circuit and and the 1V level produce the instantiation schematic diagram of circuit.
Embodiment
The present invention is described in further detail below in conjunction with drawings and the specific embodiments.
As shown in Figure 3, a kind of 3.3V/5V mixing voltage output circuit,
Its operation principle is as follows:
When output enable end EN-out was high level, output circuit was enabled, and this moment, the G place of output up and down and the F place of predrive circuit all were the inversion signal of data output end Dout, and the signal of Dout is exported by the pressure welding point PAD of output node A place; When EN-out was low level, output circuit went to enable, and this moment, the G place was that 3.3V high level signal, F place are the 0V low level signal, through level shifting circuit, transistor 101,104 was turn-offed, attitude before the PAD of A place keeps.
0-3.3V become the effect of 1.7V-5V level shifting circuit 105 is that an output G place amplitude of oscillation by predrive circuit is the signal of telecommunication of 0-3.3V, and the grid D place amplitude of oscillation that is converted to PMOS transistor 101 is the signal of telecommunication of 1.7V-5V.When level shifting circuit 105 be input as 0V the time, it is output as 1.7V; When level shifting circuit 105 be input as 3.3V the time, it is output as 5V.Level shifting circuit 105 equally only adopts and withstand voltagely is the thin grid oxygen transistor of 3.3V, is emphasis of the present invention so guarantee its reliability.
The 1V level produces circuit 106 and produces stable 1V level, offers the grid E place of PMOS transistor 102.PMOS transistor 101,102 and nmos pass transistor 103,104 constitute the output stage of output circuit.Because the supply voltage VDDH of output stage is 5V, so output stage has been carried out the reinforcing of circuit stages.When being output as high level 5V, PMOS transistor 101 is opened, nmos pass transistor 104 turn-offs, because the grid of nmos pass transistor 103 meets VDD (3.3V), so the voltage at B place is 3.3V-V
TN, V
TNBe the threshold voltage of nmos pass transistor 103, this drain-to-gate voltage absolute value of just having guaranteed nmos pass transistor 104 is not higher than 3.3V; When being output as high level 5V, the grid D voltage of PMOS transistor 101 is 1.7V simultaneously, and the absolute value of its gate source voltage is 3.3V, has guaranteed the grid oxygen reliability of PMOS transistor 101.
When being output as low level 0V, nmos pass transistor 104 is opened, PMOS transistor 101 turn-offs, because the grid of PMOS transistor 102 meets the output E that the 1V level produces circuit 106, so the source electrode C place voltage of PMOS transistor 102 is 1V+V
PN, V
PNBe the threshold voltage of PMOS transistor 102, this drain-to-gate voltage absolute value of just having guaranteed PMOS transistor 101 is not higher than 3.3V.Simultaneously, because the amplitude of oscillation of the grid voltage of PMOS transistor 101 is 1.7V-5V, when being output as 0V, PMOS transistor 101 will turn-off fully, thereby avoid flowing through from VDDH to GND big dc leakage-current.
Fig. 4 shows 0-3.3V among Fig. 3 and becomes the instantiation that 1.7V-5V level shifting circuit and 1V level produce circuit.
The diode chain that diode 208-214 forms is serially connected between power vd D (3.3V) and the public ground GND.For 0.35um technology, the forward conduction voltage of diode is about 0.55V, wants to make diode in series chain 208-214 forward conduction, the forward voltage drop of the 3.9V that need have an appointment.And the pressure drop between VDD and the GND is 3.3V, so diode chain can conducting, its leakage current is less than 1uA at normal temperatures.The diode chain of not conducting shows resistance characteristic, because they all are identical diodes, be about 1V so the 1V level produces circuit output E place level, K place level is about 1.7V, and the effect of electric capacity 215,216 is level of stablizing K place and E place in the process of circuit variation.
When predrive circuit output G place level changes 0V into by 3.3V, through inverter 201 anti-phase after, the level at M place is 3.3V, nmos pass transistor 202 shutoffs at this moment, nmos pass transistor 204 unlatchings.Because the grid of nmos pass transistor 205 meets VDD (3.3V), nmos pass transistor 205 is opened, and have the 5V level to be added in the two ends of diode chain 208,209,210 this moment approximately, makes it forward conduction, thereby conversion output D place level is pulled down to about 1.7V.This moment, 206 unlatchings of PMOS transistor will be moved 5V in the J place, and PMOS transistor 207 is turn-offed fully.Like this, the 0V level conversion at G place is for about 1.7V at D place.
When the level at predrive circuit output G place changes 3.3V into by 0V, through inverter 201 anti-phase after, the level at M place is 0V, nmos pass transistor 202 unlatchings at this moment, nmos pass transistor 204 shutoffs.Because the grid of nmos pass transistor 203 meets VDD (3.3V), nmos pass transistor 203 is opened, and have the 5V level to be added in the two ends of diode chain 208,209,210 this moment approximately, makes it forward conduction, thereby J place level is pulled down to about 1.7V.This moment, 207 unlatchings of PMOS transistor will be moved 5V in the D place, and PMOS transistor 206 is turn-offed fully.Like this, the 3.3V level conversion at G place is for the 5V at D place.
In the entire circuit course of work, because the grid voltage of nmos pass transistor 205 is VDD (3.3V), the maximum level at its end I place, source is 3.3V-V
TN, 205, V
TN, 205Be the threshold voltage of nmos pass transistor 205, this drain-to-gate voltage absolute value of just having guaranteed nmos pass transistor 204 is not higher than 3.3V; Same because the grid voltage of nmos pass transistor 203 is VDD (3.3V), the maximum level at its end H place, source is 3.3V-V
TN, 203, V
TN, 203Be the threshold voltage of nmos pass transistor 203, this drain-to-gate voltage absolute value of just having guaranteed nmos pass transistor 202 is not higher than 3.3V.Because the existence of diode chain 208,209,210, the minimum level at J place and D place all is 1.7V, and this just guarantees that the drain-to-gate voltage of PMOS transistor 206,207 and the absolute value of gate source voltage are not higher than 3.3V.
Claims (1)
1. mixing voltage output circuit, comprise predrive circuit, output stage, an output (G) of predrive circuit and the level translator between the output stage, it is characterized in that, described level translator comprises that a 1V level produces circuit (106), one is used the 0-3.3V of withstand voltage thin grid oxygen MOS transistor as 3.3V to become 1.7V-5V level shifting circuit (105), described output stage comprises first of series connection, the 2nd PMOS transistor (101), (102), first of series connection, second nmos pass transistor (103), (104), the grid of a described PMOS transistor (101) connects the output (D) of 0-3.3V to 1.7V-5V level shifting circuit (105), and the grid of the 2nd PMOS transistor (102) connects the output (E) that the 1V level produces circuit (106); The grid of first nmos pass transistor (103) connects first power supply (VDD), the source electrode of the one PMOS transistor (101) connects second source (VDDH), the grid of second nmos pass transistor (104) connects another output (F) of predrive circuit, and the drain electrode of the 2nd PMOS transistor (102) links to each other with first nmos pass transistor (103) drain electrode and constitutes output node (A);
Described 0-3.3V becomes 1.7V-5V level shifting circuit (105) and comprising: source electrode is connected in the 3rd, the 4th PMOS transistor (206), (207) of second source (VDDH), the the 3rd, the 4th nmos pass transistor (202), (203) of series connection, the the 5th, the 6th nmos pass transistor (204), (205) of series connection, the 3rd to the 7th diode (210) of series connection, (211), (212), (213), (214); The positive pole of the grid of the grid of described the 4th nmos pass transistor (203), the 6th nmos pass transistor (205) and the 7th diode (214) is connected first power supply (VDD); The grid of the 3rd nmos pass transistor (202) connects predrive circuit output (G) and connects the grid of the 5th nmos pass transistor (204) by inverter (201); The drain electrode of described the 4th nmos pass transistor (203) is connected with the drain electrode of the 3rd PMOS transistor (206) and the grid of the 4th PMOS transistor (207); The drain electrode of described the 6th nmos pass transistor (205) is connected and exports to the grid of a PMOS transistor (101) with the drain electrode of the 4th PMOS transistor (207), the grid of the 3rd PMOS transistor (206); The source electrode of described the 3rd, the 5th nmos pass transistor (202), (204) is connected with the tie point of the 3rd, the 4th diode (210), (211) after linking to each other again; (210) negative pole of described the 3rd diode produces the grid that circuit exports the 2nd PMOS transistor (102) to by the 1V level;
Described 1V level produces first, second diode (208), (209) that circuit comprises series connection, wherein the negative pole of first diode (208) connects public ground, the positive pole of second diode (209) connects the negative pole of the 3rd diode (210), and is connected with the grid of the 2nd PMOS transistor (102).
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| CN2009100213539A CN101510774B (en) | 2009-03-03 | 2009-03-03 | Mixing voltage output circuit |
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| CN2009100213539A CN101510774B (en) | 2009-03-03 | 2009-03-03 | Mixing voltage output circuit |
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| CN101510774B true CN101510774B (en) | 2010-10-13 |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102843123B (en) * | 2012-08-31 | 2015-09-09 | 电子科技大学 | A kind of high-voltage driving circuit |
| CN104716938B (en) * | 2013-12-16 | 2018-03-30 | 深圳市国微电子有限公司 | A kind of grid follow imput output circuit |
| CN104270143B (en) * | 2014-10-20 | 2018-04-10 | 深圳芯邦科技股份有限公司 | The input/output (i/o) buffer of multiple voltage domain |
| CN104270142B (en) * | 2014-10-20 | 2017-05-17 | 深圳芯邦科技股份有限公司 | Input/output buffer for multiple voltage domains |
| CN109741778A (en) * | 2018-12-29 | 2019-05-10 | 西安紫光国芯半导体有限公司 | A kind of DRAM output driving circuit and its method for reducing electric leakage |
| CN112383298B (en) * | 2021-01-18 | 2021-06-11 | 灿芯半导体(上海)股份有限公司 | DDR (double data Rate) sending circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1229248A (en) * | 1997-12-24 | 1999-09-22 | 日本电气株式会社 | Voltage Conversion Buffer Circuit |
| US6836148B2 (en) * | 2002-04-08 | 2004-12-28 | Texas Instruments Incorporated | Versatile high voltage outputs using low voltage transistors |
| US7227400B1 (en) * | 2005-03-30 | 2007-06-05 | Integrated Device Technology, Inc. | High speed MOSFET output driver |
-
2009
- 2009-03-03 CN CN2009100213539A patent/CN101510774B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1229248A (en) * | 1997-12-24 | 1999-09-22 | 日本电气株式会社 | Voltage Conversion Buffer Circuit |
| US6836148B2 (en) * | 2002-04-08 | 2004-12-28 | Texas Instruments Incorporated | Versatile high voltage outputs using low voltage transistors |
| US7227400B1 (en) * | 2005-03-30 | 2007-06-05 | Integrated Device Technology, Inc. | High speed MOSFET output driver |
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