CN101488368B - Memory - Google Patents
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- CN101488368B CN101488368B CN2008102463962A CN200810246396A CN101488368B CN 101488368 B CN101488368 B CN 101488368B CN 2008102463962 A CN2008102463962 A CN 2008102463962A CN 200810246396 A CN200810246396 A CN 200810246396A CN 101488368 B CN101488368 B CN 101488368B
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Abstract
The invention provides a memory which is so formed that, in a first block and a second block each including a prescribed number of the bit lines arranged therein, positions of the bit lines simultaneously selected in the first and second blocks with reference to ends of the first and second blocks respectively are different from each other.
Description
Technical field
The present invention relates to a kind of storer, particularly relate to the storer that possesses the storage unit that contains diode.
Background technology
In the past, as an example of storer, as you know, a plurality of storage unit of each self-contained diode were configured to rectangular intersection point type mask rom (below, be called diode ROM).
In existing diode ROM, dispose many word lines and multiple bit lines in the inside of memory cell array with crossing one another.This word line is being connected line decoder (row decoder) and column decoder (column decoder) respectively with bit line.And, be provided with address input circuit, line decoder, column decoder, sensor amplifier (sense amplifier) and output circuit in the outside of memory cell array.And, be provided with a plurality of storage unit of each self-contained diode in the inside of memory cell array.Each bar of these many word lines in a plurality of storage unit edge and multiple bit lines is rectangular to be arranged, and through selecting transistor, is connected with each word line with specified quantity.Also have, the negative electrode of each self-contained diode of storage unit of the specified quantity that is connected with each word line and shared conductive layer link together.And the anode and the bit line of diode link together.
In the action of existing sense data, at first, use line decoder, change the current potential of many word lines according to the address date of address input circuit output.According to the address date of address input circuit output, will be electrically connected with sensor amplifier with selected storage unit corresponding bit line with column decoder.Thereby after sensor amplifier was differentiated and amplified the current potential of the bit line of selecting, output circuit was to external output signal.
And; Different with the structure of the signal of reading said memory cells through bit line; Consider to have source (source) line that cathodic electricity arranged in a crossed manner with many word lines and through selection transistor AND gate diode is connected, line is read the structure of the signal of the storage unit that comprises diode from the source.At this moment, sensor amplifier is connected with the source line, and after sensor amplifier was differentiated and amplified the current potential of source line, output circuit was to external output signal.
Summary of the invention
The structure of the storer of first aspect of the present invention does; Possess many word lines, with the multiple bit lines of many word line cross-over configuration, word line extends in parallel and the storage unit of the conductive layer that is provided with and the position configuration of intersecting at conductive layer and bit line relatively; At first section (block) and second section of the bit line that disposes specified quantity respectively, the end with first section of the bit line of first section of selecting simultaneously is that position and the end with second section of the bit line of second section of benchmark is that the position of benchmark is different.
The structure of the storer of second aspect of the present invention does, possesses: many word lines; Multiple bit lines with many word line cross-over configuration; Relatively word line extends in parallel and the conductive layer that is provided with; The storage unit of the position configuration of intersecting at conductive layer and bit line; And a plurality of transistors, be provided with by the storage unit of every specified quantity, grid is connected word line, and one of source electrode and drain electrode be connected conductive layer, source electrode and drain electrode another be connected the source line; At first section and second section of the bit line that disposes specified quantity respectively, the end with first section of the bit line of first section of selecting simultaneously is that position and the end with second section of the bit line of second section of benchmark is that the position of benchmark is different.
The structure of the storer of the third aspect of the invention does; Possess many word lines, with the multiple bit lines of many word line cross-over configuration, word line extends in parallel and the storage unit of the conductive layer that is provided with, the position configuration of intersecting at conductive layer and bit line and be provided with by the storage unit of every specified quantity and many linings being connected word line and conductive layer connect up relatively; First section and second section at the bit line that disposes specified quantity respectively; During sense data, the end with first section of the bit line of first section of selecting simultaneously is that position and the end with second section of the bit line of second section of benchmark is that the position of benchmark is different.
Description of drawings
Fig. 1 is the circuit diagram of the intersection point type mask rom structure of expression first embodiment of the invention.
Fig. 2 is the circuit diagram of the intersection point type mask rom structure of expression second embodiment of the invention.
Fig. 3 is the circuit diagram of the intersection point type mask rom structure of expression third embodiment of the invention.
Fig. 4 is the plane figure of the intersection point type mask rom structure of expression four embodiment of the invention.
Fig. 5 is the enlarged drawing of the intersection point type mask rom structure of four embodiment of the invention.
Embodiment
Below, according to description of drawings embodiment of the present invention.
(first embodiment)
As shown in Figure 1; The intersection point type mask rom (diode ROM) of first embodiment possesses address pre-coded (address predecode) circuit 1, line decoder 2, column decoder 3, sensor amplifier (SA) 4, NAND circuit 5, output circuit 6 and memory cell array zone 7.Address pre-coded circuit 1 constitutes: according to the address of outside input regulation, to line decoder 2 and column decoder 3 output address datas.In addition, line decoder 2 is connecting word line (WL) 8.In addition, relatively word line 8 extends in parallel and is provided with conductive layer 9.Line decoder 2 is pre-coded circuit 1 INADD data from the address.Therefore, have the corresponding word line of selecting with input 8 of address date, make the current potential of this word line 8 rise to H level (Vcc), and make the current potential of the word line 8 except that selected word line 8 become the function of L level (GND=0V).
And, between word line 8 and conductive layer 9, be provided with the transistor 10 that grid connects word line 8 and source electrode connecting conductive layer 9.Transistor 10 is an example of " the first transistor " of the present invention.Be provided with transistor 10 by 32 bit lines of stating after every 11 (32 storage unit 12).
And, connecting multiple bit lines (BL) 11 on the column decoder 3 with word line 8 arranged perpendicular.In addition, as shown in Figure 1, memory cell array zone 7 is provided with first section and second section that comprises 32 bit lines 11 respectively.
And on memory cell array zone 7, a plurality of storage unit 12 are configured to rectangular.These a plurality of storage unit 12 are configured in the intersection point place of a plurality of conductive layers 9 with the bit line 11 of orthogonal configuration respectively.On the memory cell array zone 7, be provided with the storage unit 12 that comprises the diode 13 that anode is connected with bit line 11, with the storage unit 12 that comprises the diode 13 that anode is not connected with bit line 11.
And source line 14 is connected with the drain electrode of transistor 10.Also have, clip 32 bit lines 11 and 2 source lines 14 of configuration 141 couple together through connecting up.Many (for example 1024) word lines 8 of configuration on memory cell array zone 7, word line 8 are divided into a plurality of groups of word line 8 of each self-contained fixed qty.In the first embodiment, for example, be divided into 4 group G0～G3 that constitute a group by 256 word lines 8.And, in the first embodiment, 4 (the source line 14 of S0～S3), the word lines 8 that the G0～G3 of connection group is respectively comprised are set.
The structure of column decoder 3 is according to the pre-coded circuit 1 INADD data from the address, to select the address date corresponding bit line 11 with input.At this, in the first embodiment, the lead-out terminal of phase inverter (inverter) 15 is connected with the end of bit line 11, and the lead-out terminal of NAND circuit 16 is connected with the input terminal of phase inverter 15.Phase inverter 15 is examples of " logical circuit " of the present invention with NAND circuit 16.Wiring 17 18 is connected with the input terminal of NAND circuit 16 with connecting up.Wiring 17 is respectively an example of " second wiring " of the present invention and " first wiring " with wiring 18.
And the bit line 11 that on first section and second section, has been configured 32 respectively is divided into 4 groups, and whenever adjacent 8 is one group, and 8 bit lines are connected with 8 wirings 17 respectively with NAND circuit 16 through phase inverter 15.At this, in the first embodiment, 8 adjacent bit lines 11 come the mode of select progressively to be connected in the wiring 17 according to the opposition side from a side of configuration line code translator 2 among the 8 adjacent bit lines towards a side of configuration line code translator 2.
And in the first embodiment, being divided into every adjacent 8 is the bit line 11 of 4 groups of one group, and every group connects 4 wirings 18 respectively.Be disposed among the group of 8 bit lines 11 of first section be disposed at the second section central portion side among the group of 8 bit lines 11 of 8 bit lines 11 and second section of first section end 8 bit lines 11 through NAND circuit 16 and phase inverter 15, couple together with same wiring 18.And; In the first embodiment; The input terminal of the NAND circuit 16 that is connected with the bit line that is disposed at first section end 11 be disposed at the second section central portion near the input terminal of the NAND circuit 16 that is connected of bit line 11, couple together with same wiring 18.And the input terminal of the NAND circuit 16 that is connected with near being disposed at the first section central portion bit line 11 and the input terminal of the NAND circuit 16 that is connected with the bit line that is disposed at second section end 11 couple together with same wiring 18.
And (S0～S3) is being connected an input terminal of sensor amplifier 4 respectively to connect 4 source lines 14 of the conductive layer 9 of first section and second section.Another input terminal connecting wiring 19 of sensor amplifier 4.The structure of sensor amplifier 4 does; Detect the electric current of inflow source line 14; The signal of output H level when in connecting the selected bit line 11 of source line 14, flowing through the electric current more than the rated current, and the signal of output L level when in selected bit line 11, flowing through the electric current of not enough rated current.The lead-out terminal of these 4 sensor amplifiers 4 connects the input terminal of NAND circuit 5.Its structure is that the lead-out terminal of NAND circuit 5 is connecting output circuit 6, through the output of NAND circuit 5 input sensor amplifiers 4, thus to external output signal.
The action of the diode ROM of first embodiment then, is described with reference to Fig. 1.
At first, give the address of address pre-coded circuit 1 input regulation.Thus, with the corresponding address date of this INADD from the address pre-coded circuit 1 export to line decoder 2 and column decoder 3 respectively.And, through deciphering, select regulation word line 8 corresponding to address date with 2 pairs of address dates of line decoder.And the current potential of the word line 8 after this is selected rises to H level (Vcc), and the current potential that makes non-selected word line 8 simultaneously is L level (GND).Thus, the transistor 10 that grid is connected to selected word line 8 just becomes on-state, and the conductive layer 9 that is connected to selected word line 8 is connected with source line 14.Also have, carry out being connected of the conductive layer 9 that is connected to selected word line 8 and source line 14 both of first section and second section simultaneously.
On the other hand, at the column decoder 3 of pre-coded circuit 1 INADD data, select the wiring 17 of stipulating and connect up 18 so that select and the corresponding regulation bit line of importing 11 of address date from the address.Thus, the wiring 17 of regulation and wiring 18 NAND circuit 16 and the phase inverter 15 through being connected input terminal selected the bit line 11 stipulated.
Here, in the first embodiment, when having selected the group that is positioned at the first section end side, the group that is positioned at the second section central portion side is selected simultaneously.And, when having selected the bit line 11 that is disposed at first section end, then be disposed near the bit line 11 of central portion among the bit line 11 of second section and be selected.Specifically; At first section; Select bit line 11 from the bit line 11 that is disposed at the end in order towards near the bit line 11 that is disposed at the central portion,, then select bit line 11 in order towards the bit line that is disposed at the end 11 near the bit line 11 that is disposed at the central portion at second section.Equally, at first section,,, then select bit line 11 in order towards near the bit line 11 that is disposed at the central portion from the bit line 11 that is disposed at the end at second section from being disposed near the central portion bit line 11 when the bit line that is disposed at the end 11 is selected bit line 11 in order.
Thereby the first selected section and the bit line 11 of second section are connected to sensor amplifier 4 through transistor 10 and source line 14.Source line 14 ways of connecting that flow into according to sensor amplifier 4 and electric current from selected bit line 11 are from 19 input signals that connect up.From the current potential of sensor amplifier 4 generations near Vss, and to by column decoder 3 selected bit lines 11 Vcc being provided.Extend and the conductive layer 9 that is provided with when being connected with bit line 11 with diode 13 anodes of the selected memory cell 12 of the intersection point of selected bit line 11 being positioned at respect to selected word line 8, electric current just flows to sensor amplifier 4 through word line 8 and diode 13 from bit line 11.At this moment, sensor amplifier 4 detects the above electric current of rated current and on bit line 11, flows, the signal of output L level.So output circuit 6 is exported the signal of H level through the output signal of NAND circuit 5 reception sensor amplifiers 4 and to the outside.
And, when being positioned at selected word line 8 and not being connected, do not have electric current to flow to word line 8 from bit line 11 with bit line 11 with the anode of the diode 13 of the selected memory cell 12 of the intersection point of selected bit line 11.At this moment, sensor amplifier 4 detects does not have electric current to flow, the signal of output H level.So output circuit 6 is exported the signal of L level through the output signal of NAND circuit 5 reception sensor amplifiers 4 and to the outside.
As above-mentioned, the structure of first embodiment does, at first section, data of reading the bit line 11 that is positioned at first section end with source line 14, and at second section are read the data that are positioned near the bit line 11 the second section central portion with source line 14.Thus; Be positioned at the bit line 11 of end; Because the storage unit 12 that is connected with bit line 11 and the distance of the conductive layer 9 between the transistor 10 are little, thus the big electric current that flows, and be positioned near the bit line 11 the central portion; Because the distance of the conductive layer 9 between storage unit 12 and the transistor 10 is big, so the little electric current that flows.Thereby in both of first section and second section, with different during from bit line 11 sense datas that are positioned at the end with source line 14, big electric current and little electric current flow to source line 14 from the bit line of reading simultaneously 11.So compare to the occasion that source line 14 flows from the bit line of reading simultaneously 11 each other with big electric current, can reduce the size of current amount flowing in source line 14.Its result, can suppress current sinking (consumed power) increases.
In the first embodiment; As above-mentioned; Connect the input terminal that passes through the NAND circuit 16 that phase inverter 15 is connected with the bit line that is disposed at end side 11 among 32 bit lines 11 of first section with same wiring 18, an input terminal of the NAND circuit 16 that is connected with near the bit line 11 of side the passing through phase inverter 15 and being disposed at the second section central portion among 32 bit lines 11 of second section.Therefore, can easily constitute the data of reading the bit line 11 that is positioned at first section end with source line 14, and read the data that are positioned at second section central portion bit line 11 nearby with source line 14.
In the first embodiment, as above-mentioned, it is 4 groups of one group that 32 bit lines 11 of first section and second section are divided into every 8 adjacent bit lines 11 respectively.With the group that is positioned at the central portion side among 4 groups of the group that is positioned at end side among 4 groups of same wiring 18 connections first section and second section.Therefore, can easily select the group that is positioned at the central portion side among the bit line 11 of the group that is positioned at end side and second section among the bit line 11 of first section simultaneously.
In the first embodiment, the mode of selecting according to the side from the opposition side of a side of configuration line code translator 2 towards configuration line code translator 2 18 is connected the input terminal of NAND circuit 16 and wiring 17 with connecting up.Therefore, can select the group that is positioned at the central portion side among the group of bit line 11 of the group that is positioned at end side and second section among the group of bit line 11 of first section simultaneously.At this moment can as following, constitute, that is, in first section, near central portion, select bit line 11 in order from the end, in second section then from selecting bit line 11 in order to the end near the central portion.
In the first embodiment, as above-mentioned, adopt lead-out terminal to be connected the NAND circuit 16 that phase inverter 15 and lead-out terminal on the bit line 11 be connected on the input terminal of phase inverter 15 and constitute logical circuits.Therefore, 17 input to the signal of H level the way of NAND circuit 16 respectively, can be easily select the bit line 11 that be connected with this NAND circuit 16 through phase inverter 15 with wiring 18 through adopting from connecting up.
(second embodiment)
In the diode ROM of second embodiment, different with above-mentioned first embodiment, export by an output circuit 6 from the signal of 64 bit lines 11.
As shown in Figure 2, the diode ROM of second embodiment is provided with between word line 8 and conductive layer 9 that grid is connected with word line 8 and the transistor 10 of source electrode connecting conductive layer 9.By per 32 bit lines 11 (32 storage unit 12) transistor 10 is set.On the 7a of memory cell array zone, be provided with 2 first section and 2 second sections that comprise 32 bit lines 11 that comprise 32 bit lines 11.2 first sections (second section) couple together through transistor 10.And the end of 2 first sections (second section) is through transistor 10 connection source line 14a.Between 2 first sections (second section), source line 14b is connected to the drain electrode of transistor 10.Also have, source line 14a and source line 14b connect.And the input terminal and the source line 14a that constitute sensor amplifier 4 link together, an output of 64 bit lines, the 11 outputs signal that is comprised from 2 first sections (second section).
Here, in second embodiment, it is 2 groups of one group that 32 bit lines 11 of first section and second section are divided into every 16 adjacent bit lines 11 respectively.Through phase inverter 15 and NAND circuit 16; Connect with wiring 18 in the group of bit line 11 of 2 first sections from the first section end side direction central portion side select bit line 11 group bit line 11 and select the bit line 11 of the group of bit line 11 from the second section central portion lateral end side.
In addition, other structure of second embodiment is identical with above-mentioned first embodiment.
And the action of second embodiment is identical with above-mentioned first embodiment.
In second embodiment, as above-mentioned, it is 2 groups of one group that 32 bit lines 11 of first section and second section are divided into every 16 adjacent bit lines 11 respectively.Connect with wiring 18 among the group of bit line 11 of 2 first sections from the first section end side direction central portion side and select the group of bit line 11 and select the group of bit line 11 from the second section central portion lateral end side.Therefore, the bit line 11 that can select to be positioned at first section end simultaneously and flow through big electric current be positioned near the second section central portion and flow through the little bit line of electric current 11.So compare to the occasion that source line 14 flows from the bit line of reading simultaneously 11 each other with big electric current, can reduce the size of current amount flowing in source line 14.Its result, can suppress current sinking (consumed power) increases.
Also have, other effect of second embodiment and above-mentioned first embodiment are same.
(the 3rd embodiment)
The diode ROM of the 3rd embodiment, as shown in Figure 3, have address input circuit 201, line decoder 202, column decoder 203, sensor amplifier 204, output circuit 205 and memory cell array zone 206.Address input circuit 201 constitutes, according to the input specified address from the outside, to line decoder 202 and column decoder 203 output address datas.And word line (WL) 207 is connected with line decoder 202.The mode that extends in parallel according to relative word line 207 is provided with conductive layer 208.Word line 207 and conductive layer 208 use the lining wiring 209 that is provided with by 8 storage unit 211 stating after every to connect.And; Line decoder 202 has; According to from address input circuit 201 INADD data; Select the corresponding word line 207 of address date with input, make the current potential of this word line 207 drop to L level (GND=0V), and to make the current potential of the word line 207 except that selected word line 207 be the function of H level (Vcc).
And, connecting multiple bit lines (BL) 210 on the column decoder 203 with word line 207 arranged perpendicular.Between adjacent lining wiring 209, clip 8 bit lines 210 (210a～210h, 210i～210p).The zone that the multiple bit lines 210a～210h that is clipped by lining wiring 209 is put in establishing is first section, and the zone that multiple bit lines 210i～bit line 210p is put in establishing is second section.
And on memory cell array zone 206, a plurality of storage unit 211 are configured to rectangular.These a plurality of storage unit 211 are configured in the intersection point place of a plurality of conductive layers 208 with the bit line 210 of orthogonal configuration respectively.On memory cell array zone 206, be provided with the storage unit 211 that comprises the diode 212 that anode is connected with bit line 210 and the storage unit 211 that comprises the diode 212 that anode is not connected with bit line 210.
And column decoder 203 constitutes, and connects its selected bit line 210 and sensor amplifier 204 through p transistor npn npn 213.Wiring 214 couples together with the grid of each transistor 213 respectively.Also have, transistor 213 is examples of " transistor seconds " of the present invention.Wiring 214 is examples of " the 3rd wiring " of the present invention.Column decoder 203 is selected the bit line 210 corresponding to the address date of input according to from address input circuit 201 INADD data.At this, in the 3rd embodiment, the grid of the grid of the transistor 213 that is connected with the bit line 210a that same wiring 214 connects with first section is comprised and the transistor 213 that is connected with bit line 210m that second section is comprised.Also have, bit line 210a is disposed at the end at first section, and bit line 210m is near second section is disposed at central portion.
And; Sensor amplifier 204 detects the electric current that flows in the bit line of selecting with column decoder 203 210; When the signal of output H level during the electric current more than the mobile rated current in the selected bit line 210, then export the signal of L level in the selected bit line 210 during the electric current of flow insufficient rated current.Output circuit 205 constitutes, according to the output of importing sensor amplifier 204 and to external output signal.
Then, with reference to Fig. 3, the action of the diode ROM of the 3rd embodiment is described.
At first, the address with regulation inputs to address input circuit 201.Thus, the address date corresponding to this INADD inputs to line decoder 202 and column decoder 203 respectively from address input circuit 201.And, through deciphering, select regulation word line 207 corresponding to address date with 202 pairs of address dates of line decoder.And, make the current potential of this selected word line 207 drop to L level (GND), and make the current potential of unselected word line 207 then be H level (Vcc).
On the other hand, import from address input circuit 201 column decoder 203 of address date, select regulation bit line 210, and bit line 210 that should be selected connects sensor amplifier 204 corresponding to the address date of input.And, the current potential near Vcc is provided for selected bit line 210 by sensor amplifier 204.Be positioned at respect to selected word line 207 and extend and the conductive layer 208 that is provided with when being connected with bit line 210 with the anode of the diode 212 of the selected storage unit 211 at the intersection point place of selected bit line 210, electric current just passes through bit line 210 and diode 212 is mobile to word line 207 from sensor amplifier 204.In this time, sensor amplifier 204 detects the above electric current of regulation that flows in the bit line 210, the signal of output H level.And output circuit 205 receives the output signal of sensor amplifiers 204 and to the signal of outside output H level.
And, when being positioned at selected word line 207 and not being connected, do not have electric current mobile to word line 207 from bit line 210 with bit line 210 with the anode of the diode 212 of the selected storage unit 211 at the intersection point place of selected bit line 210.At this moment, sensor amplifier 204 detects does not have electric current to flow, thus the signal of output L level.And output circuit 205 receives the output signal of sensor amplifiers 204 and to the signal of outside output L level.
At this, through giving wiring 214 input signals, make transistor 213 become on-state, the bit line 210 of selecting first section and second section to comprise respectively by each one mode.The bit line 210 of selecting first section to be comprised in order to the bit line 210h that is positioned at the other end from the bit line 210a that is positioned at first section, one end.In the 3rd embodiment,, when selecting the bit line 210a of first section, one end, then select to be positioned near the bit line 210m of the second section central portion at second section.Then, select bit line 210n～bit line 210p in order.When near the bit line 210e the selection first section central portion, then selection is positioned at the bit line 210i of an end of second section.Then, select bit line 210j～bit line 2101 in order towards the second section central portion.Like this, in the 3rd embodiment, be elected to when being positioned the bit line 210 of the first section end side,, then select to be positioned at the bit line 210 of central portion at second section.And, be elected to when being positioned the bit line 210 of the first section central portion side, at second section, then select to be positioned at the bit line 210 of end side.
In the 3rd embodiment; Constitute through as above-mentioned, reading data that are positioned at the first section end side bit line 210 and the data that are positioned at the second section central portion side bit line 210 simultaneously suchly, just can call current amount flowing many end side bit lines 210 and the few central portion side bit line 210 of current amount flowing simultaneously.Therefore; For both of first section and second section, different with occasion from bit line 210 sense datas that are positioned at the end, big electric current and little electric current flow in the bit line of reading simultaneously 210; So compare with the occasion that big electric current flows each other, can reduce the size of streaming current amount.Its result, can suppress current sinking (consumed power) increases.
And in the 3rd embodiment, the data of as above-mentioned, reading the data of the bit line 210a that is positioned at first section end simultaneously and being positioned near the bit line 210m the second section central portion constitute suchly.Therefore, different for both of first section and second section with occasion from bit line 210 sense datas that are positioned at the end, compare with the occasion that flows in the bit line 210 that big electric current is read each other at the same time, can reduce the current amount flowing size easily.
And; As above-mentioned; The structure of the 3rd embodiment is; Wiring 214 is when sense data; Select simultaneously when the bit line 210 of first section and second section, connect the transistor 213 that is disposed at end side among the transistor 213 of multiple bit lines 210 of first section that is clipped by lining wiring 209 respectively and be on-state, connect near the transistor 213 that is disposed among the transistor 213 of multiple bit lines 210 of second section that is clipped by lining wiring 209 central portion simultaneously respectively and be on-state.Therefore; Can call current amount flowing many bit line 210a and the few bit line 210m of current amount flowing simultaneously; So for both of first section and second section; Different with occasion from bit line 210 sense datas that are positioned at the end, compare with the occasion that flows in the bit line 210 that big electric current is read each other at the same time, can easily reduce the current amount flowing size.
(the 4th embodiment)
The diode ROM of this 4th embodiment is different with above-mentioned the 3rd embodiment, and 32 bit lines 231 are clipped by lining wiring 230.
As shown in Figure 4; The diode ROM of the 4th embodiment has address input circuit 221, line decoder 222, column decoder 223, sensor amplifier (SA) 224a～224h, NAND circuit 225a and 225b, output circuit 226a and 226b and memory cell array zone 227. Sensor amplifier 224a, 224c, 224e and 224g are examples of " first sensor amplifier " of the present invention, and sensor amplifier 224b, 224d, 224f and 224h are examples of " second sensor amplifier " of the present invention.Address input circuit 221 constitutes, and according to the address of the input regulation from the outside, gives line decoder 222 and column decoder 223 output address datas.And word line 228 links together with line decoder 222.Word line 228 is provided with conductive layer 229 with extending in parallel relatively.Word line 228 is connected through the lining wiring 230 that is provided with by 16 storage unit 232 stating after every with conductive layer 229.And; Line decoder 222 has according to the address date from address input circuit 221 inputs; Select the corresponding word line 228 of address date with input; Make the current potential of this word line 228 drop to L level (GND=0V), make the word line 228 except that selected word line 228 be the function of H level (Vcc) simultaneously.
And column decoder 223 connects the multiple bit lines 231 with word line 228 arranged perpendicular.32 bit lines 231 of bit line 231 are clipped by adjacent lining wiring 230.
And, on memory cell array zone 227, be rectangular a plurality of storage unit 232 that dispose.Many word lines 228 relatively that these a plurality of storage unit 232 are configured in orthogonal configuration respectively extend in parallel and the intersection point place of the conductive layer 229 that disposes and multiple bit lines 231.And, on memory cell array zone 227, be provided with the storage unit 232 that comprises the diode 233 that anode is connected with bit line 231, the storage unit 232 of the diode 233 that is not connected with anode with bit line 231.
As shown in Figure 5; Column decoder 223 is according to the address date from address input circuit 221 (with reference to Fig. 4) input; Selection is corresponding to the bit line 231 of address date of input, and connects among this selected bit line 231 and the sensor amplifier 224a～224h through p transistor npn npn 234.Also have, the grid of each transistor 234 is connecting respectively and is connecting up 235.Multiple bit lines 231 constitutes, and the bit line 231 that is positioned at an end among the 16 adjacent bit lines 231 is selected to the bit line that is positioned at the other end 231 in order.
And as shown in Figure 4, per 16 of 32 bit lines 231 that clipped by lining wiring 230 are connected with sensor amplifier 224a～224h.And sensor amplifier 224a～224d is connected with NAND circuit 225a, and NAND circuit 225a is connected with output circuit 226a.And sensor amplifier 224e～224h is connected with NAND circuit 225b, and NAND circuit 225b is connected with output circuit 226b.Constitute like this, from (64 bit lines 231 of sensor amplifier 224e～224h) be connected obtain an output with sensor amplifier 224a～224d.Also have, the zone that will dispose the bit line 231 that is connected with 224b (224d) with sensor amplifier 224a (224c) is made as first section, and the zone that will dispose the bit line 231 that is connected with 224f (224h) with sensor amplifier 224e (224g) is made as second section.
And; Multiple bit lines 231 near first section end sense data central portion among the bit line 231 of sensor amplifier 224a (224c) and first section is connected, sensor amplifier 224b (224d) be connected near the multiple bit lines 231 to the end sense data first section central portion.And; Multiple bit lines 231 near second section end sense data central portion among the bit line 231 of sensor amplifier 224e (224g) and second section is connected, sensor amplifier 224f (224h) be connected near the multiple bit lines 231 to the end sense data second section central portion.
And the end of sensor amplifier 224a～224h is connected with bit line 231, and is connected with wiring 236.Also have, wiring 236 is examples of " the 4th wiring " of the present invention.Through connecting sensor amplifier 224a (224b) and sensor amplifier 224f (224e), can select sensor amplifier 224a (224b) and sensor amplifier 224f (224e) simultaneously with same wiring 236.Through connecting sensor amplifier 224c (224d) and sensor amplifier 224h (224g), can select sensor amplifier 224c (224d) and sensor amplifier 224h (224g) simultaneously with same wiring 236.
Like this; The 4th embodiment; Its structure is; Select simultaneously with sensor amplifier 224a～224d that output circuit 226a is connected among bit line 231 from first section end to the sensor amplifier 224a of its central portion sense data (224c), with sensor amplifier 224e～224h that output circuit 226b is connected among continuous bit line 231 near the second section central portion to the sensor amplifier 224f of its end sense data (224h).And; The 4th embodiment; Its structure is; Select simultaneously with sensor amplifier 224a～224d that output circuit 226a is connected among bit line 231 near the first section central portion to the sensor amplifier 224b of its end sense data (224d), with sensor amplifier 224e～224h that output circuit 226b is connected among continuous bit line 231 near the sensor amplifier 224e (224g) of second section end sense data its central portion.
Then, with reference to Fig. 4 and Fig. 5, the action of the diode ROM of the 4th embodiment is described.
At first, the address with regulation inputs to address input circuit 221.Thus, the address date corresponding to this INADD just is transfused to respectively to line decoder 222 and column decoder 223 from address input circuit 221.And, through deciphering, select regulation word line 228 corresponding to this address date with 222 pairs of address dates of line decoder.Make the current potential of this selected word line 228 drop to L level (GND), the current potential that makes non-selected word line 228 simultaneously is H level (Vcc).
On the other hand; Import from address input circuit 221 column decoder 223 of address date; Because grid is in on-state with the transistor 234 that wiring 235 is connected; Thereby select, and be connected to a sensor amplifier among sensor amplifier 224a～224h that this selected bit line 231 connected corresponding to the regulation bit line 231 of INADD data.Here, suppose the bit line 231a that has selected first section that is connected with sensor amplifier 224a.Secondly, to selected bit line 231a the current potential near Vcc is provided by sensor amplifier 224a.And; Because wiring 236 input signals from being connected with sensor amplifier 224a; Be positioned at the anode of selected word line 228 and the diode 233 of the selected memory cell 232 of selected bit line 231a intersection point; With situation that bit line 231a is connected under, electric current is mobile to word line 228 with diode 233 through bit line 231a from sensor amplifier 224.At this moment, sensor amplifier 224a detects the above electric current of regulation and in bit line 231a, flows, the signal of output H level.And output circuit 226a exports the signal of H level through the output signal of NAND circuit 225a reception sensor amplifier 224a and to the outside.
And; Select the bit line 231b that connected with the wiring that is connected bit line 231a 235 identical wirings 235 simultaneously with bit line 231a, and select the sensor amplifier 224f that connected with the wiring that is connected sensor amplifier 224a 236 identical wirings 236 simultaneously with sensor amplifier 224a.Under its result, the anode that is positioned at selected word line 228 and the diode 233 of the selected memory cell 232 of selected bit line 231b intersection point and the situation that bit line 231b is connected, electric current is mobile to word line 228 from sensor amplifier 224 with diode 233 through bit line 231b.At this moment, sensor amplifier 224f detects the above electric current of regulation and in bit line 231b, flows, and just exports the signal of H level.And output circuit 226b exports the signal of H level through the output signal of NAND circuit 225b reception sensor amplifier 224f and to the outside.
And, be positioned at selected word line 228 and selected bit line 231a (231b) intersection point selected storage unit 232 diode 233 anode not with situation that bit line 231a (231b) is connected under, do not have electric current mobile to word line 228 from bit line 231a (231b).At this moment, sensor amplifier 224a (224f) detects does not have electric current to flow, and just exports the signal of L level.And output circuit 226a (226b) exports the signal of L level through the output signal of NAND circuit 225a (225b) reception sensor amplifier 224a (224f) and to the outside.
In the 4th embodiment; As above-mentioned, diode ROM comprise among the bit line 231 with first section from the end to sensor amplifier 224a (224c) that near the multiple bit lines 231 of the sense data central portion is connected with the bit line 231 of second section among near be connected to the multiple bit lines 231 of end sense data the central portion sensor amplifier 224f (224h) and constitute.Therefore, owing to select sensor amplifier 224a (224c) and sensor amplifier 224f (224h) simultaneously, can call near the bit line 231 of the first many section end of streaming current amount second section central portion the bit line 231 few simultaneously with the streaming current amount.Thereby, different for both of first section and second section with occasion from bit line 231 sense datas that are positioned at the end, compare with the occasion that flows in the multiple bit lines 231 that big electric current calls each other at the same time, can reduce the size of streaming current amount.Therefore, can suppress current sinking (consumed power) increases.Equally, diode ROM comprise among the bit line 231 with first section near the central portion to sensor amplifier 224b (224d) that the multiple bit lines 231 of end sense data is connected with the bit line 231 of second section among near the multiple bit lines 231 of sense data is connected central portion from the end sensor amplifier 224e (224g) and constituting.Therefore, owing to select sensor amplifier 224b (224d) and sensor amplifier 224e (224g) to constitute simultaneously, can call the bit line 231 of near the first few section central portion of streaming current amount bit line 231 and streaming current amount second section end how simultaneously.So, for both of first section and second section,, compare with the occasion that flows in the multiple bit lines 231 that big electric current calls each other at the same time with different from the bit line 231 sense data occasions that are positioned at the end, can reduce the size of streaming current amount.Also have, not selected sensor amplifier among sensor amplifier 224a～224h, controlled in sensor amplifier 224a～224h, be in the state that phase pairs of bit line 231 is separated.
And the 4th embodiment as above-mentioned, has the wiring of being located between sensor amplifier 224a～224h and the bit line 231 236.Wiring 236 couples together sensor amplifier 224a, 224b, 224c and 1224d and sensor amplifier 224f, 224e, 224h and 224g respectively.Therefore, the sensor amplifier that is easy to select simultaneously respectively near the bit line 231 the central portion with the bit line 231 of first section and end second section, a side and the opposing party to be connected.
Moreover this time disclosed embodiment all is for example in all respects, should think not to be restrictive.Scope of the present invention is not the explanation of above-mentioned embodiment, and is represented by the claim scope, and then comprises and the meaning of claim scope equalization and all changes in the scope.
For example, in above-mentioned first～the 4th embodiment, though be applied to intersect the point type mask rom to the present invention, the present invention is not limited only to this, also can be widely used in having intersecting the storer of the storage unit that contains diode beyond the point type mask rom.
And, in above-mentioned first and second embodiments, though represented to the invention is not restricted to this by transistorized example of per 32 bit lines configuration, also can be by the transistor of bit line configuration beyond per 32.
And; In above-mentioned first and second embodiments; Though represented to constitute the example of the logical circuit that is connected with bit line through inverter circuit and NAND circuit, the invention is not restricted to this, also can use the circuit beyond inverter circuit and/or the NAND circuit to constitute logical circuit.
And, in above-mentioned first and second embodiments, be connected with conductive layer though represented transistorized source electrode; And the example that transistor drain is connected with the source line; But the invention is not restricted to this, also can transistor drain be connected with conductive layer, and transistorized source electrode is connected with the source line.
And; In above-mentioned first and second embodiments; Though represented sequentially to select the bit line of first section to the central portion side, from the example of the bit line of central portion lateral end side select progressively second section, the invention is not restricted to this simultaneously from end side; Also can be from end side to the central portion side; By the 2nd, the 1st, the 3rd, the 4th, the 6th, the 5th, the 7th, the 8th ... the bit line of select progressively first section, simultaneously from central portion lateral end side, by the 2nd, the 1st, the 3rd, the 4th, the 6th, the 5th, the 7th, the 8th ... the bit line of select progressively second section.That is, also can be in fact select the bit line of first section to the central portion side, select the bit line of second section simultaneously in fact from central portion lateral end side from end side.
And, in above-mentioned third and fourth embodiment,, also can connect up with bit line configuration linings beyond 32 by per 8 though represented respectively to the invention is not restricted to this by per 8 and by the example of per 32 bit line configuration lining wiring.
And; In above-mentioned third and fourth embodiment; Though represented from the bit line of end side to central portion side select progressively first section; Simultaneously from the example of the bit line of central portion lateral end side select progressively second section; But the invention is not restricted to this, also can be by the bit line 210 of the select progressively of bit line 210b, 210a, 210c, 210d, 210f, 210e, 210g and 210h first section shown in Figure 3, press the bit line 210 of select progressively second section of bit line 210n, 210m, 210o, 210p, 210j, 210i, 210k and 2101 simultaneously.That is, also can be in fact select the bit line 210 of first section to the central portion side, select the bit line 210 of second section simultaneously in fact from central portion lateral end side from end side.
Claims (17)
1. storer possesses:
Many word lines;
Multiple bit lines is with above-mentioned many word line cross-over configuration;
Conductive layer, above-mentioned relatively word line extends in parallel and is provided with;
Storage unit is configured in the position that above-mentioned conductive layer and above-mentioned bit line intersect,
In first section and second section of the above-mentioned bit line that disposes specified quantity respectively; The end with above-mentioned first section of the bit line of above-mentioned first section of selecting simultaneously is that the end with above-mentioned second section of bit line of position and above-mentioned second section of benchmark is that the position of benchmark is different
Also possess a plurality of the first transistors, be provided with by the said memory cells of every specified quantity, grid is connected with above-mentioned word line, and source electrode is connected with above-mentioned conductive layer with one of drain electrode, and another of above-mentioned source electrode and drain electrode is connected with the source line.
2. storer according to claim 1 is characterized in that,
When among the multiple bit lines of having selected above-mentioned first section, being disposed at the bit line of end side, select to be disposed among the multiple bit lines of above-mentioned second section bit line of central portion side.
3. storer according to claim 2 is characterized in that,
When among the bit line of the end side of having selected above-mentioned first section, being disposed at the bit line of end, select to be disposed among the bit line of above-mentioned second section near the bit line the central portion.
4. storer according to claim 2 is characterized in that,
Also possess: logical circuit, lead-out terminal is connected with each bar of above-mentioned multiple bit lines; With
First wiring is connected with the input terminal of above-mentioned logical circuit,
One of input terminal of the above-mentioned logical circuit that is connected with the bit line that is disposed at the end among the multiple bit lines of above-mentioned first section with the multiple bit lines of above-mentioned second section among be disposed at one of input terminal of the above-mentioned logical circuit that near the bit line the central portion of above-mentioned second section is connected, connect with above-mentioned first wiring.
5. storer according to claim 4 is characterized in that,
The multiple bit lines of above-mentioned first section and above-mentioned second section is that a component becomes a plurality of groups by the bit line of adjacent some respectively,
Be positioned at the group that is positioned at the central portion side among the group of bit line of group and above-mentioned a plurality of second sections of end side among the group of the bit line of above-mentioned a plurality of first sections, connect with above-mentioned first wiring.
6. storer according to claim 5 is characterized in that,
Also possess another second wiring that is connected with the input terminal of above-mentioned logical circuit,
Divide bit line,, be connected with above-mentioned second wiring according to the mode of selecting in order to the bit line that is disposed at another end from the bit line that is disposed at an end among the adjacent bit lines that is divided into after above-mentioned group for above-mentioned group.
7. storer according to claim 4 is characterized in that,
The multiple bit lines of above-mentioned first section and above-mentioned second section is that a component becomes a plurality of groups by the bit line of adjacent some respectively,
Among the group of the bit line of above-mentioned a plurality of first sections, select the group of above-mentioned bit line and select the group of above-mentioned bit line in fact from the second section central portion lateral end side from the first section end side direction central portion side in fact, connect with above-mentioned first wiring.
8. storer according to claim 4 is characterized in that,
Above-mentioned logical circuit is made up of phase inverter and NAND circuit, and the lead-out terminal of above-mentioned phase inverter is connected with above-mentioned bit line, and the lead-out terminal of above-mentioned NAND circuit is connected with the input terminal of above-mentioned phase inverter.
9. storer possesses:
Many word lines;
Multiple bit lines is with above-mentioned many word line cross-over configuration;
Conductive layer, above-mentioned relatively word line extends in parallel and is provided with;
Storage unit is configured in the position that above-mentioned conductive layer and above-mentioned bit line intersect,
In first section and second section of the above-mentioned bit line that disposes specified quantity respectively; The end with above-mentioned first section of the bit line of above-mentioned first section of selecting simultaneously is that the end with above-mentioned second section of bit line of position and above-mentioned second section of benchmark is that the position of benchmark is different
Also possess many lining wirings, be provided with by the said memory cells of every specified quantity, and connect above-mentioned word line and above-mentioned conductive layer.
10. storer according to claim 9 is characterized in that,
When among the multiple bit lines of having selected above-mentioned first section, being disposed at the bit line of end side, select to be disposed among the multiple bit lines of above-mentioned second section bit line of central portion side.
11. storer according to claim 10 is characterized in that,
When among the bit line of the above-mentioned end side of having selected above-mentioned first section, being disposed at the bit line of end, select to be disposed among the bit line of above-mentioned central portion side of above-mentioned second section near the bit line the central portion.
12. storer according to claim 10 is characterized in that,
Also possess:
Sensor amplifier, the above-mentioned bit line of connection specified quantity;
Transistor seconds is configured between above-mentioned bit line and the above-mentioned sensor amplifier, and connects each bar of above-mentioned bit line; With
The 3rd wiring connects above-mentioned transistorized grid,
The above-mentioned the 3rd when being routed in sense data; Select simultaneously when the bit line of above-mentioned first section and above-mentioned second section; The above-mentioned transistor seconds that is disposed at end side among the above-mentioned transistor seconds that each bar of the above-mentioned bit line that comprises with above-mentioned first section is connected is an on-state, and the above-mentioned transistor seconds that is disposed at the central portion side among the above-mentioned transistor seconds that each bar of the above-mentioned bit line that comprises with above-mentioned second section is connected is an on-state.
13. storer according to claim 9 is characterized in that,
Above-mentioned first section and above-mentioned second section are provided with a plurality of respectively,
In above-mentioned a plurality of first sections and above-mentioned a plurality of second section of the above-mentioned bit line that disposes specified quantity respectively; The end with above-mentioned first section of the bit line of above-mentioned first section among above-mentioned a plurality of first sections of selecting simultaneously during sense data is the position of benchmark, is that the position of benchmark is different with the end with above-mentioned second section of the bit line of above-mentioned second section among above-mentioned a plurality of second sections.
14. storer according to claim 13 is characterized in that,
When among the multiple bit lines of having selected above-mentioned first section, being disposed at the bit line of end side, select to be disposed among the multiple bit lines of above-mentioned second section bit line of central portion side.
15. storer according to claim 14 is characterized in that,
Also possess: first sensor amplifier, the above-mentioned multiple bit lines that is comprised with above-mentioned first section is connected; With second sensor amplifier, the above-mentioned multiple bit lines that is comprised with above-mentioned second section is connected,
Above-mentioned first sensor amplifier be connected near end side many above-mentioned bit lines of sense data central portion in fact, above-mentioned second sensor amplifier be connected from many above-mentioned bit lines of central portion lateral end side sense data in fact,
Above-mentioned first sensor amplifier and above-mentioned second sensor amplifier are selected simultaneously.
16. storer according to claim 15 is characterized in that,
Also possess the 4th wiring, be arranged between above-mentioned first sensor amplifier and above-mentioned second sensor amplifier and the above-mentioned bit line,
Above-mentioned the 4th wiring connects above-mentioned first sensor amplifier and above-mentioned second sensor amplifier.
17. storer according to claim 13 is characterized in that,
Also possess:
First output circuit and second output circuit, the data that output is exported from above-mentioned bit line; With
A plurality of sensor amplifiers, an end is connected with the bit line of some among the above-mentioned multiple bit lines, and the other end is connected with above-mentioned first output circuit or above-mentioned second output circuit,
The above-mentioned a plurality of sensor amplifiers that are connected with above-mentioned first output circuit connect the bit line that is disposed on above-mentioned a plurality of first section, and the above-mentioned a plurality of sensor amplifiers that are connected with above-mentioned second output circuit connect the bit line that is disposed on above-mentioned a plurality of second section,
Above-mentioned sensor amplifier constitutes; With the bit line of the above-mentioned some that is connected with first sensor amplifier among above-mentioned a plurality of sensor amplifiers that above-mentioned first output circuit is connected from above-mentioned first section end to the central portion sense data; With the bit line of the above-mentioned some that is connected with second sensor amplifier among above-mentioned a plurality of sensor amplifiers that above-mentioned second output circuit is connected near the above-mentioned second section central portion to the end sense data
Above-mentioned first sensor amplifier and above-mentioned second sensor amplifier are selected simultaneously.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007-289792 | 2007-11-07 | ||
| JP2007289792A JP4383478B2 (en) | 2007-11-07 | 2007-11-07 | memory |
| JP2007289792 | 2007-11-07 | ||
| JP2007293823 | 2007-11-13 | ||
| JP2007-293823 | 2007-11-13 | ||
| JP2007293823A JP4383479B2 (en) | 2007-11-13 | 2007-11-13 | memory |
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| CN101488368A CN101488368A (en) | 2009-07-22 |
| CN101488368B true CN101488368B (en) | 2012-03-28 |
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| CN101964211B (en) * | 2010-10-12 | 2015-12-02 | 上海华虹宏力半导体制造有限公司 | Chip erasing method |
| KR20130119196A (en) * | 2012-04-23 | 2013-10-31 | 에스케이하이닉스 주식회사 | Semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1885547A (en) * | 2005-06-24 | 2006-12-27 | 三洋电机株式会社 | Memory |
| CN1901199A (en) * | 2005-07-22 | 2007-01-24 | 三洋电机株式会社 | Memory |
| CN101047034A (en) * | 2006-03-28 | 2007-10-03 | 三洋电机株式会社 | Memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1885547A (en) * | 2005-06-24 | 2006-12-27 | 三洋电机株式会社 | Memory |
| CN1901199A (en) * | 2005-07-22 | 2007-01-24 | 三洋电机株式会社 | Memory |
| CN101047034A (en) * | 2006-03-28 | 2007-10-03 | 三洋电机株式会社 | Memory |
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| JP2009116968A (en) | 2009-05-28 |
| JP4383478B2 (en) | 2009-12-16 |
| CN101488368A (en) | 2009-07-22 |
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