CN101483192A - Vertical fense MOSFET device and manufacturing method thereof - Google Patents
Vertical fense MOSFET device and manufacturing method thereof Download PDFInfo
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Abstract
本发明涉及微电子器件制造领域，公开了一种垂直围栅MOSFET器件及其制造方法。该垂直围栅MOSFET器件，包括：半导体衬底，垂直设置在半导体衬底上的圆柱形的沟道区，沟道区的圆柱形外设置有截面为槽形的环状的介质层，所述槽形开口向上，所述介质层的槽内设置有环状的栅导电层，所述介质层的槽外设置有环状的漏导电层，所述介质层的槽外底部与所述半导体衬底接触，所述沟道区上设置有源导电层，其圆柱形上部掺n+杂质作为源端n+区，与漏导电层底部接触的半导体衬底区域掺n+杂质作为漏端n+区，其特征在于，所述沟道区的圆柱形中部设置有非对称Halo掺杂结构p+区。
The invention relates to the field of manufacturing microelectronic devices, and discloses a vertical gate MOSFET device and a manufacturing method thereof. The vertical gate MOSFET device includes: a semiconductor substrate, a cylindrical channel region vertically arranged on the semiconductor substrate, and a ring-shaped dielectric layer with a groove-shaped cross section arranged outside the cylindrical channel region. The opening of the groove is upward, and a ring-shaped gate conductive layer is arranged in the groove of the dielectric layer, and a ring-shaped drain conductive layer is arranged outside the groove of the dielectric layer, and the outer bottom of the groove of the dielectric layer is connected with the semiconductor substrate Bottom contact, an active conductive layer is arranged on the channel region, and its cylindrical upper part is doped with n+ impurities as the source n+ region, and the semiconductor substrate region in contact with the bottom of the drain conductive layer is doped with n+ impurities as the drain n+ region, its characteristics In that, the cylindrical middle part of the channel region is provided with an asymmetrical Halo-doped structure p+ region.
Description
Technical field
The present invention relates to microelectronic component and make field, particularly a kind of vertical fense MOSFET device and manufacture method thereof.
Background technology
The continuing to dwindle of microelectronic component size improves constantly integrated circuit density, and performance is constantly improved, and cost continues to descend.Along with the MOSFET size enters nanometer range, short-channel effect and subthreshold performance degradation have limited further dwindling of device size.In order to make integrated circuit after inferior 50nm, still have superperformance, need innovate from aspects such as device architecture and materials.Aspect device architecture, multiple-grid MOSFET becomes the research focus.
The double-gate structure that proposes in the eighties, two grid are than the more effective potential barrier between Controlling Source, the leakage of single grid up and down, and the double grids MOSFET of ultra-thin Si layer has good short-channel effect rejection.In order to reduce the technology difficulty of horizontal double grid, the vertical double gate structure has been proposed, i.e. the FinFET structure.If, promptly become three gate MOSFET structures with the reduced thickness of FinFET top grid oxide layer thickness to the side grid oxide layer.It is looser than double-gated devices to the requirement of Si film the ratio of width to height to exhaust three gate MOSFETs entirely.Side grid in three grid are deep into oxygen buried layer, promptly form the Pi gate MOSFET.The side gate part that gos deep into oxygen buried layer makes the Pi gate MOSFET can effectively control the raceway groove electric field, and shielding drain terminal electric field is to the influence of raceway groove.When the side grid laterally stretch into an oxygen buried layer part again, the Ω grid have just been formed.If silicon layer is surrounded by grid fully, just formed fense MOSFET.Because the grid of fense MOSFET have surrounded silicon fiml fully, grid are strengthened the control ability of raceway groove, further strengthen the inhibition ability and the current driving ability of short-channel effect, become the device architecture that preparation high integration, low pressure, low power consumption memories and CMOS integrated circuit have prospect most.
But, enclose the threshold voltage shift of gate device and leakage and cause potential barrier and reduce effect also relatively significantly when the characteristic size of device during less than 100 nanometers.In order to suppress short-channel effect, can realize by increasing channel doping concentration.But high channel doping can cause carrier mobility to reduce, and then the device drive ability is degenerated.
Summary of the invention
The purpose of this invention is to provide a kind of vertical fense MOSFET device, its grid-control ability is stronger, can effectively suppress the degeneration of short-channel effect and subthreshold characteristic, improves the driving force of device.
Another object of the present invention is to provide the manufacture method of above-mentioned vertical fense MOSFET device, can be used in the making of inferior 50nm MOSFET, and the device architecture of making is accurate, controlled, and consistency of performance is good.
In order to achieve the above object, the present invention is achieved by the following technical solutions:
1, a kind of vertical fense MOSFET device, comprise: Semiconductor substrate, be vertically set on the columniform channel region on the Semiconductor substrate, channel region cylindrical is outside equipped with the dielectric layer that the cross section is the ring-type of flute profile, described slit opening upwards, be provided with the grid conductive layer of ring-type in the groove of described dielectric layer, the groove of described dielectric layer is outside equipped with the leakage conductive layer of ring-type, the groove outer bottom of described dielectric layer contacts with described Semiconductor substrate, described channel region is provided with the source conductive layer, its cylindrical upper section is mixed n+ impurity as end n+ district, source, the semiconductor substrate region that contacts bottom leaking conductive layer is mixed n+ impurity as drain terminal n+ district, it is characterized in that the cylindrical central part of described channel region is provided with asymmetric Halo doped structure p+ district.
The further characteristics of technique scheme are:
Mix n-impurity between the cylindrical upper section of described asymmetric Halo doped structure p+ district and described channel region, also mix n-impurity, form the LDD doped structure with the semiconductor substrate region that the groove outer bottom of described dielectric layer contacts.
Described semiconductor substrate materials is selected from the binary or the ternary semiconductor of Si, Ge, SiGe, GaAs or II-VI, III-V, IV-IV family.
2, the manufacture method of above-mentioned vertical fense MOS device is characterized in that, may further comprise the steps:
(1) at superficial growth first silicon oxide layer of Semiconductor substrate as separator, at the first silicon oxide layer deposit, first silicon nitride layer, make columniform first resist layer on first silicon nitride layer surface; Then, under the sheltering of first resist layer, from top to bottom etching first silicon nitride layer, first silicon oxide layer, Semiconductor substrate successively form columniform semi-conductive channel region, then, remove first resist layer;
(2) at lateral growth second silicon oxide layer of semiconductor substrate surface and channel region, join with first silicon oxide layer; Again at surface deposition first polysilicon layer of second silicon oxide layer, first polysilicon layer exceeds and covers first silicon nitride layer; Planarization first polysilicon layer, oppositely etching first polysilicon layer exposes to second silicon oxide layer of first silicon nitride layer surface and channel region side; Again on first polysilicon layer and the first silicon nitride layer surface, deposit the 3rd silicon oxide layer and deposit second silicon nitride layer successively at the second silicon nitride layer surface deposition the 4th silicon oxide layer, exceed and cover second silicon nitride layer; Then, the top area of second silicon nitride layer is exposed on planarization the 4th silicon oxide layer surface;
(3) the 4th silicon oxide layer that exposes of first etching, etching second silicon nitride layer exposes fully up to the 3rd silicon oxide layer top again, and etching the 3rd silicon oxide layer then, the 3rd silicon oxide layer up to the channel region top etch away to extremely;
(4) at the 3rd silicon oxide layer surface deposition the 3rd silicon nitride layer, join with first silicon nitride layer, after the planarization, over against the top of channel region, make columniform second resist layer, the columniform diameter of second resist layer is greater than the columniform diameter of channel region; By sheltering of second resist layer, etch away other parts of the 3rd silicon nitride layer, form the first silicon nitride side wall, remove second resist layer then;
(5) with first silicon nitride layer and the first silicon nitride side wall for sheltering, etch away the 3rd unnecessary silicon oxide layer of sidewall, first polysilicon layer and second silicon oxide layer, up to exposing Semiconductor substrate; Then, on Semiconductor substrate, reserve annular space, at peripheral the 3rd resist layer of making annular of annular space; Under the shielding of the 3rd resist layer, carry out n-impurity at the above-mentioned annular space place of Semiconductor substrate and inject, form drain terminal LDD doped structure n-district;
(6) remove the 3rd resist layer,, exceed first silicon nitride layer and the first silicon nitride side wall at semiconductor substrate surface deposit the 4th silicon oxide layer; Planarization the 4th silicon oxide layer, oppositely etching the 4th silicon oxide layer exposes until first silicon nitride layer and the first silicon nitride side wall again; Deposit tetrazotization silicon layer again, and on the tetrazotization silicon layer,, make columniform the 4th resist layer over against the top of channel region, the columniform diameter of the 4th resist layer equals the peripheral diameter of above-mentioned annular space; Then, for sheltering, etching tetrazotization silicon layer forms the second silicon nitride side wall, and removes the 4th resist layer with the 4th resist layer;
(7) with first silicon nitride layer, the first silicon nitride side wall and the second silicon nitride side wall for sheltering, etching the 4th silicon oxide layer up to exposing Semiconductor substrate, carries out n+ impurity and injects on the Semiconductor substrate of exposing, form the drain region; Again at semiconductor substrate surface deposit second polysilicon layer, exceed and cover first silicon nitride layer, the first silicon nitride side wall, the second silicon nitride side wall; Behind planarization second polysilicon layer, and reverse etching, expose up to first silicon nitride layer, the first silicon nitride side wall and the second silicon nitride side wall; Then, etch away first silicon nitride layer, the first silicon nitride side wall and the second silicon nitride side wall;
(8) on second polysilicon layer, make the 5th resist layer, inject p+ impurity, n-impurity, n+ impurity at the channel region top according to this, form the asymmetric Halo doped structure of source end p+ district, end LDD doped structure n-district, source and end n+ district, source respectively; Then, remove the 5th resist layer, and carry out annealing in process;
(9) finish annealing in process after, in entire upper surface, deposit the 3rd polysilicon layer and the 5th silicon nitride layer successively on the 5th silicon nitride layer, are made the 6th resist layer over against end n+ district, source and drain terminal n+ district then; Shelter down at the 6th resist layer, etching the 5th silicon nitride layer and the 3rd polysilicon layer are divided into two parts with the 3rd polysilicon layer that remains successively, respectively as source conductive layer and leakage conductive layer; Remove the 6th resist layer, again at source conductive layer and leakage conductance electricity laminar surface deposit the 5th silicon oxide layer, the 5th silicon oxide layer is higher than and covers the 5th silicon nitride layer;
(10) on the 5th silicon oxide layer, make the 7th resist layer over against the inboard and the outside of first polysilicon layer with positive photoresist, under the sheltering of the 7th resist layer, etching the 5th silicon oxide layer and the 3rd silicon oxide layer successively are up to exposing first polysilicon layer; Remove the 7th resist layer,, exceed the 5th silicon nitride layer at the first polysilicon layer surface deposition the 4th polysilicon layer; Then, expose until the 5th silicon nitride layer on its surface of planarization;
(11) at the 5th silicon nitride layer and the 4th polysilicon layer surface deposition the 6th silicon oxide layer; Then, on the 6th silicon oxide layer, the source conductive layer and leak conductive layer over against local location etching contact hole respectively, up to the source conductive layer with leak conductive layer and expose, in contact hole, inject polysilicon respectively and form source electrode, drain electrode; On the 6th silicon oxide layer, the local location etching contact hole over against the 4th polysilicon layer exposes up to the 4th polysilicon layer, injects polysilicon and form gate electrode in contact hole.
The vertical fense MOS device with asymmetric Halo doped structure that the present invention proposes has been realized the fully encirclement of grid to raceway groove, and the grid-control ability is stronger, effectively suppresses the degeneration of short-channel effect and subthreshold characteristic; The LDD doped structure can effectively suppress the highfield of drain terminal, helps reducing hot carrier's effect; End asymmetric Halo doped structure in source produces a peak electric field on the Halo border, and charge carrier is quickened in advance, passes raceway groove at faster speed, and the driving force of device is improved; Asymmetric Halo structure produces an electromotive force step on minimal surface gesture the right, produces certain shielding action to leaking the pressure variation, and the influence that the minimal surface gesture is leaked pressure is weakened, and further suppresses leakage and causes potential barrier reduction effect; Perpendicular to the device architecture of substrate, make channel length not be subject to the photoetching level, can realize littler characteristic size.
Description of drawings
Fig. 1 is growth regulation one silica layer, deposit first silicon nitride layer and make the processing step schematic diagram of first resist layer on Semiconductor substrate;
Fig. 2 is the semiconductor channel schematic diagram;
Fig. 3 is the deposit schematic diagram of the grid oxide layer moulding and first polysilicon layer;
Fig. 4 is the 3rd silicon oxide layer, second silicon nitride layer, the 4th silicon oxide layer shaping schematic view;
Fig. 5 be the 3rd silicon oxide layer, second silicon nitride layer, the 4th silicon oxide layer anti-carve the erosion schematic diagram;
Fig. 6 is the first silicon nitride side wall shaping schematic view;
Fig. 7 is that drain terminal LDD doped structure n-district ion injects schematic diagram;
Fig. 8 is the 4th silicon oxide layer deposit shaping schematic view;
Fig. 9 is that drain terminal n+ district ion injects schematic diagram;
Figure 10 is a drain terminal n+ district ion injection moulding schematic diagram;
Figure 11 is that the asymmetric Halo doped structure of source end p+ district, end LDD doped structure n-district, source and end n+ district, source ion inject schematic diagram;
Figure 12 is the 3rd polysilicon layer and the 5th silicon nitride layer deposit and the 6th resist layer making schematic diagram;
Figure 13 is source conductive layer and leakage conductance electricity formable layer and the 5th silicon oxide layer deposit schematic diagram;
Figure 14 is the grid conductive layer shaping schematic view;
Figure 15 a is source electrode, drain electrode shaping schematic view;
Figure 15 b is the gate electrode shaping schematic view;
Figure 15 c is the vertical view of Figure 15 b.
Embodiment
Below in conjunction with description of drawings and embodiment the present invention is described in further detail.
With reference to Figure 15 a, 15b, 15c, vertical fense MOSFET device, its Semiconductor substrate, semiconductor substrate materials are selected from the binary or the ternary semiconductor of Si, Ge, SiGe, GaAs or II-VI, III-V, IV-IV family, present embodiment select P type semiconductor substrate 1 for use.Vertically disposed columniform channel region on P type semiconductor substrate 1, channel region cylindrical are outside equipped with the dielectric layer that the cross section is the ring-type of flute profile, and this slit opening upwards.Be provided with the grid conductive layer of ring-type in the groove of dielectric layer, grid conductive layer is drawn by two columned gate electrodes 27; The groove arranged outside of dielectric layer has the leakage conductive layer of ring-type, leaks conductive layer and draws by two columned drain electrodes 26; The groove outer bottom of dielectric layer contacts with P type semiconductor substrate 1.Channel region is provided with the source conductive layer, and the source conductive layer is drawn by columned source electrode 25; The cylindrical upper section of channel region is mixed n+ impurity as end n+ district, source, and the semiconductor substrate region that contacts bottom leaking conductive layer is mixed n+ impurity as drain terminal n+ district, and the cylindrical central part of channel region is provided with asymmetric Halo doped structure p+ district; Mix n-impurity between the cylindrical upper section of asymmetric Halo doped structure p+ district and channel region, also mix n-impurity, form the LDD doped structure with the semiconductor substrate region that the groove outer bottom of dielectric layer contacts.
The manufacture method of vertical fense MOSFET device of the present invention specifically may further comprise the steps:
With reference to Fig. 1, at first silicon oxide layer 2 of Film by Thermal Oxidation one thickness between 10nm～30nm of P type semiconductor substrate 1 as separator, again on first silicon oxide layer 2 by first silicon nitride layer 3 of low-pressure chemical vapor phase deposition technology (LPCVD) deposit one layer thickness between 20nm～60nm; Then, make columniform first resist layer 4 on first silicon nitride layer, 3 surfaces with positive photoresist.
With reference to Fig. 2, under the sheltering of first resist layer 4, adopt reactive ion etching technology (RIE), from top to bottom etching first silicon nitride layer 3, first silicon oxide layer 2, Semiconductor substrate 1 successively, form columniform semi-conductive channel region 5, then, remove first resist layer 4.
With reference to Fig. 3, pass through second silicon oxide layer of thermal oxide growth one thickness between 2nm～10nm in the side of substrate 1 surface and channel region 5, join with first silicon oxide layer; Exceed and cover first silicon nitride layer 3 at surface deposition first polysilicon layer 6, the first polysilicon layers 6 of second silicon oxide layer by the LPCVD technology again; By chemical-mechanical planarization technology (CMP) planarization first polysilicon layer 6, oppositely second silicon oxide layer of etching first polysilicon layer 6 to first silicon nitride layers, 3 surfaces and channel region 5 sides exposes again; Once more, on first polysilicon layer 6 and first silicon nitride layer, 3 surfaces,,, exceed and cover second silicon nitride layer 8 at second silicon nitride layer, 8 surface depositions the 4th silicon oxide layer 9 successively by LPCVD deposition techniques the 3rd silicon oxide layer 7 and second silicon nitride layer 8; Then, by CMP technology planarization the 4th silicon oxide layer 9 surfaces, expose the top area of second silicon nitride layer 8, as shown in Figure 4.
With reference to Fig. 5, by the RIE technology, the 4th silicon oxide layer 9 that first etching exposes, etching second silicon nitride layer 8 again, expose fully up to the 3rd silicon oxide layer 7 tops, etching the 3rd silicon oxide layer 7 then, the 3rd silicon oxide layer 7 up to channel region 5 tops etch away to extremely.At this moment, the 3rd silicon oxide layer 7 remained on surface have second silicon nitride layer 8 of ring-type.
With reference to Fig. 6, at the 3rd silicon oxide layer 7 surface depositions the 3rd silicon nitride layer, join with first silicon nitride layer 3, after the planarization, top over against channel region 5, make columniform second resist layer with positive photoresist, the columniform diameter of second resist layer is greater than the columniform diameter of channel region 5; By sheltering of second resist layer, utilize the RIE lithographic technique, etch away other parts of the 3rd silicon nitride layer, form the first silicon nitride side wall 10, remove second resist layer then.
For sheltering, etch away the 3rd unnecessary silicon oxide layer 7 of sidewall and first polysilicon layer 6 and second silicon oxide layer, with first silicon nitride layer 3 and the first silicon nitride side wall 10 up to exposing P type semiconductor substrate 1; Then, on P type semiconductor substrate 1, reserve annular space, with three resist layer 11 of positive photoresist in the peripheral making annular of annular space, under the shielding of the 3rd resist layer 11, carrying out n-impurity at the above-mentioned annular space place of P type semiconductor substrate 1 with the arsenic impurities material injects, form drain terminal LDD doped structure n-district, as shown in Figure 7.
With reference to Fig. 8, after finishing n-impurity and injecting, remove the 3rd resist layer 11, at P type semiconductor substrate 1 surface deposition the 4th silicon oxide layer 12, exceed first silicon nitride layer 3 and the first silicon nitride side wall 10 by the LPCVD technology; Then utilize CMP technology planarization the 4th silicon oxide layer 12, oppositely etching the 4th silicon oxide layer 12 exposes until first silicon nitride layer 3 and the first silicon nitride side wall 10 again.
Then, to whole surface deposition tetrazotization silicon layer, on the tetrazotization silicon layer, over against the top of channel region 5, make columniform the 4th resist layer with positive photoresist, the columniform diameter of the 4th resist layer equals the peripheral diameter of above-mentioned annular space; For sheltering, etching tetrazotization silicon layer forms the second silicon nitride side wall 13, then, removes the 4th resist layer with the 4th resist layer.
With first silicon nitride layer 3, the first silicon nitride side wall 10 and the second silicon nitride side wall 13 for sheltering, etching the 4th silicon oxide layer 12 up to exposing P type semiconductor substrate 1, carries out n+ impurity with the arsenic impurities material and injects on the P type semiconductor substrate 1 that exposes, form drain terminal n+ district 14, as shown in Figure 9.
With reference to Figure 10, after finishing n+ impurity and injecting,,, exceed and cover first silicon nitride layer 3, the first silicon nitride side wall 10, the second silicon nitride side wall 13 at P type semiconductor substrate 1 surface deposition second polysilicon layer 15 by the LPCVD technology; Behind planarization second polysilicon layer 15 surfaces, carry out reverse etching, expose up to first silicon nitride layer 3, the first silicon nitride side wall 10 and the second silicon nitride side wall 13; Then, etch away first silicon nitride layer 3, the first silicon nitride side wall 10 and the second silicon nitride side wall 13.
With reference to Figure 11, on second polysilicon layer 15, make the 5th resist layer 16 with positive photoresist, utilize ion implantation technique to inject high concentration boron, low-concentration arsenic and High Concentration of Arsenic impurity according to this at channel region 5 tops, form the asymmetric Halo doped structure of source end p+ district, end LDD doped structure n-district, source and end n+ district, source respectively; Then, remove the 5th resist layer 16, and under 900-1000 ℃ high temperature, carry out short annealing and handle.
With reference to Figure 12, after finishing annealing in process, in entire upper surface, utilize the LPCVD technology, successively deposit the 3rd polysilicon layer 17 and the 5th silicon nitride layer 18, then on the 5th silicon nitride layer 18, make the 6th resist layer 19 over against end n+ district, source and drain terminal n+ district, shelter down at the 6th resist layer 19, successively etching the 5th silicon nitride layer 18 and the 3rd polysilicon layer 17, the 3rd polysilicon layer 17 that remains is divided into two parts, respectively as source conductive layer 20a and leakage conductive layer 20b; Remove the 6th resist layer 19, again at source conductive layer 20a with leak conductive layer 20b surface and utilize LPCVD deposition techniques the 5th silicon oxide layer 21, the five silicon oxide layers 21 to be higher than and cover the 5th silicon nitride layer 18, as shown in figure 13.
With reference to Figure 13, on the 5th silicon oxide layer 21, make the 7th resist layer 22 over against the inboard and the outside of first polysilicon layer 6 with positive photoresist, under the sheltering of the 7th resist layer 22, etching the 5th silicon oxide layer 21 and the 3rd silicon oxide layer 7 successively are up to exposing first polysilicon layer 6; Remove the 7th resist layer 22 again, and,, exceed the 5th silicon nitride layer 18, the four polysilicon layers 23 as grid conductive layer at first polysilicon layer, 6 surface depositions the 4th polysilicon layer 23 by the LPCVD technology; Then, planarized surface exposes until the 5th silicon nitride layer 18, as shown in figure 14.
With reference to Figure 15 a, 15b, 15c, at the 5th silicon nitride layer 18 and the 4th polysilicon layer 23 surface depositions the 6th silicon oxide layer 24.On the 6th silicon oxide layer 24, source conductive layer 20a and leak conductive layer 20b over against local location etching contact hole respectively, up to source conductive layer 20a with leak conductive layer 20b and expose, in contact hole, inject polysilicon respectively and form source electrode 25, drain electrode 26; On the 6th silicon oxide layer 24, the local location etching contact hole over against the 4th polysilicon layer 23 exposes up to the 4th polysilicon layer 23, injects polysilicon and form gate electrode 27 in contact hole.The contact hole of formation source electrode 25, drain electrode 26, gate electrode 27 staggers when punching as far as possible, with convenient lead-in wire.
Resist layer used in the present embodiment all adopts positive photoresist, the big advantage of one is the influence that the photoresist unexposed area is not subjected to developer solution, thereby make the figure of transferring to the superfine lines on the photoresist in the photoetching process can keep good live width and shape, have good live width resolution.Adopt this dry etching technology of reactive ion etching RIE, physical bombardment and chemical reaction double action etching by active ion have the advantage of ise and plasma etching, have the good advantage of anisotropy and selectivity simultaneously concurrently.
The manufacturing technology of the resist layer that adopts in of the present invention, the removal technology of resist layer, the thermal oxide growth technology of silicon oxide layer, the low-pressure chemical vapor phase deposition technology (LPCVP) of silicon oxide layer, silicon nitride layer, polysilicon layer and to the reactive ion etching technology (RIE) of silicon oxide layer, silicon nitride layer, polysilicon layer, chemical-mechanical planarization technology (CMP), semiconductor doping (ion injection), semiconductor annealing technology are conventional microelectronics manufacturing technology.
The manufacturing technology of resist layer can adopt deep UV or extreme ultraviolet linear light lithography to form; The erosion removal technology of resist layer can adopt dry plasma etch or chemical etching technology, specifically can be referring to " the removing the new dry process of photoresist " of periodical " vacuum " phase Jiang Jian compiling in 2003 the 1st.The thermal oxide growth technology of silicon oxide layer is carried out under 900-1200 ℃ oxygen atmosphere; Silicon oxide layer low-pressure chemical vapor phase deposition technology (LPCVD), silane and oxygen are reacted under 300-600 ℃ condition, specifically can be referring to " the CVD of SiO of 1996 the 6th curly hair tables of periodical " ADVANCED MATERIALS For OPTICS and ELECTRONICS "
2And Related Materials:an Overview ", author: Andrew R.Barron.Silicon nitride layer low-pressure chemical vapor phase deposition technology (LPCVD), employing be high-purity Si H
2Cl
2And NH
3Under 700-850 ℃, carry out; The low-pressure chemical vapor phase deposition technology (LPCVD) of polysilicon layer adopts dilute Si H
4Under 570-620 ℃, carry out; Specifically can be referring to periodical: " LPCVD growth structure layer polysilicon and the technology of mixing the P polysilicon " that " functional material and device journal " the 14th volume the 2nd phase (in April, 2008) is delivered, author: Wang Lifeng, Jia Shixing, Lu Le, Jiang Lili; " LPCVD prepares silicon nitride film technology " that " integrated circuit communication " the 26th volume the 2nd phase (in June, 2008) is delivered, author: simple Chong Xi.
The reactive ion etching technology of silicon oxide layer (RIE) technology is carried out under fluorine base gas atmosphere; The reactive ion etching technology of silicon nitride layer (RIE) technology, at free fluorine ion (as SF
6Or CF
4/ O
2) etching under the environment; The reactive ion etching technology of polysilicon layer (RIE) carries out in chlorine gas environment; Specifically can be referring to periodical: " reactive ion etching of silicon dioxide " that " electronics industry special equipment " (total the 126th phase in 2005) delivers, author: Hao Huijuan, Zhang Yulin, Lu Wenjuan; " research of reactive ion etching technology " that the 31st the 6th phase of volume of " semiconductor technology " (in June, 2006) delivers, author: come five-pointed star, Liao Guanglan, Shi Tielin, Yang Shuzi; " the reactive ion etching process parameter study of silicon " that " Nanjing Normal University's journal (engineering version) " the 6th volume the 3rd phase (in September, 2006) is delivered, author: Ge Yixian, Wang Ming, Rong Hua.Chemical-mechanical planarization technology (CMP), the specifically " SiO between the ULSI circuit layer that delivers referring to periodical " micro-nano electronic technology " o. 11th in 2006
2CMP of Dielectric technology and polishing fluid ", author: Sun Ming, Liu Yuling, Jia Yingqian, Liu Bo, Liu Changyu.
Certainly, also can use other similar growths, deposit, etching, planarization, semiconductor doping, semiconductor annealing technology, reach according to above-mentioned steps and realize purpose of the present invention.
Claims (4)
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102593177A (en) * | 2012-02-16 | 2012-07-18 | 清华大学 | Tunneling transistor with horizontal quasi coaxial cable structure and forming method thereof |
| CN102110648B (en) * | 2009-12-24 | 2013-05-01 | 中国科学院微电子研究所 | Method for preparing bulk silicon gate-all-around metal semiconductor field effect transistor |
| CN103887178A (en) * | 2014-03-27 | 2014-06-25 | 西安交通大学 | A kind of manufacturing method of strained vertical MOS device |
| CN104143505A (en) * | 2013-05-10 | 2014-11-12 | 台湾积体电路制造股份有限公司 | self-aligned surround structure |
| US9929257B2 (en) | 2015-03-13 | 2018-03-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices having a semiconductor material that is semimetal in bulk and methods of forming the same |
| US9935198B2 (en) | 2013-02-08 | 2018-04-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for inducing strain in vertical semiconductor columns |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102110648B (en) * | 2009-12-24 | 2013-05-01 | 中国科学院微电子研究所 | Method for preparing bulk silicon gate-all-around metal semiconductor field effect transistor |
| CN102593177A (en) * | 2012-02-16 | 2012-07-18 | 清华大学 | Tunneling transistor with horizontal quasi coaxial cable structure and forming method thereof |
| CN102593177B (en) * | 2012-02-16 | 2014-06-11 | 清华大学 | Tunneling transistor with horizontal quasi coaxial cable structure and forming method thereof |
| US9935198B2 (en) | 2013-02-08 | 2018-04-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for inducing strain in vertical semiconductor columns |
| CN104143505A (en) * | 2013-05-10 | 2014-11-12 | 台湾积体电路制造股份有限公司 | self-aligned surround structure |
| CN104143505B (en) * | 2013-05-10 | 2017-04-12 | 台湾积体电路制造股份有限公司 | Self-aligned wrapped-around structure |
| CN103887178A (en) * | 2014-03-27 | 2014-06-25 | 西安交通大学 | A kind of manufacturing method of strained vertical MOS device |
| US9929257B2 (en) | 2015-03-13 | 2018-03-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices having a semiconductor material that is semimetal in bulk and methods of forming the same |
| US10461179B2 (en) | 2015-03-13 | 2019-10-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices having a semiconductor material that is semimetal in bulk and methods of forming the same |
| US10818780B2 (en) | 2015-03-13 | 2020-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices having a semiconductor material that is semimetal in bulk and methods of forming the same |
| US11302804B2 (en) | 2015-03-13 | 2022-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices having a semiconductor material that is semimetal in bulk and methods of forming the same |
| US12148816B2 (en) | 2015-03-13 | 2024-11-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices having a semiconductor material that is semimetal in bulk and methods of forming the same |
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