CN101483154B - Manufacturing process for gate lateral wall of dual gate oxide device - Google Patents
Manufacturing process for gate lateral wall of dual gate oxide device Download PDFInfo
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- CN101483154B CN101483154B CN2008100323464A CN200810032346A CN101483154B CN 101483154 B CN101483154 B CN 101483154B CN 2008100323464 A CN2008100323464 A CN 2008100323464A CN 200810032346 A CN200810032346 A CN 200810032346A CN 101483154 B CN101483154 B CN 101483154B
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Abstract
The present invention provides a gate side wall manufacture method of a dual-gate oxide device comprising a thick gate oxide Metal-Oxide-Semiconductor (MOS) tube and a thin Metal-Oxide-Semiconductor (MOS) tube. The gate side wall comprises a thick gate side wall and a thin gate side wall respectively made on both sides of the thick and thin gate oxide gates, wherein the thick gate oxide side wallincludes an internal offset sidewall and an external offset side wall. In the prior art the gate side wall of the dual-gate oxide device does not use the internal offset side wall, causes a larger leakage current of the thick gate oxide MOS tube and a larger capacitance between the gate and a source drain and leads the electrical behavior deterioration of the dual-gate oxide device. The inventionfirstly deposits a first side wall medium layer and removes the thin gate oxide corresponding first side wall medium layer of an active region; then forms the internal offset side wall by the dry etching; afterwards performs a light doping leakage injection process; finally deposits a second side wall medium layer and forms outside walls of the thin gate oxide side wall and the thick gate oxide side wall by the dry etching. The invention can reduce the leakage current of the thick gate oxide MOS tube and the capacitance between the gate and the source drain, and improve the electrical behavior of the dual-gate oxide device.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of grid curb wall manufacture method of Dual Gate Oxide device.
Background technology
Some electronic product all has higher requirement to power consumption and speed, has only the Dual Gate Oxide device could satisfy the dual requirements of those electronic products to power consumption and speed.The Dual Gate Oxide device not only has the thick grid oxygen mos field effect transistor (MOSFET abbreviates metal-oxide-semiconductor as) of low-power consumption, also has the thin faster grid oxygen metal-oxide-semiconductor of reaction speed.Be arranged on the grid both sides and can effectively reduce electric capacity between leakage current and grid and source-drain electrode as the bias internal side wall (offset spacer) of grid curb wall part, it has been widely used in the field of semiconductor fabrication of deep-submicron.But in the Dual Gate Oxide device, approach the reaction speed of grid oxygen metal-oxide-semiconductor and simplify technology for guaranteeing, it does not use the bias internal side wall in grid curb wall, it only forms grid curb wall by deposition side wall medium layer (being generally silicon nitride) and by etching technics, thereby cause the leakage current of thick grid oxygen metal-oxide-semiconductor and the electric capacity between grid and source-drain electrode all bigger, and make the electrical property deterioration of this Dual Gate Oxide device.
Therefore, the grid curb wall manufacture method how a kind of Dual Gate Oxide device to be provided is with the leakage current that reduces thick grid oxygen metal-oxide-semiconductor and the electric capacity between grid and source-drain electrode thereof, and improves the electrical property of Dual Gate Oxide device, become the technical problem that industry needs to be resolved hurrily.
Summary of the invention
The object of the present invention is to provide a kind of grid curb wall manufacture method of Dual Gate Oxide device, the leakage current of thick grid oxygen metal-oxide-semiconductor and the electric capacity between grid and source-drain electrode thereof can be reduced greatly by described grid curb wall manufacture method, and the electrical property of Dual Gate Oxide device can be effectively improved.
The object of the present invention is achieved like this: a kind of grid curb wall manufacture method of Dual Gate Oxide device, this Dual Gate Oxide device has thick grid oxygen metal-oxide-semiconductor and thin grid oxygen metal-oxide-semiconductor, this grid curb wall comprises thick grid oxygen side wall and thin grid oxygen side wall, it is produced in thick grid oxygen grid and thin grid oxygen grid both sides, wherein, this thick grid oxygen side wall comprises bias internal side wall and external wall, and this grid curb wall manufacture method may further comprise the steps: a, deposition first side wall medium layer; B, coating photoresist also make the active area figure that approaches grid oxygen metal-oxide-semiconductor correspondence by lithography; C, remove first side wall medium layer do not covered by wet-etching technology by photoresist; D, remove photoresist and recoat the cloth photoresist, and make the active area figure of thick grid oxygen metal-oxide-semiconductor correspondence by lithography; E, form the bias internal side wall by dry etch process; F, remove photoresist and carry out the lightly doped drain injection technology; G, deposition second side wall medium layer also form the external wall of thin grid oxygen side wall and thick grid oxygen side wall by dry etch process.
In the grid curb wall manufacture method of above-mentioned Dual Gate Oxide device, the thickness range of the thick grating oxide layer of thick grid oxygen metal-oxide-semiconductor is 16 to 18 dusts.
In the grid curb wall manufacture method of above-mentioned Dual Gate Oxide device, the thickness range of the thin gate oxide of thin grid oxygen metal-oxide-semiconductor is 10 to 12 dusts.
In the grid curb wall manufacture method of above-mentioned Dual Gate Oxide device, in step c, the etching liquid of this wet-etching technology is a phosphoric acid solution.
In the grid curb wall manufacture method of above-mentioned Dual Gate Oxide device, this first side wall medium layer is a silicon nitride.
In the grid curb wall manufacture method of above-mentioned Dual Gate Oxide device, in step a, the first side wall medium layer thickness range that is deposited is 60 to 130 dusts.
In the grid curb wall manufacture method of above-mentioned Dual Gate Oxide device, this second side wall medium layer comprises the silicon nitride layer and the silicon oxide layer of stacked on top of one another.
In the grid curb wall manufacture method of above-mentioned Dual Gate Oxide device, in step g, the thickness range of the silicon oxide layer that is deposited is 100 to 200 dusts, and the thickness range of silicon nitride layer is 500 to 700 dusts.
Do not cause the leakage current of thick grid oxygen metal-oxide-semiconductor and grid all to be compared more greatly with not having the bias internal side wall in the grid curb wall in the prior art with the electric capacity between source-drain electrode, the grid curb wall manufacture method of Dual Gate Oxide device of the present invention deposits first side wall medium layer earlier and removes first side wall medium layer of the active area of thin grid oxygen metal-oxide-semiconductor correspondence, form the bias internal side wall by dry etching again, carry out the lightly doped drain injection technology then, deposit second side wall medium layer at last and form the external wall of thin grid oxygen side wall and thick grid oxygen side wall by dry etching, so can under the prerequisite that does not influence thin grid oxygen metal-oxide-semiconductor reaction speed, greatly reduce the leakage current of thick grid oxygen metal-oxide-semiconductor and the electric capacity between grid and source-drain electrode thereof, and can effectively improve the electrical property of Dual Gate Oxide device.
Description of drawings
The grid curb wall manufacture method of Dual Gate Oxide device of the present invention is provided by following embodiment and accompanying drawing.
Fig. 1 is the cutaway view that carries out preceding this Dual Gate Oxide device of grid curb wall manufacture method of Dual Gate Oxide device of the present invention;
Fig. 2 is the flow chart of the grid curb wall manufacture method of Dual Gate Oxide device of the present invention;
Fig. 3 to Fig. 9 finishes among Fig. 2 the cutaway view of Dual Gate Oxide device behind the step S20 to S26.
Embodiment
Below will the grid curb wall manufacture method of Dual Gate Oxide device of the present invention be described in further detail.
Dual Gate Oxide device described in the present invention has thick grid oxygen metal-oxide-semiconductor and thin grid oxygen metal-oxide-semiconductor, described grid curb wall comprises thick grid oxygen side wall and thin grid oxygen side wall, it is produced in thick grid oxygen grid and thin grid oxygen grid both sides, and wherein, described thick grid oxygen side wall comprises bias internal side wall and external wall.
Referring to Fig. 1, it has shown the cutaway view of the preceding described Dual Gate Oxide device of grid curb wall manufacture method that carries out Dual Gate Oxide device of the present invention, as shown in the figure, the thick grid oxygen grid 10 and the thin grid oxygen grid 11 of thick grid oxygen metal-oxide-semiconductor and thin grid oxygen metal-oxide-semiconductor correspondence are deposited on the silicon substrate 1, the active area of both correspondences is isolated by fleet plough groove isolation structure 12, described thick grid oxygen grid 10 and 1 of silicon substrate have thick grating oxide layer 13, and described thin grid oxygen grid 11 and 1 of silicon substrate have thin gate oxide 14.In the present embodiment, the thickness range of thick grating oxide layer 13 is 16 to 18 dusts, and the thickness range of thin gate oxide 14 is 10 to 12 dusts.
Referring to Fig. 2, the grid curb wall manufacture method of Dual Gate Oxide device of the present invention is at first carried out step S20, deposits first side wall medium layer.In the present embodiment, described first side wall medium layer is a silicon nitride, and the thickness range of the silicon nitride of this step deposition is 60 to 130 dusts.
Referring to Fig. 3, in conjunction with ginseng Fig. 1, Fig. 3 has shown the cutaway view of Dual Gate Oxide device behind the completing steps S20, and described as shown in the figure side wall medium layer 15 is deposited on the silicon substrate 1 and covers thick grid oxygen grid 10, thin grid oxygen grid 11 and fleet plough groove isolation structure 12.
Then continue step S21, the coating photoresist also makes the active area figure that approaches grid oxygen metal-oxide-semiconductor correspondence by lithography.In the present embodiment, this step has also made half zone near the active area of thin grid oxygen metal-oxide-semiconductor correspondence of the fleet plough groove isolation structure 12 among Fig. 1 by lithography.
Referring to Fig. 4, in conjunction with ginseng Fig. 1 and Fig. 3, Fig. 4 has shown the cutaway view of Dual Gate Oxide device behind the completing steps S21, as shown in the figure, described photoresist 2 covers on the active area of thick grid oxygen metal-oxide-semiconductor correspondence, and has covered fleet plough groove isolation structure 12 half zone near thick grid oxygen metal-oxide-semiconductor active area.
Then continue step S22, remove first side wall medium layer of not covered by wet-etching technology by photoresist.In the present embodiment, the etching liquid of described wet-etching technology is a phosphoric acid solution.
Referring to Fig. 5, in conjunction with ginseng Fig. 4, Fig. 5 has shown the cutaway view of Dual Gate Oxide device behind the completing steps S22, as shown in the figure, first side wall medium layer 15 on the active area of thin grid oxygen metal-oxide-semiconductor correspondence is removed fully, and described fleet plough groove isolation structure 12 also is removed near first side wall medium layer 15 on half zone of thin grid oxygen metal-oxide-semiconductor active area.
Then continue step S23, remove photoresist and recoat the cloth photoresist, and make the active area figure of thick grid oxygen metal-oxide-semiconductor correspondence by lithography.In the present embodiment, this step has also made half zone near the active area of thick grid oxygen metal-oxide-semiconductor correspondence of the fleet plough groove isolation structure 12 among Fig. 1 by lithography.
Referring to Fig. 6, in conjunction with ginseng Fig. 5, Fig. 6 has shown the cutaway view of Dual Gate Oxide device behind the completing steps S23, as shown in the figure, described photoresist 2 covers on the active area of thin grid oxygen metal-oxide-semiconductor correspondence, and has covered fleet plough groove isolation structure 12 half zone near thin grid oxygen metal-oxide-semiconductor active area.
Then continue step S24, form the bias internal side wall by dry etch process.
Referring to Fig. 7, in conjunction with ginseng Fig. 6, Fig. 7 has shown the cutaway view of Dual Gate Oxide device behind the completing steps S24, as shown in the figure, is deposited on thick grid oxygen grid 10 both sides by the bias internal side wall 16 of ground floor side wall medium layer 15 etching gained.
Then continue step S25, remove photoresist and carry out the lightly doped drain injection technology.
Referring to Fig. 8, in conjunction with ginseng Fig. 7, Fig. 8 has shown the cutaway view of Dual Gate Oxide device behind the completing steps S25, and as shown in the figure, lightly doped drain structure 17 is created in the silicon substrate 1 and is arranged on bias internal side wall 16 both sides and thin grid oxygen grid 11 both sides.
Then continue step S26, deposit second side wall medium layer and form the external wall of thin grid oxygen side wall and thick grid oxygen side wall by dry etch process.In the present embodiment, described second side wall medium layer comprises the silicon nitride layer and the silicon oxide layer of stacked on top of one another, and the thickness range of the silicon oxide layer of this step deposition is 100 to 200 dusts, and the thickness range of silicon nitride layer is 500 to 700 dusts.
Referring to Fig. 9, in conjunction with ginseng Fig. 8, Fig. 9 has shown the cutaway view of Dual Gate Oxide device behind the completing steps S26, as shown in the figure, the external wall 19 of thick grid oxygen side wall is deposited on the silicon substrate 1 and is arranged on bias internal side wall 16 both sides, and thin grid oxygen side wall 20 is deposited on the silicon substrate 1 and is arranged on thin grid oxygen grid 11 both sides.
In sum, the grid curb wall manufacture method of Dual Gate Oxide device of the present invention is deposition first side wall medium layer earlier, cover by coating photoresist and photoetching active area afterwards thick grid oxygen metal-oxide-semiconductor correspondence, then by the not side wall medium layer removal in crested zone of wet-etching technology, the active area that will approach grid oxygen metal-oxide-semiconductor correspondence by coating photoresist and photoetching again covers afterwards, form the bias internal side wall in thin grid oxygen grid both sides by etching technics again, after finishing the lightly doped drain injection, deposit second side wall medium layer again and carry out the grid curb wall that dry etch process finally forms the Dual Gate Oxide device, so can under the prerequisite that does not influence thin grid oxygen metal-oxide-semiconductor reaction speed, greatly reduce the leakage current of thick grid oxygen metal-oxide-semiconductor and the electric capacity between grid and source-drain electrode thereof, and can effectively improve the electrical property of Dual Gate Oxide device.
Claims (8)
1. the grid curb wall manufacture method of a Dual Gate Oxide device, this Dual Gate Oxide device has thick grid oxygen metal-oxide-semiconductor and thin grid oxygen metal-oxide-semiconductor, this grid curb wall comprises thick grid oxygen side wall and thin grid oxygen side wall, it is produced in thick grid oxygen grid and thin grid oxygen grid both sides, this thick grid oxygen side wall comprises bias internal side wall and external wall, it is characterized in that this grid curb wall manufacture method may further comprise the steps: a, deposition first side wall medium layer; B, coating photoresist also make the active area figure that approaches grid oxygen metal-oxide-semiconductor correspondence by lithography; C, remove first side wall medium layer do not covered by wet-etching technology by photoresist; D, remove photoresist and recoat the cloth photoresist, and make the active area figure of thick grid oxygen metal-oxide-semiconductor correspondence by lithography; E, form the bias internal side wall by dry etch process; F, remove photoresist and carry out the lightly doped drain injection technology; G, deposition second side wall medium layer also form the external wall of thin grid oxygen side wall and thick grid oxygen side wall by dry etch process.
2. the grid curb wall manufacture method of Dual Gate Oxide device as claimed in claim 1 is characterized in that, the thickness range of the thick grating oxide layer of thick grid oxygen metal-oxide-semiconductor is 16 to 18 dusts.
3. the grid curb wall manufacture method of Dual Gate Oxide device as claimed in claim 1 is characterized in that, the thickness range of the thin gate oxide of thin grid oxygen metal-oxide-semiconductor is 10 to 12 dusts.
4. the grid curb wall manufacture method of Dual Gate Oxide device as claimed in claim 1 is characterized in that, in step c, the etching liquid of this wet-etching technology is a phosphoric acid solution.
5. the grid curb wall manufacture method of Dual Gate Oxide device as claimed in claim 1 is characterized in that, this first side wall medium layer is a silicon nitride.
6. the grid curb wall manufacture method of Dual Gate Oxide device as claimed in claim 1 is characterized in that, in step a, the first side wall medium layer thickness range that is deposited is 60 to 130 dusts.
7. the grid curb wall manufacture method of Dual Gate Oxide device as claimed in claim 1 is characterized in that, this second side wall medium layer comprises the silicon nitride layer and the silicon oxide layer of stacked on top of one another.
8. the grid curb wall manufacture method of Dual Gate Oxide device as claimed in claim 7 is characterized in that, in step g, the thickness range of the silicon oxide layer that is deposited is 100 to 200 dusts, and the thickness range of silicon nitride layer is 500 to 700 dusts.
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| CN2008100323464A CN101483154B (en) | 2008-01-07 | 2008-01-07 | Manufacturing process for gate lateral wall of dual gate oxide device |
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| JP5927017B2 (en) * | 2012-04-20 | 2016-05-25 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| CN104851777B (en) * | 2014-02-17 | 2017-12-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and preparation method thereof |
| CN109192703A (en) * | 2018-08-31 | 2019-01-11 | 上海华力微电子有限公司 | A kind of forming method and MOS device of bigrid side wall |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1225507A (en) * | 1998-02-05 | 1999-08-11 | 国际商业机器公司 | Manufacturing method of double gate oxide double work function CMOS |
| CN1540723A (en) * | 2003-10-30 | 2004-10-27 | 上海集成电路研发中心有限公司 | A method for preparing a nitrogen-containing double gate silicon oxide layer of a semiconductor device |
| CN1945851A (en) * | 2005-10-04 | 2007-04-11 | 台湾积体电路制造股份有限公司 | SONOS gate structure and its formation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1225507A (en) * | 1998-02-05 | 1999-08-11 | 国际商业机器公司 | Manufacturing method of double gate oxide double work function CMOS |
| CN1540723A (en) * | 2003-10-30 | 2004-10-27 | 上海集成电路研发中心有限公司 | A method for preparing a nitrogen-containing double gate silicon oxide layer of a semiconductor device |
| CN1945851A (en) * | 2005-10-04 | 2007-04-11 | 台湾积体电路制造股份有限公司 | SONOS gate structure and its formation method |
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Effective date of registration: 20111116 Address after: 201203 No. 18 Zhangjiang Road, Shanghai Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 No. 18 Zhangjiang Road, Shanghai Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |