CN101447177B - Display capable of actively adjusting driving voltage, voltage compensation circuit and driving method - Google Patents

Abstract

The present invention provides a display capable of actively adjusting a driving voltage, a voltage compensation circuit, and a driving method. The display comprises a display panel, a gate driving circuit, and a voltage selector. The display panel turns on pixels to display images according to a plurality of gate output voltages and a common voltage. The gate driving circuit provides a plurality of gate output voltages according to a gate input signal. The voltage selector provides a plurality of different positive gate voltages and a plurality of different common voltages, and outputs a corresponding positive gate voltage among the plurality of positive gate voltages according to the relationship between a reference voltage and an n-th level gate output voltage, and outputs a corresponding common voltage among the plurality of different common voltages, thereby being able to actively adjust the driving voltage.

Description

Display capable of actively adjusting driving voltage, voltage compensation circuit and driving method

technical field

The invention relates to a display, a voltage compensation circuit and a driving method, in particular to a display capable of actively adjusting a driving voltage, a voltage compensation circuit and a driving method.

Background technique

Due to the advantages of low radiation, small size and low energy consumption, liquid crystal display (LCD) has gradually replaced traditional cathode ray tube display (cathode ray tube display), which is widely used in notebook computers, personal digital assistants ( personal digital assistant, PDA), flat-screen TV, or information products such as mobile phones. The traditional method of liquid crystal display is to use an external driver chip to drive the pixels on the panel to display images, but in order to reduce the number of components and reduce manufacturing costs, it has gradually developed in recent years to directly fabricate the driving circuit structure on the display panel, such as gate The technology of integrating the gate driver into the LCD panel (Gate on Array, GOA).

Please refer to FIG. 1 , which is a schematic diagram of a liquid crystal display 100 in the prior art. As shown in FIG. 1 , the liquid crystal display 100 includes a liquid crystal display panel 110 , a source driving circuit 120 , and a gate driving circuit 130 . The liquid crystal display panel 110 of the liquid crystal display 100 is provided with a plurality of pixels PX arranged in an array, a plurality of data lines D ₁ -D _m , and a plurality of gate lines G ₁ -G _n . The source driving circuit 120 is used to drive the data lines D ₁ ˜D _m , and the gate driving circuit 130 can provide output voltages V ₁ ˜V _n to drive the gate lines G ₁ ˜G _n respectively.

Please refer to Figure 2. FIG. 2 is a schematic diagram describing the operating characteristics of a liquid crystal display. In Figure 2, the vertical axis represents the minimum output voltage (volts) of the gate drive circuit to operate the panel normally, the horizontal axis represents the use time (hours), the operating temperature of the liquid crystal display is 85 degrees Celsius, and curve A represents the positive gate voltage The characteristic curve when V _gh =11V and negative gate voltage V _g1 =-11V, curve B represents the characteristic curve when positive gate voltage V _gh =20V and negative gate voltage V _g1 =-11V. Since the minimum output voltage of the gate drive circuit in normal operation will gradually increase with the increase of operating time, see curve A in Figure 2, under the operating condition of positive gate voltage V _gh = 11V, the liquid crystal display has been used for more than about 250 hours Finally, the minimum output voltage that can normally operate the gate drive circuit will exceed the ideal gate voltage (V _gh = 11V) under this condition, which will easily cause abnormal operation; as shown in curve B of Figure 2, at the positive gate voltage V _gh Under the operating condition of =20V, the minimum output voltage of the liquid crystal display remains within the ideal voltage range even after about 800 hours of use. Therefore, increasing the positive gate voltage V _gh can effectively prolong the service life of the panel.

Please refer to Figure 3, which is a graph illustrating the power consumption of an LCD display under different operating conditions. In Fig. 3, T _{_stress} represents the length of time that the bias voltage is applied, and unstress represents that the bias voltage has not been applied yet. V _gh and V _g1 represent positive gate voltage and negative gate voltage (V), respectively, I _h and I ₁ represent current (mA) when positive gate voltage V _gh and negative gate voltage V _g are applied, P _h and _P1 represent the power consumption (mW) when positive gate voltage _Vgh and negative gate voltage _Vg are applied, respectively, and _{P_sum} represents the total power consumption (mW). Comparing the total power consumption P _{_sum} under the same condition of T _{_stress} , that is, comparing condition 1 and condition 2 or comparing condition 3 and condition 4, it can be known that the total power consumption P _{_sum} is proportional to the positive gate voltage V _gh . Therefore, although increasing the positive gate voltage V _gh can prolong the operating time, it also increases the power consumption of the panel.

Contents of the invention

The present invention provides a display capable of actively adjusting the driving voltage, which includes a display panel for turning on pixels to display images according to multiple groups of gate output voltages and a common voltage; a gate driving circuit for Input signals to provide the plurality of sets of gate output voltages; a voltage selector coupled to the gate drive circuit to receive an n-th stage gate output voltage among the plurality of sets of gate output voltages, the The voltage selector can provide multiple different positive gate voltages and multiple different common voltages, and can select from the multiple positive gate voltages according to the relationship between a reference voltage and the gate output voltage of the nth stage. selecting a corresponding positive gate voltage from among the gate voltages as an output positive gate voltage, and selecting a corresponding common voltage from the plurality of sets of different common voltages as the common voltage; a timing sequence The controller is used to generate a clock signal; and a voltage generator is used to generate a negative gate voltage.

The present invention also provides a voltage compensation circuit applied to a display panel, including a gate drive circuit for generating multiple sets of gate output voltages to a pixel array; a voltage selector coupled to the gate drive circuit To receive an n-th stage gate output voltage among multiple sets of gate output voltages, the voltage selector can provide multiple sets of different positive gate voltages and multiple sets of different common voltages, and can be based on a reference voltage and the relationship between the gate output voltage of the nth stage, select a corresponding positive gate voltage from the multiple sets of positive gate voltages as an output positive gate voltage, and select a corresponding positive gate voltage from the multiple sets of phase A corresponding common voltage is selected from different common voltages as the common voltage; a timing controller is used to generate a clock signal; and a voltage generator is used to generate a negative gate voltage.

The present invention further provides a method for driving a display panel, including providing an n-th stage gate output voltage among a plurality of gate output voltages; comparing a reference voltage with the potential level between the n-th stage gate output voltage ; When the gate output voltage of the nth stage is greater than the reference voltage, select a corresponding first positive gate voltage in multiple sets of positive gate voltages as an output positive gate voltage, and select multiple sets of phase A corresponding first common voltage among different common voltages is used as an output common voltage; A second positive gate voltage of the first positive gate voltage is used as the output positive gate voltage, and a second common voltage smaller than the first common voltage among the plurality of common voltages is selected as the output positive gate voltage the output common voltage.

By using the technical solution provided by the invention, the service life of the display panel can be improved without greatly increasing power consumption.

Description of drawings

FIG. 1 is a schematic diagram of a liquid crystal display in the prior art.

FIG. 2 is a schematic diagram of the operating characteristics of a liquid crystal display.

FIG. 3 is a graph illustrating power consumed by a liquid crystal display under different operating conditions.

FIG. 4 is a graph illustrating the relationship between the magnitude of the bias voltage applied to the liquid crystal display and the time.

FIG. 5 is a schematic diagram of a liquid crystal display in the present invention.

FIG. 6 is a functional block diagram of the gate compensation circuit of the present invention.

FIG. 7 is a functional block diagram of the voltage selector in the first embodiment of the present invention.

FIG. 8 is a timing diagram of the operation of the voltage selector according to the first embodiment of the present invention.

FIG. 9 is a functional block diagram of the voltage selector in the second embodiment of the present invention.

FIG. 10 is a timing diagram of the operation of the voltage selector according to the second embodiment of the present invention.

Fig. 11 is a flowchart of the operation of the voltage selector of the present invention.

FIG. 12 is a schematic diagram of a liquid crystal display in another embodiment of the present invention.

Reference number

50 voltage selector 52 timing controller

54 voltage generator 56 voltage level shifter

58 comparators 60ADC

62 counter 64 voltage output circuit

66 control circuit 540 gate compensation circuit

D ₁ ～D _m data lines G ₁ ～G _n gate lines

PX pixel MUX1, MUX2 multiplexer

100, 500 liquid crystal display 110, 510 liquid crystal display panel

120, 520 source drive circuit 130, 530-532 gate drive circuit

Detailed ways

Please refer to Figure 3 again, compare the total power consumption P _{_sum} under the same bias conditions, that is, compare condition 1 and condition 3 or compare condition 2 and condition 4, you can know the total power consumption P _{_sum} and the time of applying the bias voltage _{T_stress} is inversely proportional. When _{T_stress} exceeds a certain value (for example, 500 hours), under the same bias condition, the total power consumption _{P_sum} is reduced to about half of that of unstress (for example, from 115mV to 46.2mV or from 202.9mV to 111.7mV ). The present invention _uses this panel characteristic to drive the panel with a lower positive gate voltage V _gh at the beginning to save power consumption; Drive the panel to increase the service life of the panel without greatly increasing power consumption.

Due to the feed-through effect, the common voltage V _com of the display panel will also change with the value of the positive gate voltage V _gh . Please refer to FIG. 4 . FIG. 4 illustrates the relationship among the common voltage, the positive gate voltage V _gh and the biasing time T _{_stress} . As shown in Figure 4, V _com represents the common voltage when unstressed, and the common voltage V _com is inversely proportional to the positive gate voltage V _gh ; V _com' represents the common voltage when _{T_stress} is greater than a specific value (for example, 500 hours), The common voltage V _com' is also inversely proportional to the positive gate voltage V _gh . Meanwhile, when T _{_stress} exceeds a certain value (for example, 500 hours), the positive gate voltage V _gh needs to be greater than a certain value (for example, 15V) to operate the display panel normally. Comparing the value of the common voltage under the same positive gate voltage V _gh , that is, comparing V _com and V _com' , it can be seen that there is little difference between V _com and V _com' . In other words, the time T _{_stress} of applying the bias voltage has little influence on the common voltage, so the present invention only needs to consider the influence of the positive gate voltage V _gh on the common voltage: at the beginning, a lower positive gate voltage V _gh and a higher common voltage V _com to drive the panel to save power consumption; when the use time exceeds a predetermined value, then drive the panel with a higher positive gate voltage V _gh and a lower common voltage V _com to increase the power consumption of the panel service life without significantly increasing power consumption or changing the characteristics of the display panel.

Please refer to FIG. 5 , which is a schematic diagram of a liquid crystal display 500 in the present invention. The liquid crystal display 500 includes a liquid crystal display panel 510 , a source driving circuit 520 , a gate driving circuit 530 , and a gate compensation circuit 540 . The liquid crystal display panel 510 is provided with a plurality of pixels PX arranged in an array, a plurality of data lines D ₁ -D _m , and a plurality of gate lines G ₁ -G _n . The source driving circuit 520 of the liquid crystal display 500 . The gate driving circuit 530 operates according to the gate input signal Si. The gate input signal Si includes a voltage signal V _ss , a start pulse signal V _st , a clock signal V _ck , and an inverted clock signal V _xck wait. According to the gate input signal Si, the gate drive circuit 530 can drive the gate lines G ₁ -G _n with the corresponding positive gate voltage V _gh and negative gate voltage V _g1 , at this time, the output of the gate drive circuit 530 The voltages are represented by V ₁ to V _n , respectively. The gate compensation circuit 540 can provide the gate input signal Si to the gate drive circuit 530 and the gate common voltage V _com to the liquid crystal display panel 510, and correct the gate input signal Si and the gate input signal Si according to the output voltage of the gate drive circuit 530. Therefore, the liquid crystal display panel 510 can be driven with an _optimal bias voltage.

When the liquid crystal display 500 starts to operate, the gate driving circuit 530 drives the gate lines G ₁ -G _n with a predetermined positive gate voltage V _gh1 and a predetermined negative gate voltage V _g1 . Since the nth stage output of the gate drive circuit 530 is located at the end of the signal transmission path, its output voltage usually does not meet the operating conditions at the earliest, so the present invention can judge the liquid crystal according to the nth stage output voltage V _n of the gate drive circuit 530. Whether the display 500 can function normally under such bias conditions. For example, if the output voltage of each stage of the gate drive circuit 530 must be greater than the reference voltage V _ref under the condition of normal operation of the liquid crystal display 500 , the gate compensation circuit 540 of the present invention will determine the output voltage V _n of the nth stage Whether it is greater than the reference voltage V _ref : if the output voltage V _n of the nth stage is greater than the reference voltage V _ref , in most cases the output voltages of other stages of the gate drive circuit 530 will also be greater than the reference voltage V _ref . The liquid crystal display panel 510 is driven with a positive gate voltage V _gh1 , a negative gate voltage V _g1 and a common voltage V _com1 under predetermined bias conditions. When the liquid crystal display 500 is used for a certain period of time, its characteristics may deteriorate. At this time, if the liquid crystal display panel 510 continues to be driven under predetermined bias voltage conditions, predetermined display quality may not be achieved. Therefore, if the output voltage V _n of the nth stage is not greater than the reference voltage V _ref , the gate compensation circuit 540 will provide the corresponding gate input signal Si, so that the positive gate voltage V _gh2 and the negative The liquid crystal display panel 510 is driven by the gate voltage V _g1 and the common voltage V _com2 . In other words, the gate compensation circuit 540 can actively compensate the gate input voltage Si according to the output voltage of the gate drive circuit 530, so that the gate drive circuit 530 can drive the gate with the corresponding positive gate voltage _Vgh The lines G ₁ -G _n provide the corresponding common voltage V _com to the liquid crystal display panel 510 .

As shown in FIGS. 2-4 , V _gh2 >V _gh1 and V _com2 <V _com1 in the aforementioned embodiments. That is, when the display quality of the liquid crystal display 500 does not meet the predetermined standard, the present invention uses a higher positive gate voltage V _gh and a lower common voltage V _com to drive the panel to increase the service life of the panel without greatly increasing the power consume.

Please refer to FIG. 6 , which is a functional block diagram of the gate compensation circuit 540 . The gate compensation circuit 540 includes a voltage selector 50 , a timing controller 52 , a voltage generator 54 , and a voltage level shifter 56 . The voltage selector 50 is coupled to the gate driving circuit 530 and the liquid crystal display panel 510 , and can provide a corresponding positive gate voltage V _gh and a common voltage V _com according to the output voltage V _n of the gate driving circuit 530 . The timing controller 52 can provide the logic signal Sc required for the operation of the gate driving circuit 530 , and the voltage generator 54 can provide the negative gate voltage V _g1 . The voltage level shifter 56 is coupled to the voltage selector 50, the timing controller 52, the voltage generator 54 and the gate driving circuit 530, and can be based on the logic signal Sc, the positive gate voltage V _gh , and the negative gate voltage V _g1 to provide the gate input signal Si, so that the gate drive circuit 530 can be based on the voltage signal V _ss , the start pulse signal V _st , the clock signal V _ck , and the reverse clock signal V _xck in the gate input signal Si. Wait for it to work.

Please refer to FIG. 7 , which is a functional block diagram of the voltage selector 50 in the first embodiment of the present invention. The voltage selector 50 of the first embodiment includes a comparator 58 , an analog to digital converter (Analog to Digital Converter, ADC) 60 , a counter 62 , and a voltage output circuit 64 . The comparator 58 is coupled to the gate driving circuit 530, and is used to compare the potential level of the reference voltage V _ref and the output voltage V _n : if the output voltage V _n is greater than the reference voltage V _ref , the comparator 58 will output a high potential analog signal V _a ; If the output voltage V _n is not greater than the reference voltage V _ref , the comparator 58 will output a low potential analog signal V _a . The analog-to-digital converter 60 is coupled to the comparator 58 and can convert the analog signal V _a into a digital signal V _d : if a high-potential analog signal V _a is received, the analog-to-digital converter 60 will output a digital signal V with logic 1 potential _d ; if receiving the low-level analog signal V _a , the analog-to-digital converter 60 will output a digital signal V _d with logic 0 potential. The counter 62 is coupled to the analog-to-digital converter 60 and can generate an output count value C _o according to the digital signal V _d . The voltage output circuit 64 includes a control circuit 66 and multiplexers MUX1, MUX2, the control circuit 66 is coupled to the counter 62, and can compare the output count value C _o with the reference count value C _t and output a corresponding control signal V _t , The multiplexers MUX1 and MUX2 can output a corresponding positive gate voltage and a common voltage according to the control signal V _t . For example, if the output count value C _o is greater than the reference count value C _t , the multiplexer MUX1 will output a positive gate voltage V _gh1 (for example, 11V) to the voltage level shifter 56, and output a common voltage V _com1 (for example, 3.89V V) to the liquid crystal display panel 510; if the output count value C _o is not greater than the reference count value C _t , the multiplexer MUX1 will output the positive gate voltage V _gh2 (for example, 20V) to the voltage level shifter 56, and output the common voltage V _com2 (eg 3.29V) to the LCD panel 510 .

Please refer to FIG. 8 , which is a timing diagram of the voltage selector 50 in operation according to the first embodiment of the present invention. FIG. 8 shows the waveforms of the output voltage V _n , the digital signal V _d , the positive gate voltage V _gh and the common voltage V _com . When the value of the output voltage V _n is greater than the reference voltage V _ref , the counter 62 starts counting until the value of the output voltage V _n is lower than the reference voltage V _ref , and the calculated output count values are respectively determined by C _o1 , C _o2 , and C _o3 ,... wait to express. In the embodiment of FIG. 8 , the time when the first three output voltages V _n1 -V _n3 are higher than the reference voltage V _ref respectively correspond to the output count values C _o1 -C _o3 , wherein the output count values C _o1 and C _o3 are greater than the reference count value C _t , while the output count value C _o2 is less than the reference count value C _t . Since C _o1 >C _t , the liquid crystal display is still driven by the positive gate voltage V _gh1 and the common voltage V _com1 corresponding to the output voltage V _n1 . Afterwards, the waveform of the output voltage V _n2 deviates from the ideal value, so that C _o2 <C _t , at this time, the present invention selects a better positive gate voltage V _gh2 and a common voltage V _com2 to drive the liquid crystal display. After using the optimal driving voltage, the waveform of the output voltage V _n3 returns to normal, so C _o3 >C _t , and the present invention will continue to use the positive gate voltage V _gh2 and the common voltage V _com2 to drive the LCD.

Please refer to FIG. 9 , which is a functional block diagram of the voltage selector 50 in the second embodiment of the present invention. The second embodiment is similar to the first embodiment, except that the first embodiment in FIG. 7 can provide two sets of different bias conditions of V _gh1 /V _g1 /V _com1 and V _gh2 /V _g1 /V _com2 , and The second embodiment in FIG. 9 can provide n sets of different bias conditions such as V _gh1 /V _g1 /V _{com1˜V ghn} /V _g1 /V _comn . In the second embodiment, the control circuit 66 of the voltage output circuit 64 also compares the output count value C _o with the reference count value C _t and outputs a corresponding control signal V _t , and the multiplexers MUX1 and MUX2 can be based on The control signal V _t outputs a corresponding positive gate voltage and a common voltage. For example, if the output count value C _o is greater than the reference count value C _t , the multiplexer MUX1 will output a positive gate voltage V _gh1 (for example, 11V) to the voltage level shifter 56, and output a common voltage V _com1 (for example, 3.89V V) to the liquid crystal display panel 510; when the output count value Co is not greater than the reference count value Ct, the multiplexer MUX1 will first output the positive gate voltage V _gh2 (for example, 13V) to the voltage level shifter 56, and the multiplexer The device MUX2 will first output the common voltage V _com2 (for example, 3.72V) to the liquid crystal display panel 510, and then determine whether the driving condition is sufficient. If the positive gate voltage V _gh2 and the output common voltage V _com2 are used to drive the output voltage V _n to be greater than the reference voltage V _ref and the output count value C _o is still not greater than the reference count value C _t , then the multiplexer MUX1 Will output the positive gate voltage V _gh3 (for example 15V) to the voltage level shifter 56, and the multiplexer MUX2 will output the common voltage V _com3 (for example 3.53V) to the liquid crystal display panel 510; if the positive gate voltage V _gh2 When driven with the output common voltage V _com2 , the output voltage V _n is greater than the reference voltage V _ref , and the voltage selector 50 will continue to provide this bias condition and perform the above-mentioned determination steps periodically. In the case of driving with the positive gate voltage V _gh3 and the output common voltage V _com3 , if the output voltage V _n is lower than the reference voltage V _ref again, the bias condition will be changed again, and the multiplexer MUX1 outputs a positive gate The voltage V _gh4 (for example 20V) is sent to the voltage level shifter 56 , and the multiplexer MUX2 outputs the common voltage V _com4 (for example 3.29V) to the LCD panel 510 . In other words, the second embodiment of the present invention can gradually change the value of the bias voltage according to the value of the output voltage _Vn , instead of changing the value of the bias voltage greatly all at once.

Please refer to FIG. 10 , which is a timing diagram of the voltage selector 50 in operation according to the second embodiment of the present invention. Fig. 10 shows the waveforms of output voltage _Vn , digital signal _Vd , positive gate voltage _Vgh and common voltage _Vcom . When the value of the output voltage V _n is greater than the reference voltage V _ref , the counter 62 starts counting until the value of the output voltage V _n is lower than the reference voltage V _ref , and the calculated output count values are respectively determined by C _o1 , C _o2 , and C _o3 , C _o4 , ... etc. to express. In the example shown in Fig. 10, the time when the first four output voltages V _n1 ~ V _n4 are higher than the reference voltage V _ref respectively correspond to the output count values C _o1 ~ C _o4 , wherein the output count values C _o1 and C _o4 are greater than the reference count value C _t , while the output count values C _o2 and C _o3 are smaller than the reference count value C _t . Since C _o1 >C _t , the liquid crystal display is still driven by the positive gate voltage V _gh1 and the common voltage V _com1 corresponding to the output voltage V _n1 . Afterwards, the waveform of the output voltage V _n2 deviates from the ideal value, so that C _o2 <C _t , at this time, the present invention selects a better positive gate voltage V _gh2 and a common voltage V _com2 to drive the liquid crystal display. After using the positive gate voltage V _gh2 and the common voltage V _com2 , the waveform of the output voltage V _n3 still deviates from the ideal value, so C _o3 <C _t , at this time the present invention will select the better positive gate voltage V _gh3 and common voltage V _com3 to drive the liquid crystal display. After using the positive gate voltage V _gh3 and the common voltage V _com3 , the waveform of the output voltage V _n4 returns to normal, so C _o4 > C _t , and the present invention will continue to use the positive gate voltage V _gh3 and the common voltage V _com3 to Drive the LCD display.

Please refer to FIG. 11 . FIG. 11 is a flowchart of the operation of the voltage selector 50 of the present invention. The flowchart of Figure 11 includes the following steps:

Step 910: providing multiple sets of positive gate voltages and multiple sets of common voltages;

Step 920: Outputting a predetermined positive gate voltage among multiple sets of positive gate voltages and a predetermined common voltage among multiple sets of common voltages;

Step 930: Receive a gate output voltage V _n ;

Step 940: Determine whether the gate output voltage V _n is greater than a reference voltage V _ref ; if the gate output voltage V _n is greater than the reference voltage V _ref , execute step 960 ; if the gate output voltage V _n is not greater than the reference voltage V _ref , execute Step 950;

Step 950: Outputting the positive gate voltage corresponding to the other of the multiple sets of positive gate voltages and the common voltage corresponding to the other of the multiple sets of common voltages; perform step 930;

Step 960: Output the positive gate voltage corresponding to the gate output voltage _Vn and the common voltage; execute step 930.

Please refer to FIG. 12 , which is a schematic diagram of a liquid crystal display 550 in another embodiment of the present invention. The liquid crystal display 550 includes a liquid crystal display panel 510 , a source driving circuit 520 , two gate driving circuits 531 and 532 , and a gate compensation circuit 540 . The liquid crystal display 550 is similar to the liquid crystal display 500 except that the liquid crystal display 550 adopts a double-sided driving structure, that is, the gate driving circuits 531 and 532 are arranged on two sides of the liquid crystal display panel 510 respectively. Both the gate driving circuits 531 and 532 operate according to the gate input signal Si, and their output voltages are represented by Vl ₁ ˜Vl _n and Vr ₁ ˜Vr _n respectively. The liquid crystal display 550 of the present invention simultaneously judges whether it can operate normally under predetermined bias voltage conditions according to the n-th output voltages Vl _n and Vr _n of the gate driving circuits 531 and 532 . For example, if one of the n-th stage output voltages Vl _n and _Vrn is not greater than the reference voltage V _ref , the gate compensation circuit 540 will provide a corresponding gate input signal Si to change the gate driving circuits 531 and 532 at the same time. driving conditions.

As mentioned above, the present invention can select the nth stage output voltage V _n located at the end of the signal transmission path as the judgment condition, and can also judge whether the LCD can operate normally according to the output voltages of other stages. The structure of the voltage selector 50 in FIG. 7 and FIG. 8 is only an embodiment of the present invention, and does not limit the scope of the present invention.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (21)

1. the display that can initiatively adjust driving voltage is characterized in that, the described display that can initiatively adjust driving voltage comprises:

One display panel is used for coming on-pixel with display image according to many group grid output voltages and a common voltage;

One gate driver circuit is used for providing described many group grid output voltages according to a grid input signal;

One voltage selector, be coupled to described gate driver circuit to receive the n level grid output voltage in described many group grid output voltages, described voltage selector can provide a plurality of different positive gate voltage and a plurality of different common voltage, and can just concern according to the current potential between a reference voltage and the described n level grid output voltage, from described a plurality of positive gate voltage, choose a corresponding positive gate voltage with as an output positive gate voltage, and from the different common voltage of described many groups, choose a corresponding common voltage with as described common voltage;

Time schedule controller is used for producing a clock pulse signal; And

One voltage generator is used for producing a negative-gate voltage.

2. display as claimed in claim 1 is characterized in that, described voltage selector comprises:

One comparer is coupled to described gate driver circuit, is used for the current potential height of more described reference voltage and described n level grid output voltage, and produces a simulating signal according to comparative result;

One analog-digital converter is coupled to described comparer, and being used for described analog signal conversion is a digital signal;

One counter is coupled to described analog-digital converter, is used for producing an output count value according to described digital signal; And

One voltage follower circuit is coupled to described counter, is used for the size of a more described output count value and a reference count value, and produces described output positive gate voltage and described common voltage according to comparative result.

3. display as claimed in claim 2 is characterized in that, when the current potential of described n level grid output voltage during greater than described reference voltage, described comparer is exported a noble potential simulating signal; And

When the current potential of described n level grid output voltage was not more than described reference voltage, described comparer was exported an electronegative potential simulating signal.

4. display as claimed in claim 2 is characterized in that, when receiving a noble potential simulating signal, described analog-digital converter is a logical one digital signal with described noble potential analog signal conversion; And

When receiving an electronegative potential simulating signal, described analog-digital converter is a logical zero digital signal with described electronegative potential analog signal conversion.

5. display as claimed in claim 2, it is characterized in that, when described output count value during greater than described reference count value, described voltage follower circuit is chosen in described many group positive gate voltage an original positive gate voltage with as described output positive gate voltage, and chooses in the different common voltage of described many groups an original common voltage with as described common voltage; And

When described output count value during less than described reference count value, described voltage follower circuit choose in described many group positive gate voltage one greater than the positive gate voltage of described original positive gate voltage with as described output positive gate voltage, and choose in the different common voltage of described many groups one less than the common voltage of described original common voltage with as described common voltage.

6. display as claimed in claim 2 is characterized in that, described voltage follower circuit comprises:

One controller is coupled to described counter, is used for the size of more described output count value and described reference count value, and produces a control signal according to comparative result;

One first multiplexer is coupled to described controller, is used for choosing described output positive gate voltage according to described control signal from a plurality of positive gate voltage; And

One second multiplexer is coupled to described controller, is used for choosing described common voltage according to described control signal from a plurality of different common voltages.

7. display as claimed in claim 1 is characterized in that described gate driver circuit is integrated in described liquid crystal panel.

8. display as claimed in claim 1 is characterized in that, described display comprises in addition:

One voltage quasi position translator is coupled to described voltage selector, described time schedule controller and described voltage generator, be used for according to described clock signal, described negative-gate voltage, and described output positive gate voltage produces described grid input signal.

9. a voltage compensating circuit that is applied to display panel is characterized in that, described voltage compensating circuit comprises:

One gate driver circuit is in order to produce many group grid output voltage to pel arrays;

One voltage selector, be coupled to described gate driver circuit to receive the n level grid output voltage in many group grid output voltages, described voltage selector can provide different positive gate voltage of many groups and the different common voltage of many groups, and can just concern according to the current potential between a reference voltage and the described n level grid output voltage, from described many group positive gate voltage, choose a corresponding positive gate voltage with as an output positive gate voltage, and from the different common voltage of described many groups, choose a corresponding common voltage with as described common voltage;

Time schedule controller is used for producing a clock pulse signal; And

One voltage generator is used for producing a negative-gate voltage.

10. voltage compensating circuit as claimed in claim 9 is characterized in that, described voltage selector comprises:

One comparer is coupled to described gate driver circuit, is used for the current potential height of more described reference voltage and described n level grid output voltage, and produces a simulating signal according to comparative result;

One analog-digital converter is coupled to described comparer, and being used for described analog signal conversion is a digital signal;

One counter is coupled to described analog-digital converter, is used for producing an output count value according to described digital signal; And

One voltage follower circuit is coupled to described counter, is used for the size of a more described output count value and a reference count value, and produces described output positive gate voltage and described common voltage according to comparative result.

11. voltage compensating circuit as claimed in claim 10 is characterized in that, when the current potential of described n level grid output voltage during greater than described reference voltage, described comparer is exported a noble potential simulating signal; And

When the current potential of described n level grid output voltage was not more than described reference voltage, described comparer was exported an electronegative potential simulating signal.

12. voltage compensating circuit as claimed in claim 10 is characterized in that, when receiving a noble potential simulating signal, described analog-digital converter is a logical one digital signal with described noble potential analog signal conversion; And

When receiving an electronegative potential simulating signal, described analog-digital converter is a logical zero digital signal with described electronegative potential analog signal conversion.

13. voltage compensating circuit as claimed in claim 10 is characterized in that, described counter produces described output count value according to the width of described digital signal.

14. voltage compensating circuit as claimed in claim 10, it is characterized in that, when described output count value during greater than described reference count value, described voltage follower circuit is chosen in described many group positive gate voltage an original positive gate voltage with as described output positive gate voltage, and chooses in described many group common voltages an original common voltage with as described common voltage; And

When described output count value during less than described reference count value, described voltage follower circuit choose in described many group positive gate voltage one greater than the positive gate voltage of described original positive gate voltage with as described output positive gate voltage, and choose in described many group common voltages one less than the common voltage of described original common voltage with as described common voltage.

15. voltage compensating circuit as claimed in claim 10 is characterized in that, described voltage follower circuit comprises:

One controller is coupled to described counter, is used for the size of more described output count value and described reference count value, and produces a control signal according to comparative result;

One first multiplexer is coupled to described controller, is used for from a plurality of positive gate voltage, choosing described output positive gate voltage according to described control signal, and

One second multiplexer is coupled to described controller, is used for choosing described common voltage according to described control signal from a plurality of common voltages.

16. voltage compensating circuit as claimed in claim 9, it is characterized in that, described voltage compensating circuit comprises a voltage quasi position translator in addition, be coupled to described voltage selector, described time schedule controller and described voltage generator, be used for according to described clock signal, described negative-gate voltage, and described output positive gate voltage produces the required grid input signal of the described gate driver circuit of driving.

17. a method that drives display panel is characterized in that, described method comprises:

N level grid output voltage in a plurality of grid output voltages is provided;

Relatively the current potential between a reference voltage and the described n level grid output voltage just;

When described n level grid output voltage during greater than described reference voltage, choose in many group positive gate voltage corresponding first positive gate voltage with as an output positive gate voltage, and choose in the different common voltage of many groups corresponding first common voltage with as an output common voltage; And

When described n level grid output voltage is not more than described reference voltage, choose in described a plurality of positive gate voltage greater than one second positive gate voltage of described first positive gate voltage with as described output positive gate voltage, and choose in described a plurality of common voltage less than one second common voltage of described first common voltage with as described output common voltage.

18. method as claimed in claim 17 is characterized in that, described method also comprises:

Comparative result according to the height of the current potential between described reference voltage and the described n level grid output voltage provides a simulating signal;

With described analog signal conversion is a logic digital signal;

Width according to described logic digital signal produces an output count value; And

The size of a more described output count value and a reference count value.

19. method as claimed in claim 17 is characterized in that, described n level grid output voltage is to be afterbody grid output voltage.

20. method as claimed in claim 17 is characterized in that, described method comprises in addition provides described a plurality of positive gate voltage and described a plurality of common voltage.

21. method as claimed in claim 17 is characterized in that, described method comprises that in addition described output positive gate voltage of foundation and described output common voltage drive a display panel.

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