CN101426316A - Irregular LED array displaying message frame sending controller and method - Google Patents
Irregular LED array displaying message frame sending controller and method Download PDFInfo
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Abstract
本发明提供一种非规则LED阵列显示信息帧发送控制器，包括DVI/USB数据接收电路板、FPGA控制电路板，DVI/USB数据接收电路板作为目标设备与FPGA控制电路板作为主控设备相连接；本发送控制器分别通过DVI电缆和USB电缆与电脑终端相连接，还通过超5类双绞线与数据分配器组连接后再与数据缓冲器、LED灯具依次连接，构成LED灯饰控制系统，其中，所述数据分配器组由多个数据分配器串行连接组成。通过该视频处理系统，计算机上播放的任何信息可实时地在LED阵列中显示，该视频处理系统设备即插即用、数据传输速率高、稳定性高、扩展性强、系统的鲁棒性强，可满足任何规划阵列以及不同LED阵列规模的需要。
The present invention provides an irregular LED array display information frame sending controller, which includes a DVI/USB data receiving circuit board and an FPGA control circuit board. The DVI/USB data receiving circuit board is used as a target device and the FPGA control circuit board is used as a main control device Connection; the sending controller is connected to the computer terminal through a DVI cable and a USB cable respectively, and is also connected to the data distributor group through a super-category 5 twisted pair, and then connected to the data buffer and LED lamps in sequence to form an LED lighting control system , wherein the data distributor group is composed of multiple data distributors connected in series. Through the video processing system, any information played on the computer can be displayed in the LED array in real time. The video processing system equipment is plug-and-play, with high data transmission rate, high stability, strong scalability, and strong system robustness. , which can meet the needs of any planned array and different scales of LED arrays.
Description
Technical field
The present invention relates to the LED display control technology in the semiconductor lighting, specifically be meant irregular LED array displaying message frame sending controller and method.
Background technology
Traditional Landscape Lighting uses static neon light as curtain wall decoration, light and simple color change are only arranged, can not the double as amusement, multiple use such as advertisement, information propagation, can not satisfy building, as the individualized feature demand on significant building, bridge and square, and power consumption is relatively large.LED is a kind of novel high efficiency light source, for neon light, fluorescent lamp, except that have no mercury, economize material, to the advantages such as environment no electromagnetic pollution, no harm ray, the more important thing is to have advantages such as energy-conservation, that the life-span is long, the LED technical development has become the important component part of national energy strategy.In Landscape Lighting, because LED adopts low-voltage power supply, its expense that is used to insulate is compared much smaller with neon light, and reliability is higher, so LED light become the main development trend of landscape light in city from now on, has also obtained fast development in recent years.
The application of LED landscape lamp decoration system is increasing, provide the producer of light fixture many, but the unit of research control system is few, and that sees on the market has two kinds: a kind of control system of the DMX512 of being based on agreement, another kind are based on the LED lamp decoration control system of Ethernet.But these systems all only are applicable to regular LED cell array (the LED pixel is arranged by the mode of ranks, and has unified line-spacing and unified row distance).Another defective of these systems is often to require the picture element of computer indication range and LED picture element to have relation one to one, makes it to lack the flexibility of playing scope definition.
In practical engineering application, irregular LED cell array layout has very big demand, and such as the existence of skin window, even the specification of the window on the same face wall all can have variety classes.The exterior wall surface of part building is also not necessarily with a kind of specification, and some building can adopt different styles for outstanding individual character in different floor sections.For this class building, just have certain difficulty by unified line-spacing and row apart from layout L ED light fixture, even feasible reluctantly, the image quality that its engineering cost also can be higher, show is not high yet.On the other hand, if wish that (this is the major function with LED lamp decoration system of real-time playing function for profile with the less bigger picture of LED cell array demonstration, the integrality of picture is one of main performance index, the sophistication of picture takes second place), adopt above-mentioned mapping relations one to one also to be difficult to realize.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of irregular LED array displaying message frame sending controller is provided, transmit control device of the present invention can satisfy the large LED lamp decoration control system that is applied to irregular LED cell array layout, and layout is flexible, engineering cost is lower, image quality is high, realization is simple.
Another object of the present invention is to provide irregular LED array displaying message frame sending controller to realize that irregular LED array displaying message frame sends the method for control.
Purpose of the present invention is achieved through the following technical solutions: irregular LED array displaying message frame sending controller comprises the FPGA control circuit board as main control device that is connected, as the DVI/USB data receiver circuit plate of target device;
Wherein, described FPGA control circuit board comprises image buffer storage SRAM, configuration information buffer memory SRAM, network interface circuit, the power circuit that FPGA main control chip and described FPGA main control chip connect respectively;
Described DVI/USB data receiver circuit plate comprises DVI data-interface, usb data interface, and described DVI data-interface, usb data interface are connected with the FPGA main control chip of described FPGA control circuit board respectively.
Described FPGA main control chip comprises DVI data reception module, SPI data reception module, PLL frequency multiplication module, view data and configuration information processing module, internal RAM module, network interface sending module; Wherein, described DVI data reception module, the SPI data reception module also respectively with image buffer storage SRAM, configuration information buffer memory SRAM is corresponding to be connected, described view data and configuration information processing module respectively with the DVI data reception module, the SPI data reception module, PLL frequency multiplication module, the internal RAM module, network interface sending module and above-mentioned image buffer storage SRAM, configuration information buffer memory SRAM is connected, PLL frequency multiplication module while and DVI data reception module, the SPI data reception module connects, the internal RAM module is connected with the network interface sending module simultaneously, and the network interface sending module is connected with network interface circuit.
Described SPI data reception module comprises the SPI string that is connected and modular converter, SPI data memory module.
Described DVI data-interface comprises the DVI decoding circuit, and the DVI decoding circuit comprises DVI decoding chip and peripheral circuits thereof, and peripheral circuits comprises EEPROM and some exclusions of power circuit, storage EDID data.
Described USB receiving interface comprises the chip and the peripheral circuits thereof of ARM7 (can be replaced by other serial ARM chips, as ARM9) kernel, and peripheral circuits comprises power circuit, program download circuit, feeds dog circuit etc.
Described DVI data reception module is provided with clock port, the image synchronization control port, the effective port of image, the view data input port, external SRAM control signal port, external SRAM data/address port, described SPI data reception module is provided with the SPI clock port, the SPI FPDP, external SRAM control signal port, external SRAM data/address port, USB ready signal port, described view data and configuration information processing module are provided with clock port, external SRAM data/address read write port is arranged, internal RAM data write port, frame data are prepared port, the control signal port.Above DVI data reception module, the SPI data reception module, view data is connected according to following form with the configuration information processing module, described DVI data reception module, the clock port of view data and configuration information processing module is connected with the 65MHz clock of process PLL frequency multiplication module respectively, the SPI clock port of described SPI data reception module connects the 25MHz clock through PLL frequency multiplication module, DVI data reception module, the write data enable port (WE) of the SRAM of SPI data reception module and output enable port (OE) respectively the alternative multiway analog switch (MUX) by view data and configuration information processing module to image buffer storage SRAM, configuration information buffer memory SRAM controls.The SRAM data-signal port (data) of DVI data reception module, SPI data reception module and address signal port (address) are also controlled image buffer storage SRAM, configuration information buffer memory SRAM by this alternative multiway analog switch (MUX) respectively.
Adopt the irregular LED array lamp decoration control system of above-mentioned irregular LED array displaying message frame sending controller, comprise irregular LED array displaying message frame sending controller, the computer terminal, the data distributor group, data buffer, the LED light fixture, the DVI data-interface of the DVI/USB data receiver circuit plate of described irregular LED array displaying message frame sending controller, the usb data interface is respectively by the DVI cable, USB cable is connected with the computer terminal, the network interface circuit of the FPGA control circuit board of described irregular LED array displaying message frame sending controller is connected with the data distributor group by super category 5 twisted pair, again with data buffer, the LED light fixture connects successively, wherein, described data distributor group is formed by a plurality of data distributors are connected in series.
Described computer terminal comprises and is used to generate the topology file generation module of topology file and the information sending module that is used to send layout information, sectional drawing frame information and user's input information.
The information of described user's input comprises X coordinate amplification coefficient Lx and Y coordinate amplification coefficient Ly.
The irregular LED array lamp decoration control method of above-mentioned irregular LED array lamp decoration control system may further comprise the steps:
(1) the topology file generation module of computer terminal generates the led array layout according to any irregular layout situation of actual light fixture, thereby and X, the Y coordinate figure of each picture element of storage led array obtain the topology file of suffix 1mp by name;
(2) information sending module of computer terminal generates the layout information Frame that comprises each LED picture element X, Y coordinate figure according to topology file, and information sending module sends to the layout information Frame by the USB interface of computer terminal the usb data interface of DVI/USB data receiver circuit plate then;
(3) information sending module of computer terminal generates sectional drawing frame information configuration frame according to the position and the user's input information of sectional drawing frame, this user's input information comprises X coordinate amplification coefficient Lx and Y coordinate amplification coefficient Ly, by the USB interface of computer terminal sectional drawing frame information configuration frame is sent to the usb data interface of DVI/USB data receiver circuit plate then;
(4) computer terminal sends to computer desktop color of image data the DVI data-interface of DVI/USB data receiver circuit plate by the DVI interface by the DVI standard;
(5) the DVI data reception module of FPGA main control chip receives computer desktop color of image data and stores into the image buffer storage SRAM from the DVI data-interface of DVI/USB data receiver circuit plate;
(6) the usb data receiver module of FPGA main control chip receives layout information Frame, sectional drawing frame information configuration frame and stores into the configuration information buffer memory SRAM from the usb data interface of DVI/USB data receiver circuit plate;
(7) view data of FPGA main control chip and configuration information processing module are handled described layout information Frame, sectional drawing frame information configuration frame, obtain the LED picture element that actual needs shows coordinate figure (x, y);
(8) coordinate figure (x of the LED picture element that shows according to actual needs of the view data of FPGA main control chip and configuration information processing module, y), from image buffer storage SRAM, extract corresponding computer desktop color of image data, judge then whether frame data run through, if run through, then the corresponding layout information of combination is assembled into ethernet data frame and stores in the internal RAM; If do not run through, repeating step (7) then;
(9) described network interface sending module is read ethernet data frame and is sent to data distributor through network interface circuit among the RAM internally, judges that then sectional drawing frame configuration information has no change, if change, then repeating step (3) is to step (9); If do not change, then repeating step (6) is to step (9);
(10) data distributor constantly repeats to receive ethernet data frame, and information extraction produces pwm control signal driving LED light fixture from ethernet data frame.
In the said method, the described computer desktop color of image of step (1) data comprise R, G, the trichromatic pixel data of B.
In the said method, the described computer desktop color of image of step (4) data are continual, real-time operations by the operation that the DVI interface sends to the DVI data-interface of DVI/USB data receiver circuit plate, walk abreast with other each steps, be not subjected to the influence of other each step operations.In the said method, adopt ping-pong operation performing step (4) and the parallel of other each steps to carry out.
In the said method, the view data of the described FPGA main control chip of step (7) and configuration information processing module are handled described layout information Frame, sectional drawing frame information configuration frame, obtain the LED picture element that actual needs shows coordinate figure (x, y), specific as follows:
The view data of described FPGA main control chip and configuration information processing module are extracted the coordinate figure (x1 of a certain LED picture element the layout information Frame in order from configuration information buffer memory SRAM, y1), then with this coordinate figure (x1, y1) be multiplied by X coordinate amplification coefficient Lx and Y coordinate amplification coefficient Ly respectively, obtain coordinate figure (x2, y2), x2=x1*Lx wherein, y2=y1*Ly, add the coordinate figure in the sectional drawing frame upper left corner in the sectional drawing frame information configuration frame, promptly corresponding to the coordinate figure of the initial point (0,0) of LED layout (x0, y0), thereby obtain the coordinate figure (x of the LED picture element of actual needs demonstration, y), x=x0+x1*Lx wherein, y=y0+y1*Ly.
In the said method, the described network interface sending module of step (9) is read ethernet data frame and is sent to data distributor through network interface circuit among the RAM internally, and the transmission speed of its ethernet data frame is with 100M/S, so that higher transmission rate to be provided.
Described FPGA main control chip program module is described by the hardware description language (VHDL, Very High Speed Integrated Circuit Hardware Description Language) of very high speed integrated circuit.
The present invention has following advantage and effect with respect to prior art:
(1) irregular LED array displaying message frame sending controller of the present invention can be realized the extraction of the display message of LED layout under actual any irregular conditions, and can realize that the user by the X of computer terminal input, the processing of the different magnification ratio coefficients of Y coordinate, can satisfy the large LED lamp decoration control system that is applied to irregular LED cell array layout;
(2) implementation method of the present invention can send to USB interface to sectional drawing frame information configuration frame in real time according to the variation of the real-time sectional drawing frame position information sending module with the different of X, Y coordinate amplification coefficient and by the computer terminal, and finally store among the configuration information buffer memory SRAM, after the FPGA main control chip is handled, can realize that any information of playing on the computer shows in real time, satisfies the demand of different designs scheme in led array;
(3) native system adopts the video interface DVI of total digitalization, it in the whole signals transmission conversion between the digital signal, related just coding, decoding algorithm, ensure the extremely low error rate, digital-to-analogue conversion, expensive ADC have been got around, not only improved picture quality, and further reduced the complexity of circuit, engineering cost is lower.
Description of drawings
Fig. 1 is the structural representation of the LED lamp decoration control system that is made of irregular LED array displaying message frame sending controller of the present invention;
Fig. 2 is the structural representation of irregular LED array displaying message frame sending controller of the present invention;
Fig. 3 is the structural representation of FPGA main control chip;
Fig. 4 is the schematic flow sheet by irregular LED array displaying message frame sending control method of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with embodiment and accompanying drawing, but embodiments of the present invention are not limited thereto.
Embodiment 1
Figure 1 shows that the concrete structure of the irregular LED array lamp decoration control system that constitutes by irregular LED array displaying message frame sending controller of the present invention, comprise irregular LED array displaying message frame sending controller, the computer terminal, the data distributor group, data buffer (differential receiver), the LED light fixture, the DVI data-interface of the DVI/USB data receiver circuit plate of described irregular LED array displaying message frame sending controller, the usb data interface is respectively by the DVI cable, USB cable is connected with the computer terminal, the network interface circuit of the FPGA control circuit board of described irregular LED array displaying message frame sending controller is connected with the data distributor group by super category 5 twisted pair, again with data buffer, the LED light fixture connects successively, wherein, described data distributor group is formed by a plurality of data distributors are connected in series.
Described computer terminal comprises the information sending module that is used to generate the topology file generation module of topology file and is used to send layout information, sectional drawing frame information and user's input information information such as (comprising X coordinate amplification coefficient Lx and Y coordinate amplification coefficient Ly).
The circuit structure of irregular LED array displaying message frame sending controller of the present invention comprises the FPGA control circuit board as main control device that is connected, as the DVI/USB data receiver circuit plate of target device;
As shown in Figure 2, described FPGA control circuit board comprises PPGA main control chip (EP1C6Q240C8), image buffer storage SRAM, configuration information buffer memory SRAM, network interface circuit, power circuit, and described FPGA main control chip is connected with image buffer storage SRAM, configuration information buffer memory SRAM, network interface circuit, power circuit respectively.The screen resolution of the LED lamp decoration control system that irregular LED array displaying message frame sending controller of the present invention constitutes is 1024 * 768, screen refresh rate is 60Hz, the pixel figure place is 24, for guaranteeing the read-write correctly, at a high speed and stably of view data, the FPGA main control chip is peripheral to adopt 4 high speed storing SRAM, comprises SRAM image buffer storage A (512k * 16), SRAM image buffer storage C (512k * 16), SRAM image buffer storage B (512k * 8), SRAM image buffer storage D (512k * 8).
Wherein, DVI/USB data receiver circuit plate comprises DVI data-interface, usb data interface.Wherein, the DVI interface of computer terminal is connected with the DVI data-interface of DVI/USB data receiver circuit plate; The USB interface of computer terminal is connected with the usb data interface of DVI/USB data receiver circuit plate.Simultaneously, the DVI network interface card of computer terminal, DVI interface interconnect.
Described DVI data-interface comprises the DVI decoding circuit, and the DVI decoding circuit comprises DVI decoding chip and peripheral circuits thereof, and peripheral circuits comprises EEPROM and some exclusions of power circuit, storage EDID data.
Described USB receiving interface comprises the chip and the peripheral circuits thereof of ARM7 (can be replaced by other serial ARM chips, as ARM9) kernel, and peripheral circuits comprises power circuit, program download circuit, feeds dog circuit etc.
Figure 3 shows that the concrete structure of PPGA main control chip, the FPGA main control chip comprises DVI data reception module, SPI data reception module, PLL frequency multiplication module, view data and configuration information processing module, internal RAM module, network interface sending module.Wherein, described DVI data reception module, SPI data reception module also respectively with the above-mentioned corresponding connection of image buffer storage SRAM, configuration information buffer memory SRAM.Simultaneously, described view data and configuration information processing module are connected with DVI data reception module, SPI data reception module, PLL frequency multiplication module, internal RAM module, network interface sending module and above-mentioned image buffer storage SRAM, configuration information buffer memory SRAM respectively, PLL frequency multiplication module is connected with DVI data reception module, SPI data reception module simultaneously, the internal RAM module is connected with the network interface sending module simultaneously, and the network interface sending module is connected the back and is connected with the data distributor group with network interface circuit.
Simultaneously, described SPI data reception module comprises the SPI string that is connected and modular converter, SPI data memory module.
The DVI data-interface of described DVI/USB data receiver circuit plate, usb data interface are connected with the FPGA main control chip simultaneously.Specifically, the DVI data-interface of DVI/USB data receiver circuit plate, usb data interface are gone here and there and the corresponding connection of modular converter with DVI data reception module, the SPI of FPGA main control chip respectively.
Described DVI data reception module is provided with clock port, the image synchronization control port, the effective port of image, the view data input port, external SRAM control signal port, external SRAM data/address port, described SPI data reception module is provided with the SPI clock port, the SPI FPDP, external SRAM control signal port, external SRAM data/address port, USB ready signal port, described view data and configuration information processing module are provided with clock port, external SRAM data/address read write port is arranged, internal RAM data write port, frame data are prepared port, the control signal port.Above DVI data reception module, the SPI data reception module, view data is connected according to following form with the configuration information processing module, described DVI data reception module, the clock port of view data and configuration information processing module is connected with the 65MHz clock of process PLL frequency multiplication module respectively, the SPI clock port of described SPI data reception module connects the 25MHz clock through PLL frequency multiplication module, DVI data reception module, the write data enable port (WE) of the SRAM of SPI data reception module and output enable port (OE) respectively the alternative multiway analog switch (MUX) by view data and configuration information processing module to image buffer storage SRAM, configuration information buffer memory SRAM controls.The SRAM data-signal port (data) of DVI data reception module, SPI data reception module and address signal port (address) are also controlled image buffer storage SRAM, configuration information buffer memory SRAM by this alternative multiway analog switch (MUX) respectively.
Above-mentioned irregular LED array displaying message frame sending controller realizes that irregular LED array displaying message frame sends the method for control, as shown in Figure 4, may further comprise the steps:
(1) the topology file generation module of computer terminal generates the led array layout according to any irregular layout situation of actual light fixture, thereby and X, the Y coordinate figure of each picture element of storage led array obtain the topology file of suffix 1mp by name;
(2) information sending module of computer terminal generates the layout information Frame that comprises each LED picture element X, Y coordinate figure according to topology file, and information sending module sends to the layout information Frame by the USB interface of computer terminal the usb data interface of DVI/USB data receiver circuit plate then;
(3) information sending module of computer terminal generates sectional drawing frame information configuration frame according to the position and the user's input information of sectional drawing frame, this user's input information comprises X coordinate amplification coefficient Lx and Y coordinate amplification coefficient Ly, by the USB interface of computer terminal sectional drawing frame information configuration frame is sent to the usb data interface of DVI/USB data receiver circuit plate then;
(4) computer terminal sends to computer desktop color of image data the DVI data-interface of DVI/USB data receiver circuit plate by the DVI interface by the DVI standard;
(5) the DVI data reception module of FPGA main control chip receives computer desktop color of image data and stores into the image buffer storage SRAM from the DVI data-interface of DVI/USB data receiver circuit plate;
(6) the usb data receiver module of FPGA main control chip receives layout information Frame, sectional drawing frame information configuration frame and stores into the configuration information buffer memory SRAM from the usb data interface of DVI/USB data receiver circuit plate;
(7) view data of FPGA main control chip and configuration information processing module are extracted the coordinate figure (x1 of a certain LED picture element the layout information Frame in order from configuration information buffer memory SRAM, y1), then with this coordinate figure (x1, y1) be multiplied by X coordinate amplification coefficient Lx respectively and Y coordinate amplification coefficient Ly obtains coordinate figure (x2, y2), x2=x1*Lx wherein, y2=y1*Ly, the coordinate figure of adding the sectional drawing frame upper left corner in the sectional drawing frame information configuration frame is (promptly corresponding to the coordinate figure (x0, y0)) of the initial point (0,0) of LED layout, obtain the coordinate figure (x of the LED picture element of actual needs demonstration, y), x=x0+x1*Lx wherein, y=y0+y1*Ly;
(8) coordinate figure (x of the LED picture element that shows according to actual needs of the view data of FPGA main control chip and configuration information processing module, y), from image buffer storage SRAM, extract corresponding computer desktop color of image data, judge then whether a frame Ethernet data runs through, if run through, then the corresponding layout information of combination is assembled into ethernet data frame and stores in the internal RAM; If do not run through, repeating step (7) then;
(9) described network interface sending module is read ethernet data frame and is sent to data distributor through network interface circuit among the RAM internally, judges that then sectional drawing frame configuration information has no change, if change, then repeating step (3) is to step (9); If do not change, then repeating step (6) is to step (9);
(10) data distributor constantly repeats to receive ethernet data frame, and information extraction produces pwm control signal driving LED light fixture from ethernet data frame.
In the said method, the clock that DVI Data Receiving plate offers FPGA is 65MHz, and the clock of PLL frequency multiplication module generation 130MHz provides operating clock for each functional module of FPGA, with storage and the processing operation that makes things convenient for view data.
In the said method, the described computer desktop color of image of step (1) data comprise R, G, the trichromatic pixel data of B.
In the said method, the described computer desktop color of image of step (4) data are continual, real-time operations by the operation that the DVI interface sends to the DVI data-interface of DVI/USB data receiver circuit plate, walk abreast with other each steps, be not subjected to the influence of other each step operations.In the said method, adopt ping-pong operation performing step (4) and the parallel of other each steps to carry out.
In the said method, the described network interface sending module of step (9) is read ethernet data frame and is sent to data distributor through network interface circuit among the RAM internally, and the transmission speed of its ethernet data frame is with 100M/S, so that higher transmission rate to be provided.
Described FPGA main control chip program module is described by the hardware description language (VHDL, Very High Speed Integrated Circuit Hardware Description Language) of very high speed integrated circuit.
Among the present invention, it is the on-site programmable gate array FPGA (Field Programmable Gate Array) of EP1C6Q240 that the FPGA main control chip adopts the model of the Cyclone series of a slice altera corp.This a FPGA power supply is 3.3V and 1.5V, nearly 185 in available I/O mouth.Data storage (SRAM) is IS61LV51216, IS61LV5128, the IS61LV10248 of ISSI company.Network interface chip adopts the RTL8021CL chip of Realtek company, and Realtek RTL8201CL is the physical layer transceiver of a single port, has realized whole 10/100M ethernet physical layer functions.The DVI decoding chip adopts a kind of TMDS signal receiving chip TFP101A in the TI PaneIBus of the company flat panel display product series, supports XGA (1024x768@80Hz), and pixel clock is up to 86MHz; Support 24 true color, have the characteristic of low noise and low-power consumption.Adopt the LPC214x high performance chips of PHILIPS company based on the chip of ARM7 kernel, its greatest feature has been built-in USB2.0 is controller at full speed.
The program implement of described FPGA main control chip is as follows:
1, with Hardware Description Language VHDL circuit system is described;
2, the integrated circuit (IC) design integrated software QuartusII with altera corp carries out comprehensively the hardware circuit that VHDL describes, and obtaining with the model of altera corp is the corresponding net meter file of FPGA of EP1C6Q240;
3, carry out placement-and-routing and extraction delayed data;
4, carry out sequential emulation;
5, with QuartusII hardware configuration information is downloaded on the above-mentioned FPGA (model EP1C6Q240).As mentioned above, just can realize the present invention preferably.
Claims (9)
1, irregular LED array displaying message frame sending controller is characterized in that: comprise the FPGA control circuit board as main control device that is connected, as the DVI/USB data receiver circuit plate of target device;
Wherein, described FPGA control circuit board comprises image buffer storage SRAM, configuration information buffer memory SRAM, network interface circuit, the power circuit that FPGA main control chip and described FPGA main control chip connect respectively;
Described DVI/USB data receiver circuit plate comprises DVI data-interface, usb data interface, and described DVI data-interface, usb data interface are connected with the FPGA main control chip of described FPGA control circuit board respectively.
2, according to the described irregular LED array displaying message frame sending controller of claim 1, it is characterized in that: described FPGA main control chip comprises DVI data reception module, SPI data reception module, PLL frequency multiplication module, view data and configuration information processing module, internal RAM module, network interface sending module; Wherein, described DVI data reception module, the SPI data reception module also respectively with image buffer storage SRAM, configuration information buffer memory SRAM is corresponding to be connected, described view data and configuration information processing module respectively with the DVI data reception module, the SPI data reception module, PLL frequency multiplication module, the internal RAM module, network interface sending module and above-mentioned image buffer storage SRAM, configuration information buffer memory SRAM is connected, PLL frequency multiplication module while and DVI data reception module, the SPI data reception module connects, the internal RAM module is connected with the network interface sending module simultaneously, and the network interface sending module is connected with network interface circuit.
3, according to the described irregular LED array displaying message frame sending controller of claim 2, it is characterized in that: described SPI data reception module comprises the SPI string that is connected and modular converter, SPI data memory module.
4, adopt the irregular LED array lamp decoration control system of the described irregular LED array displaying message frame sending controller of claim 3, it is characterized in that: comprise irregular LED array displaying message frame sending controller, the computer terminal, the data distributor group, data buffer, the LED light fixture, the DVI data-interface of the DVI/USB data receiver circuit plate of described irregular LED array displaying message frame sending controller, the usb data interface is respectively by the DVI cable, USB cable is connected with the computer terminal, the network interface circuit of the FPGA control circuit board of described irregular LED array displaying message frame sending controller is connected with the data distributor group by super category 5 twisted pair, again with data buffer, the LED light fixture connects successively, wherein, described data distributor group is formed by a plurality of data distributors are connected in series.
5, according to the described irregular LED array lamp decoration of claim 4 control system, it is characterized in that: described computer terminal comprises and is used to generate the topology file generation module of topology file and the information sending module that is used to send layout information, sectional drawing frame information and user's input information.
6, according to the described irregular LED array lamp decoration of claim 5 control system, it is characterized in that: the information of described user's input comprises X coordinate amplification coefficient Lx and Y coordinate amplification coefficient Ly.
7, utilize the irregular LED array lamp decoration control method of each described irregular LED array lamp decoration control system of claim 4 to 6, it is characterized in that may further comprise the steps:
(1) the topology file generation module of computer terminal generates the led array layout according to any irregular layout situation of actual light fixture, thereby and X, the Y coordinate figure of each picture element of storage led array obtain the topology file of suffix 1mp by name;
(2) information sending module of computer terminal generates the layout information Frame that comprises each LED picture element X, Y coordinate figure according to topology file, and information sending module sends to the layout information Frame by the USB interface of computer terminal the usb data interface of DVI/USB data receiver circuit plate then;
(3) information sending module of computer terminal generates sectional drawing frame information configuration frame according to the position and the user's input information of sectional drawing frame, this user's input information comprises X coordinate amplification coefficient Lx and Y coordinate amplification coefficient Ly, by the USB interface of computer terminal sectional drawing frame information configuration frame is sent to the usb data interface of DVI/USB data receiver circuit plate then;
(4) computer terminal sends to computer desktop color of image data the DVI data-interface of DVI/USB data receiver circuit plate by the DVI interface by the DVI standard;
(5) the DVI data reception module of FPGA main control chip receives computer desktop color of image data and stores into the image buffer storage SRAM from the DVI data-interface of DVI/USB data receiver circuit plate;
(6) the usb data receiver module of FPGA main control chip receives layout information Frame, sectional drawing frame information configuration frame from the usb data interface of DVI/USB data receiver circuit plate, and stores among the configuration information buffer memory SRAM;
(7) view data of FPGA main control chip and configuration information processing module are handled described layout information Frame, sectional drawing frame information configuration frame, obtain the LED picture element that actual needs shows coordinate figure (x, y);
(8) coordinate figure (x of the LED picture element that shows according to actual needs of the view data of FPGA main control chip and configuration information processing module, y), from image buffer storage SRAM, extract corresponding computer desktop color of image data, judge then whether frame data run through, if run through, then the corresponding layout information of combination is assembled into ethernet data frame and stores in the internal RAM; If do not run through, repeating step (7) then;
(9) described network interface sending module is read ethernet data frame and is sent to data distributor through network interface circuit among the RAM internally, judges that then sectional drawing frame configuration information has no change, if change, then repeating step (3) is to step (9); If do not change, then repeating step (6) is to step (9);
(10) data distributor constantly repeats to receive ethernet data frame, and information extraction produces pwm control signal driving LED light fixture from ethernet data frame.
8, irregular LED array displaying message frame sending control method according to claim 7 is characterized in that: the described computer desktop color of image of step (1) data comprise R, G, the trichromatic pixel data of B.
9, irregular LED array displaying message frame sending control method according to claim 7, it is characterized in that: the view data of the described FPGA main control chip of step (7) and configuration information processing module are handled described layout information Frame, sectional drawing frame information configuration frame, obtain the coordinate figure (x of the LED picture element of actual needs demonstration, y), specific as follows:
The view data of described FPGA main control chip and configuration information processing module are extracted the coordinate figure (x1 of a certain LED picture element the layout information Frame in order from configuration information buffer memory SRAM, y1), then with this coordinate figure (x1, y1) be multiplied by X coordinate amplification coefficient Lx and Y coordinate amplification coefficient Ly respectively, obtain coordinate figure (x2, y2), x2=x1*Lx wherein, y2=y1*Ly, add the coordinate figure in the sectional drawing frame upper left corner in the sectional drawing frame information configuration frame, promptly corresponding to the coordinate figure of the initial point (0,0) of LED layout (x0, y0), thereby obtain the coordinate figure (x of the LED picture element of actual needs demonstration, y), x=x0+x1*Lx wherein, y=y0+y1*Ly.
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| US6224216B1 (en) * | 2000-02-18 | 2001-05-01 | Infocus Corporation | System and method employing LED light sources for a projection display |
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