CN104282341B - Microdisplay on silicon integrates asynchronous transmission shift-register circuit and implementation method - Google Patents

Abstract

A silicon-based microdisplay integrated asynchronous transmission shift register circuit and its realization method. The integrated asynchronous transmission shift register circuit (composed of M x N data shift transmission unit circuits, M and N represent column resolution and row resolution respectively), can be used for liquid crystal on silicon microdisplay (LCoS), silicon OLED Micro-display (OLEDoS) and other silicon-based micro-display devices and other fields, row-scanning shift registers and column-scanning shift registers for silicon-based micro-displays. Each data shift transmission unit circuit is composed of a D flip-flop, an OR gate with two inverting inputs, a NOR gate with two inputs, a transmission gate TGA and a transmission gate TGB. In the asynchronous transmission shift register circuit provided by the present invention, each unit starts the bidirectional working clock after the input data arrives, and turns off the bidirectional working clock after the data output of the current level becomes low level, thereby effectively reducing the frequency of scanning the shift register. Dynamic power consumption of the circuit.

Description

Silicon-based microdisplay integrated asynchronous transmission shift register circuit and implementation method

technical field

The invention relates to the fields of flat panel display technology, helmet display technology, intelligent video glasses, etc., and in particular to a structure of a silicon-based liquid crystal micro-display device, a silicon-based organic light-emitting micro-display device and a realization method thereof.

Background technique

Silicon-based microdisplay technology is a new type of display technology developed in recent years, including silicon-based liquid crystal LCoS and silicon-based organic light-emitting device OLEDoS. Wearable electronic devices, virtual reality, video glasses, micro-projection displays and other portable mobile information display fields have a very wide range of applications.

The silicon-based microdisplay is the same as the traditional flat-panel display, the display pixels are distributed in a matrix, and the scanning structure of row by row and column by active addressing is used to drive the pixels for information display. In this structure, in order to realize the row by row by column scan, The row shift register and the column shift register are set according to the resolution of the display. The current row shift register and column shift register adopt the working mechanism of serial input and parallel output. The parallel output terminal of the row shift register only outputs a high level at a time, and drives the gate level of the corresponding row of pixels for Image data is written into the pixel circuits of the row. In the same principle, only one parallel output terminal of the column shift register outputs a high level at a time to drive the data line of the corresponding column pixel, thereby completing the writing of display data on one pixel. In this scanning process, in each clock cycle, although only one unit circuit of the M-level or N-level shift register outputs a high level, all the unit circuits that output a low level are in a flip state, and all Flipping unit circuits will generate dynamic power consumption.

The invention proposes a silicon-based microdisplay integrated asynchronous transmission shift register circuit, adopts CMOS technology, and integrates with a silicon-based microdisplay chip, does not increase the volume and cost of the microdisplay application system, has high working reliability, and can be applied to various On-chip scan circuit for low-power silicon-based microdisplays.

Contents of the invention

The purpose of the present invention is to solve the problem of large dynamic power consumption of the internal high-speed scanning drive circuit of the silicon-based microdisplay, and provide a silicon-based microdisplay integrated asynchronous transmission shift register circuit and its implementation method for low-power asynchronous data transmission. The circuit structure It can be started to work when the output of the previous stage circuit is high level, and after the current stage circuit outputs high level data, the clock of the current stage circuit is disconnected, so as to avoid the power consumption caused by the flipping of the circuit.

The present invention firstly provides a data shift transmission unit circuit that constitutes a silicon-based microdisplay integrated asynchronous transmission shift register circuit, the unit circuit includes:

D flip-flop, two-inverted input OR gate, two-input NOR gate, transmission gate TGA and transmission gate TGB circuit; the data input end of the D flip-flop is connected together with one input end of the two-input NOR gate circuit , and connected to the single data output end of the pre-stage unit, the positive-phase clock input end CK of the D flip-flop is connected to the output end of the transmission gate TGB, and the inverting clock input end BCK of the D flip-flop is connected to the output end of the transmission gate TGA The non-inverting output terminal Q of the D flip-flop is connected to the data input terminal of the next stage, and is connected to the other input terminal of the two-input NOR gate circuit, and the inverting output terminal BQ of the D flip-flop is used as the inverting phase of the current stage. The output terminal is connected to one input terminal of the two inverting input or gates, and the other input terminal of the two inverting input or gates is connected to the inverting output terminal of the previous unit circuit; the D flip-flop bidirectional clock is transmitted Work under the control of the gates TGA and TGB; the transmission gates TGA and TGB have three input terminals, the inverting control input terminals of the transmission gates TGA and TGB are connected together, and connected with the output terminal of the two-input NOR gate; the transmission gate TGA It is connected with the positive phase control input terminal of TGB, and connected with the output terminal of the two inverting input OR gates; the signal input terminal of the transmission gate TGA is connected with the BGVCK or BGHCK of the external global bidirectional clock signal, and the signal input terminal of the transmission gate TGB The terminal is connected to GVCK or GHCK of the external global bidirectional clock signal.

The silicon-based microdisplay integrates an asynchronous transmission shift register unit circuit. In the row scanning shift register circuit, the signal input terminal of the transmission gate TGA is connected with the BGVCK of the external global bidirectional clock signal, and the signal input terminal of the transmission gate TGB is connected with the BGVCK of the external global bidirectional clock signal. The GVCK of the external global bidirectional clock signal is connected. In the column scanning shift register circuit, the signal input terminal of the transmission gate TGA is connected with the BGHCK of the external global bidirectional clock signal, and the signal input terminal of the transmission gate TGB is connected with the GHCK of the external global bidirectional clock signal. The output terminal of the transmission gate TGA is connected with the inverting clock input terminal BCK of the D flip-flop, and the output terminal of the transmission gate TGB is connected with the non-phase clock input terminal CK of the D flip-flop.

The present invention simultaneously provides a silicon-based microdisplay integrated asynchronous transmission shift register circuit composed of the above-mentioned data shift transmission unit circuit, and the integrated asynchronous transmission shift register circuit is composed of M x N data shift transmission units Circuit composition, where M and N represent the column resolution and row resolution of the silicon-based microdisplay, respectively.

In the N row scanning data shift transmission unit circuits, the data input end of the first unit circuit is connected with the external field synchronous signal VS, and is connected with the input end of the field synchronous inverter at the same time, and the field synchronous inverter The output end of the two inverting input or gates is connected to one input end; the data input ends of each subsequent data shift transmission unit circuit are connected to the data output ends of the previous unit circuits; the other of the two inverting input or gates One input terminal is connected with the inverting output terminal of the current stage to form an N-stage row scanning shift register circuit of the silicon-based microdisplay.

In the M column scanning data shift transmission unit circuits, the data input terminal of the first unit circuit is connected with the external horizontal synchronous signal HS, and is connected with the input terminal of the horizontal synchronous inverter at the same time, and the horizontal synchronous inverter The output terminal of the two inverting input or gates is connected to one input terminal; the data input terminals of each subsequent data shift transmission unit circuit are connected to the data output terminals of the previous unit circuits; the other of the two inverting input or gates One input terminal is connected with the inverting output terminal of the current stage to form an M-stage column scanning shift register circuit of the silicon-based microdisplay.

The dual-phase clock signals of each unit circuit of the M-level column scanning circuit shift register are connected together respectively, the positive-phase clock signal is connected with GHCK, and the reverse-phase clock signal is connected with BGHCK; the N-level row scanning circuit shift The two-phase clock signals of each unit circuit of the bit register are respectively connected together, the positive-phase clock signal is connected to GVCK, and the negative-phase clock signal is connected to BGVCK.

The invention proposes a silicon-based microdisplay integrated asynchronous transmission shift register circuit, each unit circuit is provided with a clock control circuit, when a certain unit circuit needs to output a high level to open the corresponding pixel gate or data line, the unit circuit It can be activated automatically to complete the function of outputting high level and transmitting the high level signal to the next stage. When all the unit circuits in flipping state are in the non-working state because there is no clock signal, the dynamic power consumption of the active addressing and scanning circuit will be greatly saved. For high-resolution silicon-based microdisplays, only the shift register of all on-chip circuits is in the high-speed flip working state, and the dynamic power consumption is the largest. The overall power consumption of the chip, when applied to portable battery-powered devices such as wearables, video glasses, and micro-projectors, can improve the battery life of the device.

The realization method of the integrated asynchronous transmission shift register circuit function provided by the present invention, through the following steps successively:

First, using CMOS technology to integrate M x N above-mentioned data shift transmission unit circuits and silicon-based microdisplays on one chip;

Second, after the silicon-based microdisplay receives the video signal, the field synchronous signal VS is active at a high level, and is added to the data input end of the D flip-flop 3 of the first-level unit circuit 8 of the N-level line scanning shift register circuit, so that the transmission Gates TGA5 and TGB2 inverting control input terminals are at low level, and at the same time, field synchronous inverter 6 outputs low level, driving two inverting inputs or gate 4 outputs high level, so that transmission gates TGA5 and TGB2 positive phase control input terminals is high level, the transmission gates TGA5 and TGB2 are in the open state, when the clock arrives, the data output terminal of this stage outputs high level, and its reverse output terminal is low level.

Third, in the second global clock cycle, the data input terminal of the D flip-flop 3 of the current stage becomes low level, the positive phase output terminal is high level, and the reverse output terminal is low level. After the two-input NOR gate 1 and the two-inverting input OR gate 4, the driving transmission gates TGA5 and TGB2 are always in the open state, and the global bidirectional clock signal will make the D flip-flop 3 flip to the low level of the non-inverting output terminal, and the inverting The output is high in steady state.

Fourth, because the data output of the previous stage and the data output of the current stage are both low level, and the inverting output of the previous stage and the inverting output of the current stage are both high level, so the transmission gates TGA5 and TGB2 are in the closed state, and the D flip-flop 3 in sleep wait state.

Fifth, the high level output by the data output terminal of the first stage unit circuit (8) is added to the D flip-flop (3 ) to the data input terminal of the unit circuit (8) to repeat the working process of the second to fourth steps of the first-level unit circuit (8), and sequentially transmit a high-level pulse to the data input terminal of each unit circuit at the following level to complete a Line scanning process of frame image;

Sixth, during the period when a certain level unit circuit 10 of the N-level line scanning shift register circuit outputs a high level, the corresponding horizontal synchronous signal HS is high level, and is added to the M level column scanning shift register circuit. The data input terminal of the D flip-flop 3 in the primary unit circuit 9 . Repeat the previous second to fifth steps, and the data shift transmission unit circuit 9 of the M-level row scan shift register circuit sequentially transmits the high level to complete the column scan process of a row of images.

Advantages and positive effects of the present invention

The integrated asynchronous transmission shift register circuit provided by the invention can reduce somersaults of the high-speed scanning shift register circuit inside the silicon-based micro-display chip, thereby greatly reducing the dynamic power consumption of the silicon-based micro-display chip. For wearable displays such as helmet-mounted displays and smart video glasses, battery life can be extended, and it can reduce the heating of head-mounted video displays, making people feel more comfortable when wearing such displays. It can be applied to on-chip scanning driving circuits of silicon-based liquid crystal display devices, silicon-based organic display devices, etc., and has great application prospects.

Description of drawings

Fig. 1 is a circuit junction diagram of a silicon-based microdisplay integrated asynchronous transmission shift register data shift transmission unit;

Fig. 2 is the structural diagram of the first-level unit circuit of the N-level row scanning shift register circuit;

Fig. 3 is the structural diagram of the first-level unit circuit of the M-level column scanning shift register circuit;

Fig. 4 is a block diagram of M x N stage shift register circuit structure;

Fig. 5 is a working signal waveform diagram of the asynchronous transmission shift register data shift transmission unit circuit.

detailed description

Embodiment 1. A silicon-based microdisplay integrated asynchronous transmission shift register circuit

As shown in Figure 1, a kind of silicon-based microdisplay integrated asynchronous transmission shift register circuit provided by the present invention includes:

M x N asynchronous transmission shift register unit circuits 10 (see FIG. 4 ), where M and N represent the column resolution and row resolution of silicon-based microdisplays, and each asynchronous transmission shift register unit circuit 10 includes a D trigger device 3, two-inverting-input OR gate 4, two-input NOR gate 1, transmission gate TGA5 and transmission gate TGB2. The data input terminal of the D flip-flop 3 is connected with one input terminal of the two-input NOR gate 1, and is connected with the data output terminal of the previous stage, and the positive-phase clock input terminal CK of the D flip-flop 3 is connected with the output terminal of the transmission gate TGB2 The inverting clock input terminal BCK of the D flip-flop 3 is connected to the output terminal of the transmission gate TGA5, the non-inverting output terminal Q of the D flip-flop 3 is connected to the data input terminal of the next stage, and is connected with the two-input NOR gate 1 The other input terminal of the D flip-flop 3 is connected to the other input terminal, and the inverting output terminal BQ of the D flip-flop 3 is used as the inverting output terminal of the current stage, and is connected with one input terminal of the two inverting input OR gate 4, and the other of the two inverting input OR gate 4 The input terminal is connected with the inverting output terminal of the preceding unit circuit.

The silicon-based microdisplay integrates the D flip-flop 3 of the asynchronous transmission shift register unit circuit 10, and its bidirectional clock works under the control of transmission gates TGA5 and TGB2. Both transmission gates TGA5 and TGB2 have three input terminals, and transmission gate TGA5 It is connected with the inverting control input terminal of TGB2, and connected with the output terminal of the two-input NAND gate 1, and the positive-phase control input terminal of the transmission gate TGA5 and TGB2 is connected together, and connected with the two-inverted input OR gate 4 The output terminals are connected. In the row scanning shift register circuit, the signal input terminal of the transmission gate TGA5 is connected with the BGVCK of the external global bidirectional clock signal, and the signal input terminal of the transmission gate TGB2 is connected with the GVCK of the external global bidirectional clock signal. In the shift register circuit, the signal input terminal of the transmission gate TGA is connected to the BGHCK of the external global bidirectional clock signal, the signal input terminal of the transmission gate TGB is connected to the GHCK of the external global bidirectional clock signal, and the output terminal of the transmission gate TGA5 is connected to the D flip-flop The inverting clock input terminal BCK of 3 is connected, and the output terminal of transmission gate TGB2 is connected with the non-phase clock input terminal CK of D flip-flop 3 .

The N row scanning data shift transmission unit circuits 10, wherein the data input end of the first unit circuit 8 is connected with the external field synchronous signal VS, and is connected with the input end of the field synchronous inverter 6 at the same time, and the field synchronous The output end of the inverter 6 is connected with an input end of two inverting input OR gates 4; the data input ends of each data shift transmission unit circuit 10 thereafter are all connected with the data output ends of the previous unit circuits 10; N-level line scan shift register circuit for basic microdisplay.

The M column scanning data shift transmission unit circuits 10, wherein the data input terminal of the first unit circuit 9 is connected with the external horizontal synchronous signal HS, and is connected with the input terminal of the horizontal synchronous inverter 7 at the same time, and the horizontal synchronous The output end of the inverter 7 is connected with an input end of two inverting input OR gates 4; the data input ends of each data shift transmission unit circuit 10 thereafter are all connected with the data output ends of the front unit circuit 10; M-level column scan shift register circuit for base microdisplay.

The two-phase clock signals of each unit circuit 10 of the M-level column scanning circuit shift register are connected together respectively, the positive-phase clock signal is connected with GHCK, and the anti-phase clock signal is connected with BGHCK; the N-level row scanning circuit The bi-phase clock signals of each unit circuit 10 of the shift register are respectively connected together, the positive phase clock signal is connected to GVCK, and the negative phase clock signal is connected to BGVCK.

Embodiment 2. A realization method of a silicon-based microdisplay integrated asynchronous transmission shift register circuit

A method for realizing the function of a silicon-based microdisplay integrated asynchronous transmission shift register circuit provided by the present invention, through the following steps in sequence:

First, using CMOS technology to integrate M x N above-mentioned data shift transmission unit circuits and silicon-based microdisplays on one chip;

Second, after the silicon-based microdisplay receives the video signal, the field synchronous signal VS is active at a high level, and is added to the data input end of the D flip-flop 3 of the first-level unit circuit 8 of the N-level line scanning shift register circuit, so that the transmission Gates TGA5 and TGB2 inverting control input terminals are at low level, and at the same time, field synchronous inverter 6 outputs low level, driving two inverting inputs or gate 4 outputs high level, so that transmission gates TGA5 and TGB2 positive phase control input terminals is high level, the transmission gates TGA5 and TGB2 are in the open state, when the clock arrives, the data output terminal of this stage outputs high level, and its reverse output terminal is low level.

Third, in the second global clock cycle, the data input terminal of the D flip-flop 3 of the current stage becomes low level, the positive phase output terminal is high level, and the reverse output terminal is low level. After the two-input NOR gate 1 and the two-inverting input OR gate 4, the driving transmission gates TGA5 and TGB2 are always in the open state, and the global bidirectional clock signal will make the D flip-flop 3 flip to the low level of the non-inverting output terminal, and the inverting The output is high in steady state.

Fourth, because the data output of the previous stage and the data output of the current stage are both low level, and the inverting output of the previous stage and the inverting output of the current stage are both high level, so the transmission gates TGA5 and TGB2 are in the closed state, and the D flip-flop 3 in sleep wait state.

Fifth, the high level output by the data output terminal of the first stage unit circuit (8) is added to the D flip-flop (3 ) to the data input terminal of the unit circuit (8) to repeat the working process of the second to fourth steps of the first-level unit circuit (8), and sequentially transmit a high-level pulse to the data input terminal of each unit circuit at the following level to complete a Line scanning process of frame image;

Sixth, during the period when a certain level unit circuit 10 of the N-level line scanning shift register circuit outputs a high level, the corresponding horizontal synchronous signal HS is high level, and is added to the M level column scanning shift register circuit. The data input terminal of the D flip-flop 3 in the primary unit circuit 9 . Repeat the first to fourth steps above, and the data shift transmission unit circuit 9 of the M-level row scan shift register circuit sequentially transmits the high level to complete the column scan process of a row of images.

The above steps are performed cyclically to complete the display scanning of the pixel matrix of the silicon-based micro-display device.

Embodiment 3, the first stage of N-stage row scanning shift register circuit

As shown in Figure 2, the silicon-based microdisplay line scan shift register circuit composed of N line scan data shift transmission unit circuits 10 is started to work by the field synchronous signal VS, and its first stage data shift There is no previous-stage unit circuit in front of the bit transfer unit circuit 8 . The first stage of the line scan shift register circuit is provided with a field synchronous inverter 6, the input end of the field synchronous inverter 6 is connected with the external field synchronous signal input end and the data input end of the D flip-flop 3, and the field synchronous inverter The output terminal of the phaser 6 is connected with one input terminal of the OR gate 4 with two inverting inputs. When the field synchronous signal VS high level arrives, the output of the two-input NOR gate 1 is low level, the output terminal of the field synchronous inverter 6 is also low level, and the output terminal of the two inverting input OR gate 4 is high level Level, so the transmission gates TGA5 and TGB2 are in the open state, the global bidirectional clocks GVCK and BGVCK will make the D flip-flop 3 work through the transmission gates TGA5 and TGB2, and a high-level pulse will be sent to the positive phase data output of the D flip-flop 3 Transfer to the second-level unit circuit of the N-level line scanning shift register circuit, and the data input terminals of each subsequent data shift transmission unit circuit 10 are connected to the data output terminals of the previous unit circuits to complete the silicon-based microdisplay line scanning function of the shift register.

Embodiment 4, the first stage of the M-stage column scanning shift register circuit

As shown in Figure 3, the silicon-based microdisplay column scan shift register circuit composed of M column scan data shift transmission unit circuits 10 is started to work by the row synchronization signal HS, and its first stage data shift There is no previous-stage unit circuit in front of the bit transfer unit circuit 9 . The first stage of the column scanning shift register circuit is provided with a row synchronous inverter 7, and the input end of the row synchronous inverter 7 is connected with the external row synchronous signal input end and the data input end of the D flip-flop 3, and the row synchronous inverter The output terminal of the phaser 7 is connected with one input terminal of the OR gate 4 with two inverting inputs. After the high level of the horizontal synchronous signal arrives, the output of the two-input NOR gate 1 is low level, the output terminal of the horizontal synchronous inverter 7 is also low level, and the output terminal of the two inverting input OR gate 4 is high level Therefore, the transmission gates TGA5 and TGB2 are in the open state, and the global bidirectional clocks GHCK and BGHCK will make D flip-flop 3 work through the transmission gates TGA5 and TGB2, and a high-level pulse will be transmitted at the positive phase data output of D flip-flop 3 To the second-level unit circuit of the M-level column scan shift register circuit, the data input terminals of each subsequent data shift transmission unit circuit 10 are connected to the data output terminals of the previous unit circuits to complete the column scan shift of the silicon-based microdisplay. The function of the bit register.

Embodiment 5, M x N stage shift register circuit

As shown in FIG. 4 , the M×N stage shift register circuit is divided into an M stage column scanning shift register circuit and an N stage row scanning shift register circuit. The M-level column scan shift register circuit works under the control of the line synchronization signal HS, the global line scan positive phase clock GHCK and the global line scan inversion clock BGHCK; the N level line scan shift register circuit works under the control of the field synchronization signal VS, global field scan It works under the control of the positive phase clock GVCK and the global field scan negative phase clock BGVCK.

The above-mentioned M and N are the resolution of the silicon-based microdisplay. If M=1920 and N=1080, the resolution of the silicon-based microdisplay is 1920x1080. When M and N are set to other values, the silicon-based microdisplay The resolution is M x N. The N-level row scanning shift register circuit is composed of 1-N data shift transmission unit circuits 10, which respectively constitute the 1-N stages of the row scanning shift register circuit; the M-level column scanning shift register circuit It is composed of 1-M data shift transmission unit circuits 10, which respectively constitute 1-M stages of the column scanning shift register circuit.

The output of each level of data shift transmission unit circuit 10 of the N-level row scanning shift register circuit drives the gate of a row of pixels of the silicon-based microdisplay; each of the M-level column scanning shift register circuits The output of the first-level data shift transmission unit circuit 10 drives the data lines of a row of pixels of the silicon-based microdisplay.

As shown in Figure 4, the two-phase clock signals of each unit circuit 10 of the described N-level line scanning circuit shift register are all connected together respectively, and the positive phase clock signal is connected to GVCK, and the reverse phase clock signal is connected to BGVCK; The dual-phase clock signals of each unit circuit 10 of the M-level column scanning circuit shift register are respectively connected together, the positive-phase clock signal is connected to GHCK, and the negative-phase clock signal is connected to BGHCK.

For the working timing of each unit circuit of the M-level column scan shift register circuit, as shown in Figure 5, when the data input end of the current level is at a high level, the D flip-flop 3 is in the working state, and the data output of the current level is Terminal Q outputs a high level, and the width of this high level is equal to one period of the global biphase column scanning clock signals GHCK and GBHCK. Only in this global clock cycle, D flip-flop 3 is in normal working state. After the two CK signals, both the data input terminal and the data output terminal of the current stage are at low level, and the transmission gates TGA5 and TGB2 are in the closed state. In other global clock cycles, the clock input terminal signal CK of D flip-flop 3 remains Low, in sleep state, which reduces dynamic power consumption.

Claims (6)

1. a silicon-based microdisplay integrated data shift transmission unit circuit in the asynchronous transmission shift register circuit, it is characterized in that this unit circuit comprises: D flip-flop, two-inverted input OR gate, two-input NOR gate, transmission gate TGA and transmission gate TGB circuit; the data input end of the D flip-flop is connected together with one input end of the two-input NOR gate, And it is connected with the data output terminal of the front-stage unit circuit, the positive-phase clock input terminal CK of the D flip-flop is connected with the output terminal of the transmission gate TGB, and the inverting clock input terminal BCK of the D flip-flop is connected with the output terminal of the transmission gate TGA, The non-inverting output terminal Q of the D flip-flop is used as the data output terminal of the current stage, and is connected with the other input terminal of the two-input NOR gate, and the inverting output terminal BQ of the D flip-flop is used as the inverting output terminal of the current stage, and is connected with the other input terminal of the two-input NOR gate. One input end of the inverting input OR gate is connected, and the other input end of the two inverting input OR gates is connected with the inverting output end of the single path of the previous stage unit; the bidirectional clock of the D flip-flop is connected between the transmission gates TGA and TGB Work under control; both transmission gates TGA and TGB have three input terminals, the inverting control input terminals of transmission gates TGA and TGB are connected together, and connected with the output terminal of the two-input NOR gate; the positive phase of transmission gates TGA and TGB The control input terminals are connected together and connected with the output terminals of the two inverting input OR gates; the signal input terminal of the transmission gate TGA is connected with the BGVCK or BGHCK of the external global bidirectional clock signal, and the signal input terminal of the transmission gate TGB is connected with the external global bidirectional clock signal Connect to GVCK or GHCK of the clock signal. 2. the data shift transmission unit circuit in the silicon-based microdisplay integrated asynchronous transmission shift register circuit according to claim 1, is characterized in that, in the line scan shift register circuit, the signal input terminal of transmission gate TGA and The BGVCK of the external global bidirectional clock signal is connected, and the signal input terminal of the transmission gate TGB is connected with the GVCK of the external global bidirectional clock signal. In the column scanning shift register circuit, the signal input terminal of the transmission gate TGA is connected with the BGHCK of the external global bidirectional clock signal The signal input terminal of the transmission gate TGB is connected with the GHCK of the external global bidirectional clock signal. 3. a silicon-based microdisplay integrated asynchronous transmission shift register circuit that uses the unit circuit described in claim 1 to form, it is characterized in that described integrated asynchronous transmission shift register circuit is made up of M x N described in claim 1 The data shift transmission unit circuit is composed of M and N respectively representing the column resolution and row resolution of the silicon-based microdisplay, that is, the column resolution is realized by M said data shift transmission unit circuits, and the row resolution is realized by N said data shift transmission unit circuits are implemented. 4. The data shift transmission unit circuit according to claim 1, wherein M data shift transmission unit circuits form an M-level horizontal scanning shift register circuit, wherein the data input end of the first-level unit circuit is It is connected to the external horizontal synchronous signal HS, and connected to the input terminal of the horizontal synchronous inverter at the same time, and the output terminal of the horizontal synchronous inverter is connected to one input terminal of the two inverting input OR gates; the data of each subsequent unit circuit The input ends are all connected to the data output ends of the unit circuit in front of it, and the other input end of the two inverting input OR gates is connected to the inverting output end of the current stage to form an M-level horizontal scanning shift register circuit of the silicon-based microdisplay. 5. The data shift transmission unit circuit according to claim 1, characterized in that N-level vertical scanning shift register circuits are formed by N data shift transmission unit circuits, wherein the current level data input of the first level unit circuit The terminal is connected to the external vertical synchronous signal VS, and is connected to the input terminal of the vertical synchronous inverter at the same time, and the output terminal of the vertical synchronous inverter is connected to one input terminal of the two inverting input OR gates; the subsequent unit circuits The data input terminals are all connected to the data output terminals of the unit circuit in front of it, and the other input terminal of the two inverting input OR gates is connected to the inverting output terminal of the current stage to form an N-level vertical scanning shift register circuit of the silicon-based microdisplay. 6. A method for realizing the function of a silicon-based microdisplay integrated asynchronous transmission shift register circuit, through the following steps successively: First, using the CMOS process to integrate the M x N data shift transmission unit circuits in claim 1 and the silicon-based microdisplay on one chip; Second, after the silicon-based micro-display receives the video signal, the field synchronous signal VS is active at high level, and is added to the data input end of the D flip-flop (3) of the first-level unit circuit (8) of the N-level line scan shift register , so that the transmission gates TGA (5) and TGB (2) inverting control input terminals are at low level, the field synchronous inverter (6) outputs low level, and drives two inverting input OR gates (4) to output high level , so that the positive-phase control input terminals of the transmission gates TGA(5) and TGB(2) are at high level, and the transmission gates TGA(5) and TGB(2) are in the open state. When the clock arrives, the data output terminal of this stage outputs a high level level; The 3rd, in the second global clock period, the data input terminal of this stage D flip-flop (3) becomes low level, the positive phase output terminal is high level, and the reverse output terminal is low level; The NOR gate (1) and the two inverting input OR gates (4) drive the transmission gates TGA (5) and TGB (2) to be always on, and the global bidirectional clock signal will cause the D flip-flop (3) to flip to the positive phase The output terminal is a low level, and the inverting output terminal is a stable state of a high level; Fourth, since the data output of the previous stage and the data output of this stage are both low level, and the inverting output of the previous stage and the inverting output of this stage are both high level, so the transmission gates TGA (5) and TGB (2) are closed state, the D flip-flop (3) is in a dormant waiting state; The 5th, the high level that the present stage data output end of the first stage unit circuit (8) outputs, adds the D flip-flop (3) of the data shift transmission unit circuit (10) of the row scan shift register circuit thereafter ) to the data input end of the unit circuit (8) to repeat the working process of the second to fourth steps of the first-level unit circuit (8), and to transmit a high-level pulse to the data input end of each unit circuit in the following order to complete a Line scanning process of frame image; Sixth, during the output of a certain level unit circuit (10) of the N-level row scanning shift register circuit is a high level period, the corresponding row synchronous signal HS is high level, and is added to the M-level column scanning shift register The data input terminal of the D flip-flop (3) in the first stage unit circuit (9) of the circuit; repeat the steps from the second to the fifth in front, and scan the data shift transmission unit circuit (9) of the shift register circuit by the M-level column ) sequentially transmit the high level to complete the column scanning process of a row of images.