CN101399246B - Substrate Structure and Manufacturing Method of Flip Chip Package - Google Patents
Substrate Structure and Manufacturing Method of Flip Chip Package Download PDFInfo
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- CN101399246B CN101399246B CN 200710153286 CN200710153286A CN101399246B CN 101399246 B CN101399246 B CN 101399246B CN 200710153286 CN200710153286 CN 200710153286 CN 200710153286 A CN200710153286 A CN 200710153286A CN 101399246 B CN101399246 B CN 101399246B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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Abstract
The invention relates to a flip chip package substrate structure and a manufacturing method thereof, wherein the package substrate comprises: a substrate body, wherein a circuit layer is arranged on one surface of the substrate body and comprises a plurality of circuits and a plurality of electric connection pads, and the electric connection pads are higher than the circuits; an insulating protective layer disposed on the surface of the substrate body and having a plurality of protective layer openings for exposing the electrical connection pads; and a conductive layer disposed between the circuits and the substrate body and between the pads and the substrate body, wherein the pads are formed by electroplating through the conductive layer, the pads have a height greater than that of the insulating protective layer, and the openings of the protective layer have a size greater than or equal to that of the pads. Therefore, the packaging substrate structure can be applied to a flip chip packaging structure with fine pitch.
Description
Technical field
The present invention relates to a kind of package substrate construction and method for making thereof, refer to a kind of package substrate construction and method for making thereof that is applicable to the thin space composite packing structure especially.
Background technology
Along with the manufacture of semiconductor ability constantly upwards promotes, the function of semiconductor chip is become stronger day by day and is tending towards complicated, and the volume of transmitted data of semiconductor chip also constantly increases simultaneously, thus semiconductor chip institute must the also increase thereupon of pin (pin) number.
Because chip technology is constantly towards high frequency, the development of high pin number, requirement on tradition routing encapsulation (WireBonding) technology can't satisfy electrically, compared to the technology of traditional routing encapsulation, chip package be adopt crystal face down by Solder Bumps as chip and substrate electric connection technology.In addition, the I/O contact feet can be distributed in the surface of entire chip, can increase substantially the quantity of chip signal I/O end points, can shorten the path of current signal transmission simultaneously, and can reduce interference of noise, improve heat-sinking capability and reduce encapsulation volume.Therefore, the chip package technology becomes the mainstream technology in market gradually.
Existing base plate for packaging sees also Fig. 1.The surface of this base plate for packaging 1 has a line layer, comprises a plurality of circuits 11 and a plurality of electric connection pads 12, and has a welding resisting layer 13, has a plurality of perforates 131, and appearing electric connection pad 12, and bore size 131 is less than the size of electric connection pad 12.In addition, utilize in this electric connection pad 12 surfaces modes of coating or printing form solder projection 14,14 ', so that base plate for packaging 1 can pass through this solder projection 14,14 ' electrically connect with a chip (scheming not show).
In addition, another existing base plate for packaging sees also Fig. 2.The surface of this base plate for packaging 2 has a line layer, comprise a plurality of circuits 21 and a plurality of electric connection pads 22, and has a welding resisting layer 23, have a plurality of perforates 231, to appear electric connection pad 22, and perforate 231 sizes are greater than the size of electric connection pad 22, so that base plate for packaging 2 can electrically connect with this chip (figure does not show) by being disposed at the solder projection on the chip electrode pad.
Chip must be filled bottom glue material with after base plate for packaging is connected in the space between chip and the base plate for packaging, in order to fixed chip and promote reliability.Subsequently, via curing, just can reach the purpose of fixed chip and lifting encapsulating structure reliability.
Though the structure on base plate for packaging 1 surface can reach the purpose of electric connection among Fig. 1, coating or the formed solder projection 14,14 of mode of printing ' quality control be difficult for, cause solder projection 14,14 ' the height and the consistency of size not good.In addition, when base plate for packaging 2 forms electrical contact with chip among Fig. 2, then can reduce its height, and influence the quality that follow-up bottom glue material is filled, reduce the reliability of product then because of solder projection is fills up in the gap of perforate 231 and electric connection pad 22.In addition, if improve the solder projection height, certainly will raise the cost because of increasing the scolder consumption.
The method for making of above-mentioned prior art and structure are unfavorable for the making of thin bump pitch (fine bump pitch), because be not easy to control when the convex pads surface forms solder projection its height, and height is not good with the consistency of size, to form for the crystal-covering connection structure with most I/O contacts with chip for base plate for packaging, often take place easily not form contact because of part solder projection height is not enough with chip chamber, or take place easily to form bridge joint because of the excessive and adjacent contact of part solder bump size, so all cause the non-defective unit chip to scrap along with the chip package failure, on the other hand, semiconductor chip more develops to advanced technology, its chip body dielectric coefficient is lower, and the intensity of the anti-stress of chip body is also low thereupon; Not good because of the consistency of solder projection height and size, even finish the crystal-covering connection structure with most I/O contacts, its stress that chip is bestowed is bigger, also easier chip is damaged and scraps.Again on the one hand, also not good when being thin base because of the consistency of solder projection height and size as if substrate, and make substrate stress inequality cause damage easily, yield reduces.
Moreover, the density of laying electronic pads along with semiconductor chip surface improves, the solder bump size of chip and base plate for packaging also need be dwindled thereupon, also dwindle and descend and chip and base plate for packaging connect the clearance height of postpone along with contact size, cause when filling bottom glue material, the glue material is difficult for being filled in the space between base plate for packaging and the chip fully and produces hole, and then serious problems such as chip explosion take place.
Therefore, need a kind of package substrate construction that can be applied to thin space and can improve the problems referred to above at present badly.
Summary of the invention
The shortcoming of prior art in view of the above, main purpose of the present invention is to propose a kind of package substrate construction and method for making thereof, can be applied to thin space, improve the primer filling quality of composite packing structure and be unfavorable for carrying out the problem that solder bump forms contact, with the lifting production reliability, and save cost.
For reaching above-mentioned purpose, the invention provides a kind of crystal-coated packing substrate plate structure, it comprises: a substrate body, surface thereof have a line layer, comprise a plurality of circuits and a plurality of electric connection pad, and those electric connection pads are higher than those circuits; One insulating protective layer is arranged at the surface of this substrate body, and has a plurality of protective layer perforates, to appear those electric connection pads; An and conductive layer; be disposed between those circuits and this substrate body; and between those electric connection pads and this substrate body; wherein those electric connection pads are to electroplate formation by this conductive layer; and the height of those electric connection pads is greater than the height of this insulating protective layer, and those protective layer bore size are more than or equal to the size of those electric connection pads.
In the said structure, be preferably, the height of those electric connection pads is greater than the insulation protection layer height, inferior good be that the height of those electric connection pads is equal to or slightly less than the insulation protection layer height.
In the said structure, the multiple configurable surface-treated layers in those electric connection pads surface can be selected from nickel/gold, have organizational security to weld one of them of film (OSP), nickel/palladium/gold, tin, scolding tin, silver and above-mentioned combination institute cohort group.
In the said structure, this insulating protective layer can be welding resisting layer or dielectric layer.
The present invention also provides a kind of method for making of crystal-coated packing substrate plate, and it comprises: a substrate body is provided, and forms a thin metal or a nonmetallic conductive layer in the dielectric layer surface of this substrate body; Form one first resistance layer in this conductive layer surface, and form a plurality of open regions, to appear the partially conductive layer in first resistance layer; In open region, form a line layer, comprise a plurality of circuits and a plurality of electric connection pad; Form one second resistance layer in the first resistance layer surface, and form a plurality of perforates, to appear those electric connection pads in second resistance layer; Form a connection gasket protective layer in those electric connection pad surfaces; Remove second resistance layer and first resistance layer, and carry out microetch to remove the conductive layer of its covering, those circuits of attenuate make those electric connection pads be higher than those circuits simultaneously; Remove this connection gasket protective layer; And form an insulating protective layer in this substrate body surface, and and form a plurality of protective layer perforates in this insulating protective layer, appearing those electric connection pads, and those protective layer bore size are more than or equal to the size of those electric connection pads.
In the above-mentioned method for making, this connection gasket protective layer can utilize to electroplate and is formed at those electric connection pad surfaces, its material be preferably tin, nickel, gold, silver, chromium and titanium one of them.
In the above-mentioned method for making, those electric connection pads can carry out surface treatment again, can be selected from nickel/gold, organizational security weldering film (OSP) is arranged, change nickel soak gold, nickel/palladium/gold, tin, scolding tin, silver and above-mentioned combination institute cohort group one of them.
In the above-mentioned method for making, this insulating protective layer can be welding resisting layer or dielectric layer.
In view of the above, package substrate construction provided by the present invention and method for making thereof can be applicable to composite packing structure, particularly when circuit when thin space develops, its electric connection pad is owing to have enough height, help reducing the scolder consumption, and be easy to fill bottom glue material, moreover, electric connection pad has enough height can be avoided again because of the clearance height of chip and base plate for packaging reduces, and defectives such as bad or hole take place to fill when making follow-up filling primer.
On the other hand, the formed electric connection pad of the present invention, because be easy to control its height, and height is good with the consistency of size, to form for the crystal-covering connection structure with most I/O contacts with chip for base plate for packaging, can avoid taking place easily in the prior art base plate for packaging and chip chamber and not form contact because of part solder projection height is not enough, also avoid taking place easily so promptly avoiding causing the non-defective unit chip to scrap along with the chip package failure because of the excessive and adjacent contact of part solder bump size forms defectives such as bridge joint.Moreover, not good if the envelope substrate when being thin base, also can be avoided because of the consistency of solder projection height and size, and make envelope substrate stress inequality cause damage easily, the defective of yield reduction.
It is above-mentioned to sum up, and package substrate construction provided by the present invention and method for making thereof are simple, thereby can improve and produce yield and reduce cost.
Description of drawings
Fig. 1 is the base plate for packaging cutaway view of prior art;
Fig. 2 is another base plate for packaging cutaway view of prior art;
Fig. 3 A to 3I ' is the making flow process cutaway view of the base plate for packaging of the embodiment of the invention.
Symbol description among the figure
1,2 base plate for packaging, 11,21,33 circuits
12,22,34 electric connection pads, 13,23 welding resisting layers
131,231,371 perforate 14,14 ' solder projections
30 substrate body, 31 conductive layers
32 first resistance layers, 321 open regions
351 perforates of 35 second resistance layers
36 connection gasket protective layers, 37 insulating protective layers
371 protective layer perforates, 38 surface-treated layers
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification disclosed.The present invention also can be implemented or be used by other different specific embodiment, and the every details in this specification also can be carried out various modifications and change based on different viewpoints and application under not departing from spirit of the present invention.
See also Fig. 3, the making flow process cutaway view of package substrate construction of the present invention.
At first, as shown in Figure 3A, provide a substrate body 30, and form a thin metal or a nonmetallic conductive layer 31 in the dielectric layer surface of this substrate body 30.
Shown in Fig. 3 B, form one first resistance layer 32 in conductive layer 31 surfaces, and on first resistance layer 32, form a plurality of open regions 321, to appear partially conductive layer 31.
Subsequently, shown in Fig. 3 C, via conductive layer 31, electroplate in open region 321 and form a line layer, comprise a plurality of circuits 33 and a plurality of electric connection pad 34, wherein, the circuit 33 of present embodiment and electric connection pad 34 materials are all copper.
Shown in Fig. 3 D, form one second resistance layer 35 in first resistance layer, 32 surfaces, and on second resistance layer 35, form a plurality of perforates 351, to appear those electric connection pads 34.
Then, shown in Fig. 3 E, electroplate a connection gasket protective layer 36 in those electric connection pad 34 surfaces, its material be preferably tin, nickel, gold, silver, chromium, titanium one of them, the material of connection gasket protective layer 36 is a tin in the present embodiment.
Shown in Fig. 3 F, remove second resistance layer and first resistance layer, and carry out microetch to remove the conductive layer of its covering, those circuits 33 of attenuate make those electric connection pads 34 be higher than those circuits 33 simultaneously.
Shown in Fig. 3 G, remove the connection gasket protective layer, to finish the structure that electric connection pad 34 is higher than circuit 33.
At last; shown in Fig. 3 H; form an insulating protective layer 37 in substrate body 30 surfaces; and in a plurality of protective layer perforates 371 of these insulating protective layer 37 formation; to appear those electric connection pads 34; and those protective layer perforate 371 sizes perhaps equal the size of those electric connection pads 34 greater than the size of those electric connection pads 34, shown in Fig. 3 H '.In the present embodiment, the height of those electric connection pads 34 is greater than insulating protective layer 37 height.
The present invention also provides a kind of structure of base plate for packaging, and it comprises: a substrate body 30, and surface thereof has a line layer, comprises a plurality of circuits 33 and a plurality of electric connection pad 34, and those electric connection pads 34 are higher than those circuits 33; An and insulating protective layer 37; be arranged at the surface of this substrate body 30; and have a plurality of protective layer perforates 371; to appear those electric connection pads 34; and those protective layer perforate 371 sizes are greater than the size of those electric connection pads 34; see Fig. 3 H, or equal the size of those electric connection pads 34, see Fig. 3 H '.
In addition, shown in Fig. 3 I or Fig. 3 I ', the electric connection pad 34 of base plate for packaging of the present invention also can carry out surface treatment.Wherein, the optional free nickel of surface-treated layer 38 materials of electric connection pad 34/gold, organizational security weldering film arranged, change one of them that nickel soaks gold, nickel/palladium/gold, tin, scolding tin, Pb-free solder, silver and above-mentioned combination institute cohort group.In present embodiment, the material of this surface-treated layer 38 is nickel/gold.
In view of the above, package substrate construction provided by the present invention and method for making thereof can be applicable to composite packing structure, particularly when circuit when thin space develops, its electric connection pad is owing to have enough height, help reducing the scolder consumption, and be easy to fill bottom glue material, moreover, electric connection pad has enough height can be avoided again because of the clearance height of chip and base plate for packaging reduces, and defectives such as bad or hole take place to fill when making follow-up filling primer.
On the other hand, the formed electric connection pad of the present invention, because be easy to control its height, and height is good with the consistency of size, to form for the crystal-covering connection structure with most I/O contacts with chip for base plate for packaging, can avoid taking place easily in the prior art base plate for packaging and chip chamber and not form contact because of part solder projection height is not enough, also avoid taking place easily so promptly avoiding causing the non-defective unit chip to scrap along with the chip package failure because of the excessive and adjacent contact of part solder bump size forms defectives such as bridge joint.Moreover, not good if the envelope substrate when being thin base, also can be avoided because of the consistency of solder projection height and size, and make envelope substrate stress inequality cause damage easily, the defective of yield reduction.
The foregoing description is only given an example for convenience of description, and the interest field that the present invention advocated should be as the criterion so that the scope of claims is described certainly, but not only limits to the foregoing description.
Claims (5)
1. the method for making of a crystal-coated packing substrate plate is characterized in that, comprising:
One substrate body is provided, and forms a conductive layer in a surface of this substrate body;
Form one first resistance layer in this conductive layer surface, and form a plurality of open regions, to appear the partially conductive layer in first resistance layer;
In open region, form a line layer, comprise a plurality of circuits and a plurality of electric connection pad;
Form one second resistance layer in the first resistance layer surface, and form a plurality of perforates, to appear those electric connection pads in second resistance layer;
Form a connection gasket protective layer in those electric connection pad surfaces;
Remove second resistance layer and first resistance layer, and carry out microetch to remove the conductive layer of its covering, those circuits of attenuate make those electric connection pads be higher than those circuits simultaneously;
Remove this connection gasket protective layer; And
Form an insulating protective layer in this substrate body surface, and form a plurality of protective layer perforates, to appear those electric connection pads in this insulating protective layer.
2. method for making as claimed in claim 1, wherein, this connection gasket protective layer utilizes galvanoplastic to form.
3. method for making as claimed in claim 1, wherein, the material of this connection gasket protective layer be tin, nickel, gold, silver, chromium and titanium one of them.
4. method for making as claimed in claim 1 wherein, also is included in those electric connection pads and forms a surface-treated layer, be selected from nickel/gold, organizational security weldering film is arranged, change nickel soak gold, nickel/palladium/gold, tin, scolding tin, silver and above-mentioned combination institute cohort group one of them.
5. method for making as claimed in claim 1, wherein, this insulating protective layer be welding resisting layer and dielectric layer one of them, and those protective layer bore size greater than and equal those electric connection pad sizes one of them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710153286 CN101399246B (en) | 2007-09-29 | 2007-09-29 | Substrate Structure and Manufacturing Method of Flip Chip Package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710153286 CN101399246B (en) | 2007-09-29 | 2007-09-29 | Substrate Structure and Manufacturing Method of Flip Chip Package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101399246A CN101399246A (en) | 2009-04-01 |
| CN101399246B true CN101399246B (en) | 2011-12-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200710153286 Expired - Fee Related CN101399246B (en) | 2007-09-29 | 2007-09-29 | Substrate Structure and Manufacturing Method of Flip Chip Package |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102398886B (en) * | 2010-09-15 | 2014-07-23 | 矽品精密工业股份有限公司 | Encapsulation structure with microelectromechanical components and its manufacturing method |
| JP2017076698A (en) * | 2015-10-15 | 2017-04-20 | 日本特殊陶業株式会社 | Wiring board and manufacturing method of the same |
| TWI607676B (en) * | 2016-06-08 | 2017-12-01 | 矽品精密工業股份有限公司 | Package substrate and its electronic package and the manufacture thereof |
| CN108289388A (en) * | 2017-12-07 | 2018-07-17 | 江门崇达电路技术有限公司 | The undesirable PCB production methods of tin in a kind of prevention |
| CN112885806B (en) * | 2019-11-29 | 2022-03-08 | 长鑫存储技术有限公司 | Substrate and preparation method thereof, chip packaging structure and packaging method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1343089A (en) * | 2000-07-07 | 2002-04-03 | 株式会社东芝 | Printed circuit board with channel and manufacturing method thereof |
| US20060244140A1 (en) * | 2005-04-28 | 2006-11-02 | Wen-Hung Hu | Conductive bump structure of circuit board and method for forming the same |
| CN1941352A (en) * | 2005-09-27 | 2007-04-04 | 三星电机株式会社 | Semiconductor package substrate having different thicknesses between wire bonding pad and ball pad and method for fabricating the same |
-
2007
- 2007-09-29 CN CN 200710153286 patent/CN101399246B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1343089A (en) * | 2000-07-07 | 2002-04-03 | 株式会社东芝 | Printed circuit board with channel and manufacturing method thereof |
| US20060244140A1 (en) * | 2005-04-28 | 2006-11-02 | Wen-Hung Hu | Conductive bump structure of circuit board and method for forming the same |
| CN1941352A (en) * | 2005-09-27 | 2007-04-04 | 三星电机株式会社 | Semiconductor package substrate having different thicknesses between wire bonding pad and ball pad and method for fabricating the same |
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| Publication number | Publication date |
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| CN101399246A (en) | 2009-04-01 |
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Owner name: XINXING ELECTRONICS CO., LTD. Free format text: FORMER OWNER: QUANMAO PRECISION SCIENCE + TECHNOLOGY CO., LTD. Effective date: 20111020 |
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Effective date of registration: 20111020 Address after: China Taiwan Taoyuan County Applicant after: UNIMICRON TECHNOLOGY Corp. Address before: Hsinchu, Taiwan, China Applicant before: PHOENIX PRECISION TECHNOLOGY CORPORATION |
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